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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.90 98.23 93.91 97.02 93.02 96.33 99.77 92.99


Total test records in report: 1098
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T310 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_intg_err.829652598 Oct 15 11:38:53 AM UTC 24 Oct 15 11:38:56 AM UTC 24 163201945 ps
T1004 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/8.edn_same_csr_outstanding.3513073479 Oct 15 11:38:54 AM UTC 24 Oct 15 11:38:57 AM UTC 24 87756460 ps
T1005 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_rw.1659082192 Oct 15 11:38:54 AM UTC 24 Oct 15 11:38:57 AM UTC 24 21792351 ps
T1006 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/9.edn_intr_test.3289426931 Oct 15 11:38:54 AM UTC 24 Oct 15 11:38:57 AM UTC 24 12554050 ps
T1007 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.4029876119 Oct 15 11:38:54 AM UTC 24 Oct 15 11:38:57 AM UTC 24 79198914 ps
T1008 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/9.edn_same_csr_outstanding.1682853304 Oct 15 11:38:54 AM UTC 24 Oct 15 11:38:57 AM UTC 24 72435174 ps
T1009 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.981416641 Oct 15 11:38:54 AM UTC 24 Oct 15 11:38:58 AM UTC 24 106210782 ps
T1010 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/10.edn_intr_test.120693062 Oct 15 11:38:56 AM UTC 24 Oct 15 11:38:58 AM UTC 24 13295616 ps
T1011 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/10.edn_same_csr_outstanding.2865943744 Oct 15 11:38:56 AM UTC 24 Oct 15 11:38:59 AM UTC 24 40282052 ps
T1012 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_intg_err.1155183768 Oct 15 11:38:54 AM UTC 24 Oct 15 11:38:59 AM UTC 24 964754985 ps
T1013 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_errors.702758454 Oct 15 11:38:54 AM UTC 24 Oct 15 11:38:59 AM UTC 24 245386411 ps
T1014 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_errors.719030700 Oct 15 11:38:54 AM UTC 24 Oct 15 11:38:59 AM UTC 24 496841322 ps
T1015 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_intg_err.2229574864 Oct 15 11:38:56 AM UTC 24 Oct 15 11:38:59 AM UTC 24 253674652 ps
T1016 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/12.edn_intr_test.2004503620 Oct 15 11:38:59 AM UTC 24 Oct 15 11:39:01 AM UTC 24 12642269 ps
T1017 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3504825088 Oct 15 11:38:56 AM UTC 24 Oct 15 11:38:59 AM UTC 24 70775688 ps
T1018 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/11.edn_intr_test.3489157761 Oct 15 11:38:57 AM UTC 24 Oct 15 11:39:00 AM UTC 24 18950229 ps
T282 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_rw.3649441883 Oct 15 11:38:57 AM UTC 24 Oct 15 11:39:00 AM UTC 24 21301719 ps
T1019 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_intg_err.771052490 Oct 15 11:38:56 AM UTC 24 Oct 15 11:39:00 AM UTC 24 81867715 ps
T1020 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_errors.1750974211 Oct 15 11:38:56 AM UTC 24 Oct 15 11:39:00 AM UTC 24 101573965 ps
T1021 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/11.edn_same_csr_outstanding.1666222938 Oct 15 11:38:57 AM UTC 24 Oct 15 11:39:00 AM UTC 24 62711411 ps
T1022 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_rw.561336133 Oct 15 11:38:59 AM UTC 24 Oct 15 11:39:01 AM UTC 24 72567706 ps
T1023 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3916011954 Oct 15 11:38:57 AM UTC 24 Oct 15 11:39:00 AM UTC 24 106505802 ps
T1024 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3863498355 Oct 15 11:38:59 AM UTC 24 Oct 15 11:39:01 AM UTC 24 205185432 ps
T1025 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_intg_err.3345544393 Oct 15 11:38:59 AM UTC 24 Oct 15 11:39:02 AM UTC 24 67886394 ps
T1026 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/12.edn_same_csr_outstanding.2390342549 Oct 15 11:38:59 AM UTC 24 Oct 15 11:39:02 AM UTC 24 32713885 ps
T1027 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_errors.1043174803 Oct 15 11:38:57 AM UTC 24 Oct 15 11:39:02 AM UTC 24 85738994 ps
T1028 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_errors.3685329146 Oct 15 11:38:59 AM UTC 24 Oct 15 11:39:02 AM UTC 24 83290822 ps
T1029 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/13.edn_intr_test.821916186 Oct 15 11:39:00 AM UTC 24 Oct 15 11:39:02 AM UTC 24 14746290 ps
T1030 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_rw.3871673883 Oct 15 11:39:00 AM UTC 24 Oct 15 11:39:03 AM UTC 24 36081940 ps
T1031 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/14.edn_intr_test.2031893558 Oct 15 11:39:00 AM UTC 24 Oct 15 11:39:03 AM UTC 24 13764648 ps
T283 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_rw.1258944286 Oct 15 11:39:00 AM UTC 24 Oct 15 11:39:03 AM UTC 24 14734019 ps
T1032 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/13.edn_same_csr_outstanding.1252159725 Oct 15 11:39:00 AM UTC 24 Oct 15 11:39:03 AM UTC 24 24114358 ps
T1033 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.853340203 Oct 15 11:39:00 AM UTC 24 Oct 15 11:39:03 AM UTC 24 142097193 ps
T1034 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_intg_err.2079651924 Oct 15 11:39:00 AM UTC 24 Oct 15 11:39:03 AM UTC 24 49811350 ps
T1035 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/14.edn_same_csr_outstanding.279951221 Oct 15 11:39:00 AM UTC 24 Oct 15 11:39:03 AM UTC 24 73948520 ps
T1036 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_rw.2795306983 Oct 15 11:39:02 AM UTC 24 Oct 15 11:39:04 AM UTC 24 20177816 ps
T1037 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/15.edn_intr_test.1484742019 Oct 15 11:39:02 AM UTC 24 Oct 15 11:39:04 AM UTC 24 21084219 ps
T1038 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.747237467 Oct 15 11:39:01 AM UTC 24 Oct 15 11:39:04 AM UTC 24 82806944 ps
T1039 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_errors.3721707155 Oct 15 11:39:00 AM UTC 24 Oct 15 11:39:04 AM UTC 24 49085982 ps
T1040 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/15.edn_same_csr_outstanding.1461294758 Oct 15 11:39:02 AM UTC 24 Oct 15 11:39:04 AM UTC 24 383357712 ps
T1041 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_errors.2790490757 Oct 15 11:39:02 AM UTC 24 Oct 15 11:39:05 AM UTC 24 77341036 ps
T1042 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_rw.1031015624 Oct 15 11:39:03 AM UTC 24 Oct 15 11:39:05 AM UTC 24 12474832 ps
T1043 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.4214433436 Oct 15 11:39:03 AM UTC 24 Oct 15 11:39:05 AM UTC 24 19864344 ps
T1044 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_intg_err.1604645158 Oct 15 11:39:00 AM UTC 24 Oct 15 11:39:05 AM UTC 24 241951776 ps
T1045 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/16.edn_intr_test.115142780 Oct 15 11:39:03 AM UTC 24 Oct 15 11:39:05 AM UTC 24 16618260 ps
T1046 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/16.edn_same_csr_outstanding.2570952577 Oct 15 11:39:03 AM UTC 24 Oct 15 11:39:05 AM UTC 24 64351157 ps
T1047 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_intg_err.2125217675 Oct 15 11:39:02 AM UTC 24 Oct 15 11:39:06 AM UTC 24 309691279 ps
T1048 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_intg_err.937993182 Oct 15 11:39:03 AM UTC 24 Oct 15 11:39:06 AM UTC 24 627580464 ps
T1049 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/17.edn_intr_test.2646963745 Oct 15 11:39:05 AM UTC 24 Oct 15 11:39:07 AM UTC 24 15747297 ps
T1050 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_rw.1067733372 Oct 15 11:39:05 AM UTC 24 Oct 15 11:39:07 AM UTC 24 16098204 ps
T1051 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_rw.667205735 Oct 15 11:39:05 AM UTC 24 Oct 15 11:39:07 AM UTC 24 17100666 ps
T1052 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/17.edn_same_csr_outstanding.3990677341 Oct 15 11:39:05 AM UTC 24 Oct 15 11:39:07 AM UTC 24 82769795 ps
T1053 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3304434726 Oct 15 11:39:04 AM UTC 24 Oct 15 11:39:07 AM UTC 24 54579298 ps
T1054 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/18.edn_intr_test.1009570954 Oct 15 11:39:05 AM UTC 24 Oct 15 11:39:07 AM UTC 24 47070652 ps
T1055 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/18.edn_same_csr_outstanding.3793464314 Oct 15 11:39:05 AM UTC 24 Oct 15 11:39:07 AM UTC 24 124102051 ps
T1056 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_errors.2858916784 Oct 15 11:39:03 AM UTC 24 Oct 15 11:39:08 AM UTC 24 203840307 ps
T1057 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_intg_err.116334094 Oct 15 11:39:05 AM UTC 24 Oct 15 11:39:08 AM UTC 24 684514353 ps
T1058 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/19.edn_intr_test.4252752491 Oct 15 11:39:06 AM UTC 24 Oct 15 11:39:08 AM UTC 24 58018524 ps
T1059 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3253010936 Oct 15 11:39:05 AM UTC 24 Oct 15 11:39:08 AM UTC 24 104074932 ps
T1060 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/20.edn_intr_test.3202370594 Oct 15 11:39:06 AM UTC 24 Oct 15 11:39:08 AM UTC 24 153663330 ps
T1061 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_rw.1920029703 Oct 15 11:39:06 AM UTC 24 Oct 15 11:39:08 AM UTC 24 41029476 ps
T1062 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_errors.1117419575 Oct 15 11:39:04 AM UTC 24 Oct 15 11:39:08 AM UTC 24 177581961 ps
T1063 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_errors.3726397031 Oct 15 11:39:05 AM UTC 24 Oct 15 11:39:08 AM UTC 24 98243865 ps
T1064 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1047653818 Oct 15 11:39:06 AM UTC 24 Oct 15 11:39:08 AM UTC 24 43628972 ps
T1065 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/19.edn_same_csr_outstanding.269449892 Oct 15 11:39:06 AM UTC 24 Oct 15 11:39:08 AM UTC 24 29913876 ps
T1066 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3071530204 Oct 15 11:39:06 AM UTC 24 Oct 15 11:39:08 AM UTC 24 81881831 ps
T1067 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_intg_err.3317246235 Oct 15 11:39:04 AM UTC 24 Oct 15 11:39:09 AM UTC 24 87409679 ps
T1068 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/21.edn_intr_test.301836272 Oct 15 11:39:07 AM UTC 24 Oct 15 11:39:09 AM UTC 24 21376739 ps
T1069 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/22.edn_intr_test.145054962 Oct 15 11:39:07 AM UTC 24 Oct 15 11:39:09 AM UTC 24 51044280 ps
T1070 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_intg_err.1599496032 Oct 15 11:39:06 AM UTC 24 Oct 15 11:39:09 AM UTC 24 89380911 ps
T1071 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/25.edn_intr_test.2569132496 Oct 15 11:39:07 AM UTC 24 Oct 15 11:39:09 AM UTC 24 21686960 ps
T1072 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/24.edn_intr_test.724062758 Oct 15 11:39:07 AM UTC 24 Oct 15 11:39:09 AM UTC 24 30996872 ps
T1073 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/27.edn_intr_test.3257266368 Oct 15 11:39:07 AM UTC 24 Oct 15 11:39:09 AM UTC 24 23574492 ps
T1074 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/23.edn_intr_test.2174777908 Oct 15 11:39:07 AM UTC 24 Oct 15 11:39:10 AM UTC 24 59853973 ps
T1075 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/26.edn_intr_test.2727535700 Oct 15 11:39:07 AM UTC 24 Oct 15 11:39:10 AM UTC 24 14480458 ps
T1076 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/28.edn_intr_test.4067987981 Oct 15 11:39:08 AM UTC 24 Oct 15 11:39:10 AM UTC 24 16178901 ps
T1077 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_errors.3366597655 Oct 15 11:39:06 AM UTC 24 Oct 15 11:39:10 AM UTC 24 94999935 ps
T1078 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/31.edn_intr_test.109239745 Oct 15 11:39:09 AM UTC 24 Oct 15 11:39:11 AM UTC 24 12932114 ps
T1079 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/33.edn_intr_test.2409256089 Oct 15 11:39:09 AM UTC 24 Oct 15 11:39:11 AM UTC 24 52999025 ps
T1080 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/29.edn_intr_test.1861523317 Oct 15 11:39:09 AM UTC 24 Oct 15 11:39:11 AM UTC 24 12324669 ps
T1081 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/30.edn_intr_test.4176984869 Oct 15 11:39:09 AM UTC 24 Oct 15 11:39:11 AM UTC 24 50286229 ps
T1082 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/34.edn_intr_test.3209064410 Oct 15 11:39:09 AM UTC 24 Oct 15 11:39:11 AM UTC 24 43996834 ps
T1083 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/32.edn_intr_test.2624984098 Oct 15 11:39:09 AM UTC 24 Oct 15 11:39:11 AM UTC 24 30410174 ps
T1084 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/36.edn_intr_test.3318699636 Oct 15 11:39:09 AM UTC 24 Oct 15 11:39:11 AM UTC 24 37030958 ps
T1085 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/35.edn_intr_test.2914708974 Oct 15 11:39:09 AM UTC 24 Oct 15 11:39:11 AM UTC 24 75292949 ps
T1086 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/37.edn_intr_test.3238512469 Oct 15 11:39:09 AM UTC 24 Oct 15 11:39:11 AM UTC 24 34501564 ps
T1087 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/38.edn_intr_test.2409930904 Oct 15 11:39:09 AM UTC 24 Oct 15 11:39:11 AM UTC 24 11695856 ps
T1088 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/39.edn_intr_test.460153144 Oct 15 11:39:09 AM UTC 24 Oct 15 11:39:11 AM UTC 24 35915579 ps
T1089 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/40.edn_intr_test.4226231861 Oct 15 11:39:09 AM UTC 24 Oct 15 11:39:11 AM UTC 24 14444321 ps
T1090 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/41.edn_intr_test.2006467589 Oct 15 11:39:10 AM UTC 24 Oct 15 11:39:12 AM UTC 24 25251447 ps
T1091 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/43.edn_intr_test.2827662571 Oct 15 11:39:10 AM UTC 24 Oct 15 11:39:13 AM UTC 24 42841865 ps
T1092 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/44.edn_intr_test.2753818763 Oct 15 11:39:10 AM UTC 24 Oct 15 11:39:13 AM UTC 24 24161876 ps
T1093 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/45.edn_intr_test.3909716357 Oct 15 11:39:11 AM UTC 24 Oct 15 11:39:13 AM UTC 24 40986356 ps
T1094 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/46.edn_intr_test.373488536 Oct 15 11:39:11 AM UTC 24 Oct 15 11:39:13 AM UTC 24 13409769 ps
T1095 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/42.edn_intr_test.3980550701 Oct 15 11:39:10 AM UTC 24 Oct 15 11:39:13 AM UTC 24 17279012 ps
T1096 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/48.edn_intr_test.2835930622 Oct 15 11:39:11 AM UTC 24 Oct 15 11:39:13 AM UTC 24 34442238 ps
T1097 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/49.edn_intr_test.1552409779 Oct 15 11:39:11 AM UTC 24 Oct 15 11:39:13 AM UTC 24 42880615 ps
T1098 /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/47.edn_intr_test.3362329177 Oct 15 11:39:11 AM UTC 24 Oct 15 11:39:13 AM UTC 24 60734533 ps

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/0.edn_stress_all.1966557921
Short name T6
Test name
Test status
Simulation time 323310918 ps
CPU time 4.48 seconds
Started Oct 15 11:24:42 AM UTC 24
Finished Oct 15 11:24:47 AM UTC 24
Peak memory 229044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966557921 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.1966557921
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/0.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/6.edn_genbits.3705073182
Short name T49
Test name
Test status
Simulation time 61274997 ps
CPU time 1.99 seconds
Started Oct 15 11:25:15 AM UTC 24
Finished Oct 15 11:25:18 AM UTC 24
Peak memory 232156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705073182 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_genbits.3705073182
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/6.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/1.edn_sec_cm.3746489494
Short name T16
Test name
Test status
Simulation time 1052886700 ps
CPU time 6.76 seconds
Started Oct 15 11:24:54 AM UTC 24
Finished Oct 15 11:25:02 AM UTC 24
Peak memory 259764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746489494 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.3746489494
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/1.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/0.edn_alert.2343487083
Short name T23
Test name
Test status
Simulation time 34873148 ps
CPU time 1.66 seconds
Started Oct 15 11:24:44 AM UTC 24
Finished Oct 15 11:24:47 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343487083 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 0.edn_alert.2343487083
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/0.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/3.edn_disable_auto_req_mode.3386534597
Short name T43
Test name
Test status
Simulation time 30449946 ps
CPU time 1.9 seconds
Started Oct 15 11:25:04 AM UTC 24
Finished Oct 15 11:25:07 AM UTC 24
Peak memory 227856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386534597 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable_auto_req_mode.3386534597
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/3.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/1.edn_stress_all_with_rand_reset.2181764434
Short name T35
Test name
Test status
Simulation time 13194339819 ps
CPU time 72.18 seconds
Started Oct 15 11:24:48 AM UTC 24
Finished Oct 15 11:26:02 AM UTC 24
Peak memory 231308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2181764434 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_
with_rand_reset.2181764434
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/1.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/3.edn_genbits.1926391842
Short name T39
Test name
Test status
Simulation time 79136383 ps
CPU time 1.57 seconds
Started Oct 15 11:25:01 AM UTC 24
Finished Oct 15 11:25:03 AM UTC 24
Peak memory 229892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926391842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_genbits.1926391842
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/3.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/8.edn_disable_auto_req_mode.4018796797
Short name T90
Test name
Test status
Simulation time 39972155 ps
CPU time 1.3 seconds
Started Oct 15 11:25:25 AM UTC 24
Finished Oct 15 11:25:27 AM UTC 24
Peak memory 230088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018796797 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable_auto_req_mode.4018796797
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/8.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/23.edn_alert.281792911
Short name T109
Test name
Test status
Simulation time 89776176 ps
CPU time 1.51 seconds
Started Oct 15 11:26:04 AM UTC 24
Finished Oct 15 11:26:06 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281792911 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 23.edn_alert.281792911
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/23.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/0.edn_disable_auto_req_mode.53226037
Short name T9
Test name
Test status
Simulation time 28800363 ps
CPU time 1.67 seconds
Started Oct 15 11:24:45 AM UTC 24
Finished Oct 15 11:24:48 AM UTC 24
Peak memory 227928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53226037 -assert nopostproc +UVM_TESTNAME=edn_disab
le_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable_auto_req_mode.53226037
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/0.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/8.edn_alert.594115792
Short name T82
Test name
Test status
Simulation time 34276119 ps
CPU time 1.82 seconds
Started Oct 15 11:25:23 AM UTC 24
Finished Oct 15 11:25:26 AM UTC 24
Peak memory 227976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594115792 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 8.edn_alert.594115792
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/8.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/0.edn_disable.3693547074
Short name T24
Test name
Test status
Simulation time 12353585 ps
CPU time 1.37 seconds
Started Oct 15 11:24:45 AM UTC 24
Finished Oct 15 11:24:47 AM UTC 24
Peak memory 228284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693547074 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.3693547074
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/0.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/16.edn_disable.2134891376
Short name T94
Test name
Test status
Simulation time 19787731 ps
CPU time 1.28 seconds
Started Oct 15 11:25:46 AM UTC 24
Finished Oct 15 11:25:48 AM UTC 24
Peak memory 217736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134891376 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.2134891376
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/16.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/7.edn_alert_test.3646885947
Short name T22
Test name
Test status
Simulation time 83499993 ps
CPU time 1.21 seconds
Started Oct 15 11:25:21 AM UTC 24
Finished Oct 15 11:25:23 AM UTC 24
Peak memory 217216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646885947 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.3646885947
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/7.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/6.edn_alert.1820766330
Short name T57
Test name
Test status
Simulation time 25495817 ps
CPU time 1.74 seconds
Started Oct 15 11:25:17 AM UTC 24
Finished Oct 15 11:25:20 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820766330 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 6.edn_alert.1820766330
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/6.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/17.edn_disable_auto_req_mode.2855228694
Short name T167
Test name
Test status
Simulation time 95678254 ps
CPU time 1.66 seconds
Started Oct 15 11:25:50 AM UTC 24
Finished Oct 15 11:25:53 AM UTC 24
Peak memory 227856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855228694 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable_auto_req_mode.2855228694
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/17.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/9.edn_disable_auto_req_mode.1528242639
Short name T83
Test name
Test status
Simulation time 93773477 ps
CPU time 1.58 seconds
Started Oct 15 11:25:28 AM UTC 24
Finished Oct 15 11:25:31 AM UTC 24
Peak memory 227860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528242639 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable_auto_req_mode.1528242639
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/9.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/4.edn_tl_intg_err.3873175048
Short name T306
Test name
Test status
Simulation time 82552169 ps
CPU time 2 seconds
Started Oct 15 11:38:46 AM UTC 24
Finished Oct 15 11:38:49 AM UTC 24
Peak memory 216708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873175048 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.3873175048
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/4.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/32.edn_stress_all.1514495327
Short name T322
Test name
Test status
Simulation time 984594689 ps
CPU time 7.3 seconds
Started Oct 15 11:26:30 AM UTC 24
Finished Oct 15 11:26:38 AM UTC 24
Peak memory 228988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514495327 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.1514495327
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/32.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/7.edn_stress_all.3386871245
Short name T124
Test name
Test status
Simulation time 250263170 ps
CPU time 3.74 seconds
Started Oct 15 11:25:19 AM UTC 24
Finished Oct 15 11:25:23 AM UTC 24
Peak memory 229292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386871245 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.3386871245
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/7.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/6.edn_err.1398112434
Short name T212
Test name
Test status
Simulation time 33455107 ps
CPU time 1.32 seconds
Started Oct 15 11:25:17 AM UTC 24
Finished Oct 15 11:25:20 AM UTC 24
Peak memory 229772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398112434 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 6.edn_err.1398112434
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/6.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_aliasing.2440214242
Short name T276
Test name
Test status
Simulation time 68313211 ps
CPU time 1.73 seconds
Started Oct 15 11:38:40 AM UTC 24
Finished Oct 15 11:38:42 AM UTC 24
Peak memory 216756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440214242 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.2440214242
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/1.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/12.edn_disable.794709629
Short name T50
Test name
Test status
Simulation time 58247682 ps
CPU time 1.28 seconds
Started Oct 15 11:25:35 AM UTC 24
Finished Oct 15 11:25:37 AM UTC 24
Peak memory 227912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794709629 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.794709629
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/12.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/23.edn_disable.1415584417
Short name T188
Test name
Test status
Simulation time 23245127 ps
CPU time 0.98 seconds
Started Oct 15 11:26:05 AM UTC 24
Finished Oct 15 11:26:07 AM UTC 24
Peak memory 228036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415584417 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.1415584417
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/23.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/19.edn_alert.819678159
Short name T134
Test name
Test status
Simulation time 79156449 ps
CPU time 1.57 seconds
Started Oct 15 11:25:54 AM UTC 24
Finished Oct 15 11:25:56 AM UTC 24
Peak memory 232076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819678159 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 19.edn_alert.819678159
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/19.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/41.edn_alert.580553521
Short name T160
Test name
Test status
Simulation time 46866311 ps
CPU time 1.74 seconds
Started Oct 15 11:26:56 AM UTC 24
Finished Oct 15 11:26:59 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580553521 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 41.edn_alert.580553521
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/41.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/42.edn_disable_auto_req_mode.842572090
Short name T171
Test name
Test status
Simulation time 63542120 ps
CPU time 1.46 seconds
Started Oct 15 11:27:00 AM UTC 24
Finished Oct 15 11:27:02 AM UTC 24
Peak memory 227844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842572090 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable_auto_req_mode.842572090
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/42.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/16.edn_intr.1310233372
Short name T31
Test name
Test status
Simulation time 41920124 ps
CPU time 1.2 seconds
Started Oct 15 11:25:45 AM UTC 24
Finished Oct 15 11:25:47 AM UTC 24
Peak memory 229976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310233372 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 16.edn_intr.1310233372
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/16.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/3.edn_stress_all.4203113272
Short name T123
Test name
Test status
Simulation time 114445997 ps
CPU time 3.66 seconds
Started Oct 15 11:25:01 AM UTC 24
Finished Oct 15 11:25:05 AM UTC 24
Peak memory 229136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203113272 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.4203113272
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/3.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/12.edn_alert.474587774
Short name T91
Test name
Test status
Simulation time 347835661 ps
CPU time 1.96 seconds
Started Oct 15 11:25:35 AM UTC 24
Finished Oct 15 11:25:38 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474587774 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 12.edn_alert.474587774
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/12.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/134.edn_alert.840645915
Short name T301
Test name
Test status
Simulation time 53040879 ps
CPU time 1.41 seconds
Started Oct 15 11:28:04 AM UTC 24
Finished Oct 15 11:28:08 AM UTC 24
Peak memory 227976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840645915 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 134.edn_alert.840645915
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/134.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/37.edn_alert.901113077
Short name T183
Test name
Test status
Simulation time 24338477 ps
CPU time 1.73 seconds
Started Oct 15 11:26:45 AM UTC 24
Finished Oct 15 11:26:47 AM UTC 24
Peak memory 232076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901113077 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 37.edn_alert.901113077
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/37.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/16.edn_err.3788967602
Short name T202
Test name
Test status
Simulation time 33136701 ps
CPU time 1.32 seconds
Started Oct 15 11:25:46 AM UTC 24
Finished Oct 15 11:25:48 AM UTC 24
Peak memory 229912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788967602 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 16.edn_err.3788967602
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/16.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/6.edn_disable_auto_req_mode.824471304
Short name T128
Test name
Test status
Simulation time 197472682 ps
CPU time 1.68 seconds
Started Oct 15 11:25:17 AM UTC 24
Finished Oct 15 11:25:20 AM UTC 24
Peak memory 231856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824471304 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable_auto_req_mode.824471304
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/6.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/2.edn_disable.4034822440
Short name T46
Test name
Test status
Simulation time 53903969 ps
CPU time 1.3 seconds
Started Oct 15 11:24:57 AM UTC 24
Finished Oct 15 11:25:00 AM UTC 24
Peak memory 227984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034822440 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.4034822440
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/2.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/1.edn_genbits.3905613686
Short name T26
Test name
Test status
Simulation time 45321304 ps
CPU time 2.37 seconds
Started Oct 15 11:24:48 AM UTC 24
Finished Oct 15 11:24:52 AM UTC 24
Peak memory 231336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905613686 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_genbits.3905613686
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/1.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/54.edn_genbits.1082933446
Short name T339
Test name
Test status
Simulation time 53074195 ps
CPU time 2.23 seconds
Started Oct 15 11:27:22 AM UTC 24
Finished Oct 15 11:27:26 AM UTC 24
Peak memory 231480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082933446 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 54.edn_genbits.1082933446
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/54.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/111.edn_alert.179192922
Short name T152
Test name
Test status
Simulation time 87778133 ps
CPU time 1.31 seconds
Started Oct 15 11:27:56 AM UTC 24
Finished Oct 15 11:27:58 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179192922 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 111.edn_alert.179192922
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/111.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/10.edn_intr.2083725339
Short name T34
Test name
Test status
Simulation time 35449762 ps
CPU time 1.26 seconds
Started Oct 15 11:25:29 AM UTC 24
Finished Oct 15 11:25:31 AM UTC 24
Peak memory 230036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083725339 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 10.edn_intr.2083725339
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/10.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/1.edn_disable_auto_req_mode.1397984209
Short name T14
Test name
Test status
Simulation time 35655343 ps
CPU time 1.87 seconds
Started Oct 15 11:24:53 AM UTC 24
Finished Oct 15 11:24:56 AM UTC 24
Peak memory 227848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397984209 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable_auto_req_mode.1397984209
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/1.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/10.edn_disable.2677440231
Short name T103
Test name
Test status
Simulation time 26869162 ps
CPU time 1.22 seconds
Started Oct 15 11:25:30 AM UTC 24
Finished Oct 15 11:25:32 AM UTC 24
Peak memory 227976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677440231 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.2677440231
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/10.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/120.edn_alert.2091508204
Short name T156
Test name
Test status
Simulation time 144852289 ps
CPU time 1.16 seconds
Started Oct 15 11:27:58 AM UTC 24
Finished Oct 15 11:28:07 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091508204 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 120.edn_alert.2091508204
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/120.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/122.edn_alert.142637993
Short name T201
Test name
Test status
Simulation time 150979064 ps
CPU time 1.46 seconds
Started Oct 15 11:27:58 AM UTC 24
Finished Oct 15 11:28:07 AM UTC 24
Peak memory 227984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142637993 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 122.edn_alert.142637993
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/122.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/125.edn_alert.1794006779
Short name T723
Test name
Test status
Simulation time 32001159 ps
CPU time 1.22 seconds
Started Oct 15 11:28:00 AM UTC 24
Finished Oct 15 11:28:03 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794006779 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 125.edn_alert.1794006779
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/125.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/137.edn_alert.213312525
Short name T744
Test name
Test status
Simulation time 26311963 ps
CPU time 1.08 seconds
Started Oct 15 11:28:05 AM UTC 24
Finished Oct 15 11:28:08 AM UTC 24
Peak memory 230032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213312525 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 137.edn_alert.213312525
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/137.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/15.edn_disable_auto_req_mode.1532340051
Short name T86
Test name
Test status
Simulation time 79039938 ps
CPU time 1.58 seconds
Started Oct 15 11:25:44 AM UTC 24
Finished Oct 15 11:25:46 AM UTC 24
Peak memory 227856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532340051 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable_auto_req_mode.1532340051
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/15.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/153.edn_alert.3641846935
Short name T204
Test name
Test status
Simulation time 32489368 ps
CPU time 1.04 seconds
Started Oct 15 11:28:14 AM UTC 24
Finished Oct 15 11:28:17 AM UTC 24
Peak memory 230004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641846935 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 153.edn_alert.3641846935
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/153.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/16.edn_alert.4108801290
Short name T169
Test name
Test status
Simulation time 41052027 ps
CPU time 1.75 seconds
Started Oct 15 11:25:46 AM UTC 24
Finished Oct 15 11:25:49 AM UTC 24
Peak memory 232080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108801290 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 16.edn_alert.4108801290
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/16.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/19.edn_disable.1005388214
Short name T196
Test name
Test status
Simulation time 92451921 ps
CPU time 1.09 seconds
Started Oct 15 11:25:54 AM UTC 24
Finished Oct 15 11:25:56 AM UTC 24
Peak memory 227980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005388214 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.1005388214
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/19.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/33.edn_disable.222534667
Short name T223
Test name
Test status
Simulation time 15724830 ps
CPU time 1.2 seconds
Started Oct 15 11:26:35 AM UTC 24
Finished Oct 15 11:26:37 AM UTC 24
Peak memory 227916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222534667 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.222534667
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/33.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/55.edn_err.2361141641
Short name T213
Test name
Test status
Simulation time 78386696 ps
CPU time 1.23 seconds
Started Oct 15 11:27:24 AM UTC 24
Finished Oct 15 11:27:26 AM UTC 24
Peak memory 231960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361141641 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 55.edn_err.2361141641
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/55.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/9.edn_disable.2498235813
Short name T74
Test name
Test status
Simulation time 14396027 ps
CPU time 1.36 seconds
Started Oct 15 11:25:27 AM UTC 24
Finished Oct 15 11:25:30 AM UTC 24
Peak memory 228044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498235813 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.2498235813
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/9.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/16.edn_genbits.60603608
Short name T77
Test name
Test status
Simulation time 225430799 ps
CPU time 3.95 seconds
Started Oct 15 11:25:45 AM UTC 24
Finished Oct 15 11:25:50 AM UTC 24
Peak memory 231204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60603608 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 16.edn_genbits.60603608
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/16.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/18.edn_alert.916624762
Short name T133
Test name
Test status
Simulation time 34116893 ps
CPU time 1.95 seconds
Started Oct 15 11:25:51 AM UTC 24
Finished Oct 15 11:25:54 AM UTC 24
Peak memory 227980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916624762 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 18.edn_alert.916624762
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/18.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/118.edn_genbits.2358707016
Short name T328
Test name
Test status
Simulation time 101348157 ps
CPU time 1.28 seconds
Started Oct 15 11:27:57 AM UTC 24
Finished Oct 15 11:28:03 AM UTC 24
Peak memory 229908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358707016 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 118.edn_genbits.2358707016
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/118.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/34.edn_genbits.4167977449
Short name T358
Test name
Test status
Simulation time 145926239 ps
CPU time 3.41 seconds
Started Oct 15 11:26:36 AM UTC 24
Finished Oct 15 11:26:40 AM UTC 24
Peak memory 233144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167977449 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_genbits.4167977449
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/34.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/35.edn_intr.1135349564
Short name T110
Test name
Test status
Simulation time 22563249 ps
CPU time 1.26 seconds
Started Oct 15 11:26:40 AM UTC 24
Finished Oct 15 11:26:42 AM UTC 24
Peak memory 230036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135349564 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 35.edn_intr.1135349564
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/35.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/15.edn_genbits.1111871931
Short name T12
Test name
Test status
Simulation time 65586746 ps
CPU time 2.04 seconds
Started Oct 15 11:25:42 AM UTC 24
Finished Oct 15 11:25:45 AM UTC 24
Peak memory 233384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111871931 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_genbits.1111871931
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/15.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_rw.3414331493
Short name T274
Test name
Test status
Simulation time 20378114 ps
CPU time 1.19 seconds
Started Oct 15 11:38:34 AM UTC 24
Finished Oct 15 11:38:37 AM UTC 24
Peak memory 216644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414331493 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.3414331493
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/0.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/0.edn_tl_intg_err.858063944
Short name T262
Test name
Test status
Simulation time 154997389 ps
CPU time 2.11 seconds
Started Oct 15 11:38:33 AM UTC 24
Finished Oct 15 11:38:36 AM UTC 24
Peak memory 217764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858063944 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.858063944
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/0.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/10.edn_stress_all.821203853
Short name T115
Test name
Test status
Simulation time 100267927 ps
CPU time 2.94 seconds
Started Oct 15 11:25:29 AM UTC 24
Finished Oct 15 11:25:32 AM UTC 24
Peak memory 233396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821203853 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.821203853
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/10.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/111.edn_genbits.1547904742
Short name T347
Test name
Test status
Simulation time 93226673 ps
CPU time 1.54 seconds
Started Oct 15 11:27:56 AM UTC 24
Finished Oct 15 11:27:58 AM UTC 24
Peak memory 232192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547904742 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 111.edn_genbits.1547904742
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/111.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/123.edn_genbits.2839998563
Short name T330
Test name
Test status
Simulation time 98303659 ps
CPU time 1.43 seconds
Started Oct 15 11:27:58 AM UTC 24
Finished Oct 15 11:28:07 AM UTC 24
Peak memory 231956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839998563 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 123.edn_genbits.2839998563
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/123.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/134.edn_genbits.131907354
Short name T765
Test name
Test status
Simulation time 71822524 ps
CPU time 1.37 seconds
Started Oct 15 11:28:03 AM UTC 24
Finished Oct 15 11:28:13 AM UTC 24
Peak memory 230160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131907354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 134.edn_genbits.131907354
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/134.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/139.edn_genbits.1711738212
Short name T773
Test name
Test status
Simulation time 61907885 ps
CPU time 1.36 seconds
Started Oct 15 11:28:08 AM UTC 24
Finished Oct 15 11:28:13 AM UTC 24
Peak memory 227860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711738212 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 139.edn_genbits.1711738212
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/139.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/155.edn_genbits.944705402
Short name T348
Test name
Test status
Simulation time 74614966 ps
CPU time 1.29 seconds
Started Oct 15 11:28:14 AM UTC 24
Finished Oct 15 11:28:27 AM UTC 24
Peak memory 229988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944705402 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 155.edn_genbits.944705402
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/155.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/164.edn_genbits.414528193
Short name T344
Test name
Test status
Simulation time 59171397 ps
CPU time 1 seconds
Started Oct 15 11:28:17 AM UTC 24
Finished Oct 15 11:28:22 AM UTC 24
Peak memory 229968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414528193 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 164.edn_genbits.414528193
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/164.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/180.edn_genbits.3255827271
Short name T334
Test name
Test status
Simulation time 66125064 ps
CPU time 1.32 seconds
Started Oct 15 11:28:29 AM UTC 24
Finished Oct 15 11:28:32 AM UTC 24
Peak memory 229984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255827271 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 180.edn_genbits.3255827271
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/180.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/92.edn_genbits.308341015
Short name T341
Test name
Test status
Simulation time 40405969 ps
CPU time 1.63 seconds
Started Oct 15 11:27:47 AM UTC 24
Finished Oct 15 11:27:50 AM UTC 24
Peak memory 232152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308341015 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 92.edn_genbits.308341015
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/92.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/17.edn_intr.3183811427
Short name T111
Test name
Test status
Simulation time 21396488 ps
CPU time 1.54 seconds
Started Oct 15 11:25:48 AM UTC 24
Finished Oct 15 11:25:50 AM UTC 24
Peak memory 230036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183811427 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 17.edn_intr.3183811427
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/17.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/12.edn_err.2591524921
Short name T136
Test name
Test status
Simulation time 71598961 ps
CPU time 1.66 seconds
Started Oct 15 11:25:35 AM UTC 24
Finished Oct 15 11:25:37 AM UTC 24
Peak memory 248292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591524921 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 12.edn_err.2591524921
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/12.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/117.edn_alert.654444924
Short name T236
Test name
Test status
Simulation time 40739916 ps
CPU time 1.25 seconds
Started Oct 15 11:27:57 AM UTC 24
Finished Oct 15 11:28:02 AM UTC 24
Peak memory 230032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654444924 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 117.edn_alert.654444924
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/117.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/133.edn_alert.4067946017
Short name T139
Test name
Test status
Simulation time 45174256 ps
CPU time 1.54 seconds
Started Oct 15 11:28:03 AM UTC 24
Finished Oct 15 11:28:13 AM UTC 24
Peak memory 232076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067946017 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 133.edn_alert.4067946017
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/133.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/103.edn_genbits.220075447
Short name T699
Test name
Test status
Simulation time 50158029 ps
CPU time 1.57 seconds
Started Oct 15 11:27:53 AM UTC 24
Finished Oct 15 11:27:55 AM UTC 24
Peak memory 229904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220075447 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 103.edn_genbits.220075447
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/103.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_aliasing.437818521
Short name T253
Test name
Test status
Simulation time 65172354 ps
CPU time 2.27 seconds
Started Oct 15 11:38:34 AM UTC 24
Finished Oct 15 11:38:38 AM UTC 24
Peak memory 217752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437818521 -assert nopostproc +UVM_TESTNAME=edn
_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/e
dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.437818521
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/0.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_bit_bash.1485408015
Short name T966
Test name
Test status
Simulation time 182771027 ps
CPU time 3.96 seconds
Started Oct 15 11:38:34 AM UTC 24
Finished Oct 15 11:38:39 AM UTC 24
Peak memory 217808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485408015 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.1485408015
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/0.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_hw_reset.2838728196
Short name T965
Test name
Test status
Simulation time 15533762 ps
CPU time 1.38 seconds
Started Oct 15 11:38:33 AM UTC 24
Finished Oct 15 11:38:35 AM UTC 24
Peak memory 216664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838728196 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.2838728196
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/0.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3067268548
Short name T968
Test name
Test status
Simulation time 202835871 ps
CPU time 2.22 seconds
Started Oct 15 11:38:37 AM UTC 24
Finished Oct 15 11:38:40 AM UTC 24
Peak memory 228184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3067268548 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.3067268548
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/0.edn_intr_test.897402242
Short name T964
Test name
Test status
Simulation time 22043301 ps
CPU time 1.19 seconds
Started Oct 15 11:38:33 AM UTC 24
Finished Oct 15 11:38:35 AM UTC 24
Peak memory 216644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897402242 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.897402242
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/0.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/0.edn_same_csr_outstanding.3239229153
Short name T275
Test name
Test status
Simulation time 61362374 ps
CPU time 1.58 seconds
Started Oct 15 11:38:36 AM UTC 24
Finished Oct 15 11:38:38 AM UTC 24
Peak memory 216764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239229153 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_outstanding.3239229153
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/0.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/0.edn_tl_errors.836714851
Short name T963
Test name
Test status
Simulation time 50290173 ps
CPU time 2.72 seconds
Started Oct 15 11:38:30 AM UTC 24
Finished Oct 15 11:38:34 AM UTC 24
Peak memory 228156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836714851 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.836714851
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/0.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_bit_bash.1635796473
Short name T973
Test name
Test status
Simulation time 355002262 ps
CPU time 3.79 seconds
Started Oct 15 11:38:40 AM UTC 24
Finished Oct 15 11:38:44 AM UTC 24
Peak memory 217696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635796473 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.1635796473
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/1.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_hw_reset.4105879207
Short name T969
Test name
Test status
Simulation time 21491873 ps
CPU time 1.27 seconds
Started Oct 15 11:38:39 AM UTC 24
Finished Oct 15 11:38:42 AM UTC 24
Peak memory 216768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105879207 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.4105879207
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/1.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.860084649
Short name T971
Test name
Test status
Simulation time 271435042 ps
CPU time 1.67 seconds
Started Oct 15 11:38:40 AM UTC 24
Finished Oct 15 11:38:42 AM UTC 24
Peak memory 227068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=860084649 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.860084649
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_rw.870527513
Short name T263
Test name
Test status
Simulation time 28939794 ps
CPU time 1.41 seconds
Started Oct 15 11:38:39 AM UTC 24
Finished Oct 15 11:38:42 AM UTC 24
Peak memory 216720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870527513 -assert nopostproc +UVM_TESTNAME=edn_base_
test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.870527513
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/1.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/1.edn_intr_test.1512535004
Short name T967
Test name
Test status
Simulation time 42624140 ps
CPU time 1.21 seconds
Started Oct 15 11:38:38 AM UTC 24
Finished Oct 15 11:38:40 AM UTC 24
Peak memory 216720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512535004 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.1512535004
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/1.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/1.edn_same_csr_outstanding.1868775902
Short name T254
Test name
Test status
Simulation time 34257838 ps
CPU time 2.01 seconds
Started Oct 15 11:38:40 AM UTC 24
Finished Oct 15 11:38:43 AM UTC 24
Peak memory 216720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868775902 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_outstanding.1868775902
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/1.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/1.edn_tl_errors.3804240318
Short name T970
Test name
Test status
Simulation time 98062226 ps
CPU time 4.33 seconds
Started Oct 15 11:38:37 AM UTC 24
Finished Oct 15 11:38:42 AM UTC 24
Peak memory 228188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804240318 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.3804240318
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/1.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/1.edn_tl_intg_err.1685465271
Short name T297
Test name
Test status
Simulation time 157613256 ps
CPU time 2.1 seconds
Started Oct 15 11:38:38 AM UTC 24
Finished Oct 15 11:38:41 AM UTC 24
Peak memory 217868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685465271 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.1685465271
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/1.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3504825088
Short name T1017
Test name
Test status
Simulation time 70775688 ps
CPU time 1.87 seconds
Started Oct 15 11:38:56 AM UTC 24
Finished Oct 15 11:38:59 AM UTC 24
Peak memory 227016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3504825088 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.3504825088
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_rw.1314364328
Short name T1003
Test name
Test status
Simulation time 22216537 ps
CPU time 1.19 seconds
Started Oct 15 11:38:56 AM UTC 24
Finished Oct 15 11:38:58 AM UTC 24
Peak memory 216708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314364328 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.1314364328
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/10.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/10.edn_intr_test.120693062
Short name T1010
Test name
Test status
Simulation time 13295616 ps
CPU time 1.22 seconds
Started Oct 15 11:38:56 AM UTC 24
Finished Oct 15 11:38:58 AM UTC 24
Peak memory 215656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120693062 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.120693062
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/10.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/10.edn_same_csr_outstanding.2865943744
Short name T1011
Test name
Test status
Simulation time 40282052 ps
CPU time 1.43 seconds
Started Oct 15 11:38:56 AM UTC 24
Finished Oct 15 11:38:59 AM UTC 24
Peak memory 215772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865943744 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_outstanding.2865943744
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/10.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_errors.702758454
Short name T1013
Test name
Test status
Simulation time 245386411 ps
CPU time 3 seconds
Started Oct 15 11:38:54 AM UTC 24
Finished Oct 15 11:38:59 AM UTC 24
Peak memory 227996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702758454 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.702758454
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/10.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_intg_err.771052490
Short name T1019
Test name
Test status
Simulation time 81867715 ps
CPU time 2.64 seconds
Started Oct 15 11:38:56 AM UTC 24
Finished Oct 15 11:39:00 AM UTC 24
Peak memory 218076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771052490 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.771052490
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/10.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3916011954
Short name T1023
Test name
Test status
Simulation time 106505802 ps
CPU time 1.71 seconds
Started Oct 15 11:38:57 AM UTC 24
Finished Oct 15 11:39:00 AM UTC 24
Peak memory 226884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3916011954 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.3916011954
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_rw.3649441883
Short name T282
Test name
Test status
Simulation time 21301719 ps
CPU time 0.93 seconds
Started Oct 15 11:38:57 AM UTC 24
Finished Oct 15 11:39:00 AM UTC 24
Peak memory 216724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649441883 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.3649441883
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/11.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/11.edn_intr_test.3489157761
Short name T1018
Test name
Test status
Simulation time 18950229 ps
CPU time 0.93 seconds
Started Oct 15 11:38:57 AM UTC 24
Finished Oct 15 11:39:00 AM UTC 24
Peak memory 216888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489157761 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.3489157761
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/11.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/11.edn_same_csr_outstanding.1666222938
Short name T1021
Test name
Test status
Simulation time 62711411 ps
CPU time 1.35 seconds
Started Oct 15 11:38:57 AM UTC 24
Finished Oct 15 11:39:00 AM UTC 24
Peak memory 216748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666222938 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_outstanding.1666222938
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/11.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_errors.1750974211
Short name T1020
Test name
Test status
Simulation time 101573965 ps
CPU time 2.61 seconds
Started Oct 15 11:38:56 AM UTC 24
Finished Oct 15 11:39:00 AM UTC 24
Peak memory 227988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750974211 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.1750974211
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/11.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_intg_err.2229574864
Short name T1015
Test name
Test status
Simulation time 253674652 ps
CPU time 1.98 seconds
Started Oct 15 11:38:56 AM UTC 24
Finished Oct 15 11:38:59 AM UTC 24
Peak memory 227024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229574864 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.2229574864
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/11.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3863498355
Short name T1024
Test name
Test status
Simulation time 205185432 ps
CPU time 1.18 seconds
Started Oct 15 11:38:59 AM UTC 24
Finished Oct 15 11:39:01 AM UTC 24
Peak memory 229064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3863498355 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.3863498355
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_rw.561336133
Short name T1022
Test name
Test status
Simulation time 72567706 ps
CPU time 0.78 seconds
Started Oct 15 11:38:59 AM UTC 24
Finished Oct 15 11:39:01 AM UTC 24
Peak memory 216704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561336133 -assert nopostproc +UVM_TESTNAME=edn_base_
test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.561336133
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/12.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/12.edn_intr_test.2004503620
Short name T1016
Test name
Test status
Simulation time 12642269 ps
CPU time 1.07 seconds
Started Oct 15 11:38:59 AM UTC 24
Finished Oct 15 11:39:01 AM UTC 24
Peak memory 216904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004503620 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.2004503620
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/12.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/12.edn_same_csr_outstanding.2390342549
Short name T1026
Test name
Test status
Simulation time 32713885 ps
CPU time 1.4 seconds
Started Oct 15 11:38:59 AM UTC 24
Finished Oct 15 11:39:02 AM UTC 24
Peak memory 216716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390342549 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_outstanding.2390342549
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/12.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_errors.1043174803
Short name T1027
Test name
Test status
Simulation time 85738994 ps
CPU time 2.91 seconds
Started Oct 15 11:38:57 AM UTC 24
Finished Oct 15 11:39:02 AM UTC 24
Peak memory 228036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043174803 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.1043174803
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/12.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_intg_err.3345544393
Short name T1025
Test name
Test status
Simulation time 67886394 ps
CPU time 1.59 seconds
Started Oct 15 11:38:59 AM UTC 24
Finished Oct 15 11:39:02 AM UTC 24
Peak memory 227008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345544393 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.3345544393
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/12.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.853340203
Short name T1033
Test name
Test status
Simulation time 142097193 ps
CPU time 1.34 seconds
Started Oct 15 11:39:00 AM UTC 24
Finished Oct 15 11:39:03 AM UTC 24
Peak memory 226956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=853340203 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.853340203
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_rw.1258944286
Short name T283
Test name
Test status
Simulation time 14734019 ps
CPU time 1.33 seconds
Started Oct 15 11:39:00 AM UTC 24
Finished Oct 15 11:39:03 AM UTC 24
Peak memory 216724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258944286 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.1258944286
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/13.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/13.edn_intr_test.821916186
Short name T1029
Test name
Test status
Simulation time 14746290 ps
CPU time 0.96 seconds
Started Oct 15 11:39:00 AM UTC 24
Finished Oct 15 11:39:02 AM UTC 24
Peak memory 216644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821916186 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.821916186
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/13.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/13.edn_same_csr_outstanding.1252159725
Short name T1032
Test name
Test status
Simulation time 24114358 ps
CPU time 1.3 seconds
Started Oct 15 11:39:00 AM UTC 24
Finished Oct 15 11:39:03 AM UTC 24
Peak memory 216716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252159725 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_outstanding.1252159725
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/13.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_errors.3685329146
Short name T1028
Test name
Test status
Simulation time 83290822 ps
CPU time 2.06 seconds
Started Oct 15 11:38:59 AM UTC 24
Finished Oct 15 11:39:02 AM UTC 24
Peak memory 228048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685329146 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.3685329146
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/13.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_intg_err.1604645158
Short name T1044
Test name
Test status
Simulation time 241951776 ps
CPU time 3.54 seconds
Started Oct 15 11:39:00 AM UTC 24
Finished Oct 15 11:39:05 AM UTC 24
Peak memory 217752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604645158 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.1604645158
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/13.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.747237467
Short name T1038
Test name
Test status
Simulation time 82806944 ps
CPU time 1.29 seconds
Started Oct 15 11:39:01 AM UTC 24
Finished Oct 15 11:39:04 AM UTC 24
Peak memory 226956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=747237467 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.747237467
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_rw.3871673883
Short name T1030
Test name
Test status
Simulation time 36081940 ps
CPU time 0.82 seconds
Started Oct 15 11:39:00 AM UTC 24
Finished Oct 15 11:39:03 AM UTC 24
Peak memory 216708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871673883 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.3871673883
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/14.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/14.edn_intr_test.2031893558
Short name T1031
Test name
Test status
Simulation time 13764648 ps
CPU time 0.96 seconds
Started Oct 15 11:39:00 AM UTC 24
Finished Oct 15 11:39:03 AM UTC 24
Peak memory 216844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031893558 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.2031893558
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/14.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/14.edn_same_csr_outstanding.279951221
Short name T1035
Test name
Test status
Simulation time 73948520 ps
CPU time 1.61 seconds
Started Oct 15 11:39:00 AM UTC 24
Finished Oct 15 11:39:03 AM UTC 24
Peak memory 216900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279951221 -assert nopostproc +UVM_
TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_outstanding.279951221
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/14.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_errors.3721707155
Short name T1039
Test name
Test status
Simulation time 49085982 ps
CPU time 2.68 seconds
Started Oct 15 11:39:00 AM UTC 24
Finished Oct 15 11:39:04 AM UTC 24
Peak memory 228100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721707155 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.3721707155
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/14.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_intg_err.2079651924
Short name T1034
Test name
Test status
Simulation time 49811350 ps
CPU time 1.55 seconds
Started Oct 15 11:39:00 AM UTC 24
Finished Oct 15 11:39:03 AM UTC 24
Peak memory 227024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079651924 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.2079651924
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/14.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.4214433436
Short name T1043
Test name
Test status
Simulation time 19864344 ps
CPU time 1.16 seconds
Started Oct 15 11:39:03 AM UTC 24
Finished Oct 15 11:39:05 AM UTC 24
Peak memory 226956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=4214433436 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.4214433436
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_rw.2795306983
Short name T1036
Test name
Test status
Simulation time 20177816 ps
CPU time 1.02 seconds
Started Oct 15 11:39:02 AM UTC 24
Finished Oct 15 11:39:04 AM UTC 24
Peak memory 216708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795306983 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.2795306983
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/15.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/15.edn_intr_test.1484742019
Short name T1037
Test name
Test status
Simulation time 21084219 ps
CPU time 0.91 seconds
Started Oct 15 11:39:02 AM UTC 24
Finished Oct 15 11:39:04 AM UTC 24
Peak memory 216844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484742019 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.1484742019
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/15.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/15.edn_same_csr_outstanding.1461294758
Short name T1040
Test name
Test status
Simulation time 383357712 ps
CPU time 1.56 seconds
Started Oct 15 11:39:02 AM UTC 24
Finished Oct 15 11:39:04 AM UTC 24
Peak memory 216760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461294758 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_outstanding.1461294758
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/15.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_errors.2790490757
Short name T1041
Test name
Test status
Simulation time 77341036 ps
CPU time 1.94 seconds
Started Oct 15 11:39:02 AM UTC 24
Finished Oct 15 11:39:05 AM UTC 24
Peak memory 226928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790490757 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.2790490757
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/15.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_intg_err.2125217675
Short name T1047
Test name
Test status
Simulation time 309691279 ps
CPU time 3.06 seconds
Started Oct 15 11:39:02 AM UTC 24
Finished Oct 15 11:39:06 AM UTC 24
Peak memory 217752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125217675 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.2125217675
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/15.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3304434726
Short name T1053
Test name
Test status
Simulation time 54579298 ps
CPU time 1.46 seconds
Started Oct 15 11:39:04 AM UTC 24
Finished Oct 15 11:39:07 AM UTC 24
Peak memory 227016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3304434726 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.3304434726
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_rw.1031015624
Short name T1042
Test name
Test status
Simulation time 12474832 ps
CPU time 1.01 seconds
Started Oct 15 11:39:03 AM UTC 24
Finished Oct 15 11:39:05 AM UTC 24
Peak memory 216708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031015624 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.1031015624
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/16.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/16.edn_intr_test.115142780
Short name T1045
Test name
Test status
Simulation time 16618260 ps
CPU time 1.22 seconds
Started Oct 15 11:39:03 AM UTC 24
Finished Oct 15 11:39:05 AM UTC 24
Peak memory 216644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115142780 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.115142780
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/16.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/16.edn_same_csr_outstanding.2570952577
Short name T1046
Test name
Test status
Simulation time 64351157 ps
CPU time 1.38 seconds
Started Oct 15 11:39:03 AM UTC 24
Finished Oct 15 11:39:05 AM UTC 24
Peak memory 216760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570952577 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_outstanding.2570952577
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/16.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_errors.2858916784
Short name T1056
Test name
Test status
Simulation time 203840307 ps
CPU time 3.87 seconds
Started Oct 15 11:39:03 AM UTC 24
Finished Oct 15 11:39:08 AM UTC 24
Peak memory 228100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858916784 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.2858916784
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/16.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_intg_err.937993182
Short name T1048
Test name
Test status
Simulation time 627580464 ps
CPU time 2.37 seconds
Started Oct 15 11:39:03 AM UTC 24
Finished Oct 15 11:39:06 AM UTC 24
Peak memory 217872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937993182 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.937993182
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/16.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3253010936
Short name T1059
Test name
Test status
Simulation time 104074932 ps
CPU time 2.25 seconds
Started Oct 15 11:39:05 AM UTC 24
Finished Oct 15 11:39:08 AM UTC 24
Peak memory 228100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3253010936 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.3253010936
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_rw.1067733372
Short name T1050
Test name
Test status
Simulation time 16098204 ps
CPU time 1.12 seconds
Started Oct 15 11:39:05 AM UTC 24
Finished Oct 15 11:39:07 AM UTC 24
Peak memory 216708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067733372 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.1067733372
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/17.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/17.edn_intr_test.2646963745
Short name T1049
Test name
Test status
Simulation time 15747297 ps
CPU time 1.02 seconds
Started Oct 15 11:39:05 AM UTC 24
Finished Oct 15 11:39:07 AM UTC 24
Peak memory 216904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646963745 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.2646963745
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/17.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/17.edn_same_csr_outstanding.3990677341
Short name T1052
Test name
Test status
Simulation time 82769795 ps
CPU time 1.31 seconds
Started Oct 15 11:39:05 AM UTC 24
Finished Oct 15 11:39:07 AM UTC 24
Peak memory 216760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990677341 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_outstanding.3990677341
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/17.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_errors.1117419575
Short name T1062
Test name
Test status
Simulation time 177581961 ps
CPU time 2.71 seconds
Started Oct 15 11:39:04 AM UTC 24
Finished Oct 15 11:39:08 AM UTC 24
Peak memory 228012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117419575 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.1117419575
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/17.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_intg_err.3317246235
Short name T1067
Test name
Test status
Simulation time 87409679 ps
CPU time 3.12 seconds
Started Oct 15 11:39:04 AM UTC 24
Finished Oct 15 11:39:09 AM UTC 24
Peak memory 217752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317246235 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.3317246235
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/17.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1047653818
Short name T1064
Test name
Test status
Simulation time 43628972 ps
CPU time 1.37 seconds
Started Oct 15 11:39:06 AM UTC 24
Finished Oct 15 11:39:08 AM UTC 24
Peak memory 227016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1047653818 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.1047653818
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_rw.667205735
Short name T1051
Test name
Test status
Simulation time 17100666 ps
CPU time 0.96 seconds
Started Oct 15 11:39:05 AM UTC 24
Finished Oct 15 11:39:07 AM UTC 24
Peak memory 216704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667205735 -assert nopostproc +UVM_TESTNAME=edn_base_
test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.667205735
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/18.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/18.edn_intr_test.1009570954
Short name T1054
Test name
Test status
Simulation time 47070652 ps
CPU time 1.21 seconds
Started Oct 15 11:39:05 AM UTC 24
Finished Oct 15 11:39:07 AM UTC 24
Peak memory 216904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009570954 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.1009570954
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/18.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/18.edn_same_csr_outstanding.3793464314
Short name T1055
Test name
Test status
Simulation time 124102051 ps
CPU time 1.54 seconds
Started Oct 15 11:39:05 AM UTC 24
Finished Oct 15 11:39:07 AM UTC 24
Peak memory 216748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793464314 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_outstanding.3793464314
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/18.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_errors.3726397031
Short name T1063
Test name
Test status
Simulation time 98243865 ps
CPU time 2.49 seconds
Started Oct 15 11:39:05 AM UTC 24
Finished Oct 15 11:39:08 AM UTC 24
Peak memory 228080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726397031 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.3726397031
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/18.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_intg_err.116334094
Short name T1057
Test name
Test status
Simulation time 684514353 ps
CPU time 2.18 seconds
Started Oct 15 11:39:05 AM UTC 24
Finished Oct 15 11:39:08 AM UTC 24
Peak memory 217820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116334094 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.116334094
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/18.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3071530204
Short name T1066
Test name
Test status
Simulation time 81881831 ps
CPU time 1.29 seconds
Started Oct 15 11:39:06 AM UTC 24
Finished Oct 15 11:39:08 AM UTC 24
Peak memory 227012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3071530204 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.3071530204
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_rw.1920029703
Short name T1061
Test name
Test status
Simulation time 41029476 ps
CPU time 1.13 seconds
Started Oct 15 11:39:06 AM UTC 24
Finished Oct 15 11:39:08 AM UTC 24
Peak memory 216708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920029703 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.1920029703
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/19.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/19.edn_intr_test.4252752491
Short name T1058
Test name
Test status
Simulation time 58018524 ps
CPU time 0.9 seconds
Started Oct 15 11:39:06 AM UTC 24
Finished Oct 15 11:39:08 AM UTC 24
Peak memory 216888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252752491 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.4252752491
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/19.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/19.edn_same_csr_outstanding.269449892
Short name T1065
Test name
Test status
Simulation time 29913876 ps
CPU time 1.27 seconds
Started Oct 15 11:39:06 AM UTC 24
Finished Oct 15 11:39:08 AM UTC 24
Peak memory 216932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269449892 -assert nopostproc +UVM_
TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_outstanding.269449892
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/19.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_errors.3366597655
Short name T1077
Test name
Test status
Simulation time 94999935 ps
CPU time 3.42 seconds
Started Oct 15 11:39:06 AM UTC 24
Finished Oct 15 11:39:10 AM UTC 24
Peak memory 227984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366597655 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.3366597655
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/19.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_intg_err.1599496032
Short name T1070
Test name
Test status
Simulation time 89380911 ps
CPU time 2.39 seconds
Started Oct 15 11:39:06 AM UTC 24
Finished Oct 15 11:39:09 AM UTC 24
Peak memory 217752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599496032 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.1599496032
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/19.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_aliasing.548588675
Short name T974
Test name
Test status
Simulation time 88699415 ps
CPU time 1.73 seconds
Started Oct 15 11:38:42 AM UTC 24
Finished Oct 15 11:38:45 AM UTC 24
Peak memory 216660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548588675 -assert nopostproc +UVM_TESTNAME=edn
_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/e
dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.548588675
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/2.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_bit_bash.677200173
Short name T977
Test name
Test status
Simulation time 108826364 ps
CPU time 3.57 seconds
Started Oct 15 11:38:42 AM UTC 24
Finished Oct 15 11:38:47 AM UTC 24
Peak memory 217648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677200173 -assert nopostproc +UVM_TESTNAME=edn
_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/e
dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.677200173
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/2.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_hw_reset.3458320877
Short name T277
Test name
Test status
Simulation time 75416338 ps
CPU time 1.34 seconds
Started Oct 15 11:38:41 AM UTC 24
Finished Oct 15 11:38:44 AM UTC 24
Peak memory 216708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458320877 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.3458320877
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/2.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3971157572
Short name T976
Test name
Test status
Simulation time 90978765 ps
CPU time 1.92 seconds
Started Oct 15 11:38:43 AM UTC 24
Finished Oct 15 11:38:47 AM UTC 24
Peak memory 226956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3971157572 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.3971157572
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_rw.264205833
Short name T278
Test name
Test status
Simulation time 14995324 ps
CPU time 1.17 seconds
Started Oct 15 11:38:42 AM UTC 24
Finished Oct 15 11:38:45 AM UTC 24
Peak memory 216324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264205833 -assert nopostproc +UVM_TESTNAME=edn_base_
test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.264205833
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/2.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/2.edn_intr_test.37725082
Short name T972
Test name
Test status
Simulation time 13960149 ps
CPU time 1.22 seconds
Started Oct 15 11:38:41 AM UTC 24
Finished Oct 15 11:38:44 AM UTC 24
Peak memory 216528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37725082 -assert nopostproc +UVM_TESTNAME=edn_base_test
+UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.37725082
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/2.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/2.edn_same_csr_outstanding.361329403
Short name T286
Test name
Test status
Simulation time 75929089 ps
CPU time 1.73 seconds
Started Oct 15 11:38:43 AM UTC 24
Finished Oct 15 11:38:46 AM UTC 24
Peak memory 216644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361329403 -assert nopostproc +UVM_
TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_outstanding.361329403
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/2.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/2.edn_tl_errors.746370982
Short name T255
Test name
Test status
Simulation time 182975984 ps
CPU time 2.56 seconds
Started Oct 15 11:38:40 AM UTC 24
Finished Oct 15 11:38:43 AM UTC 24
Peak memory 227996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746370982 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.746370982
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/2.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/2.edn_tl_intg_err.1475545433
Short name T298
Test name
Test status
Simulation time 314760086 ps
CPU time 2.21 seconds
Started Oct 15 11:38:41 AM UTC 24
Finished Oct 15 11:38:45 AM UTC 24
Peak memory 217820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475545433 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.1475545433
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/2.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/20.edn_intr_test.3202370594
Short name T1060
Test name
Test status
Simulation time 153663330 ps
CPU time 0.83 seconds
Started Oct 15 11:39:06 AM UTC 24
Finished Oct 15 11:39:08 AM UTC 24
Peak memory 216888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202370594 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.3202370594
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/20.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/21.edn_intr_test.301836272
Short name T1068
Test name
Test status
Simulation time 21376739 ps
CPU time 0.86 seconds
Started Oct 15 11:39:07 AM UTC 24
Finished Oct 15 11:39:09 AM UTC 24
Peak memory 216644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301836272 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.301836272
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/21.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/22.edn_intr_test.145054962
Short name T1069
Test name
Test status
Simulation time 51044280 ps
CPU time 0.91 seconds
Started Oct 15 11:39:07 AM UTC 24
Finished Oct 15 11:39:09 AM UTC 24
Peak memory 216624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145054962 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.145054962
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/22.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/23.edn_intr_test.2174777908
Short name T1074
Test name
Test status
Simulation time 59853973 ps
CPU time 1.16 seconds
Started Oct 15 11:39:07 AM UTC 24
Finished Oct 15 11:39:10 AM UTC 24
Peak memory 216888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174777908 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.2174777908
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/23.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/24.edn_intr_test.724062758
Short name T1072
Test name
Test status
Simulation time 30996872 ps
CPU time 1.09 seconds
Started Oct 15 11:39:07 AM UTC 24
Finished Oct 15 11:39:09 AM UTC 24
Peak memory 216644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724062758 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.724062758
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/24.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/25.edn_intr_test.2569132496
Short name T1071
Test name
Test status
Simulation time 21686960 ps
CPU time 0.95 seconds
Started Oct 15 11:39:07 AM UTC 24
Finished Oct 15 11:39:09 AM UTC 24
Peak memory 216832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569132496 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.2569132496
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/25.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/26.edn_intr_test.2727535700
Short name T1075
Test name
Test status
Simulation time 14480458 ps
CPU time 1.07 seconds
Started Oct 15 11:39:07 AM UTC 24
Finished Oct 15 11:39:10 AM UTC 24
Peak memory 216844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727535700 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.2727535700
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/26.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/27.edn_intr_test.3257266368
Short name T1073
Test name
Test status
Simulation time 23574492 ps
CPU time 0.95 seconds
Started Oct 15 11:39:07 AM UTC 24
Finished Oct 15 11:39:09 AM UTC 24
Peak memory 216904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257266368 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.3257266368
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/27.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/28.edn_intr_test.4067987981
Short name T1076
Test name
Test status
Simulation time 16178901 ps
CPU time 1.07 seconds
Started Oct 15 11:39:08 AM UTC 24
Finished Oct 15 11:39:10 AM UTC 24
Peak memory 216904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067987981 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.4067987981
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/28.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/29.edn_intr_test.1861523317
Short name T1080
Test name
Test status
Simulation time 12324669 ps
CPU time 0.97 seconds
Started Oct 15 11:39:09 AM UTC 24
Finished Oct 15 11:39:11 AM UTC 24
Peak memory 216904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861523317 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.1861523317
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/29.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_aliasing.1888531594
Short name T978
Test name
Test status
Simulation time 83810429 ps
CPU time 1.38 seconds
Started Oct 15 11:38:45 AM UTC 24
Finished Oct 15 11:38:47 AM UTC 24
Peak memory 216696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888531594 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.1888531594
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/3.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_bit_bash.1342637203
Short name T284
Test name
Test status
Simulation time 400390763 ps
CPU time 4.06 seconds
Started Oct 15 11:38:45 AM UTC 24
Finished Oct 15 11:38:50 AM UTC 24
Peak memory 217760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342637203 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.1342637203
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/3.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_hw_reset.1496699827
Short name T279
Test name
Test status
Simulation time 19752341 ps
CPU time 1.33 seconds
Started Oct 15 11:38:44 AM UTC 24
Finished Oct 15 11:38:46 AM UTC 24
Peak memory 216708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496699827 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.1496699827
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/3.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3366006242
Short name T979
Test name
Test status
Simulation time 41511151 ps
CPU time 1.43 seconds
Started Oct 15 11:38:45 AM UTC 24
Finished Oct 15 11:38:48 AM UTC 24
Peak memory 216716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3366006242 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.3366006242
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_rw.2554988833
Short name T280
Test name
Test status
Simulation time 36070906 ps
CPU time 1.38 seconds
Started Oct 15 11:38:45 AM UTC 24
Finished Oct 15 11:38:47 AM UTC 24
Peak memory 216644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554988833 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.2554988833
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/3.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/3.edn_intr_test.3702942686
Short name T975
Test name
Test status
Simulation time 11880848 ps
CPU time 1.25 seconds
Started Oct 15 11:38:44 AM UTC 24
Finished Oct 15 11:38:46 AM UTC 24
Peak memory 216780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702942686 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.3702942686
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/3.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/3.edn_same_csr_outstanding.1215919828
Short name T287
Test name
Test status
Simulation time 24990571 ps
CPU time 1.7 seconds
Started Oct 15 11:38:45 AM UTC 24
Finished Oct 15 11:38:48 AM UTC 24
Peak memory 216764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215919828 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_outstanding.1215919828
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/3.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/3.edn_tl_errors.1085899665
Short name T980
Test name
Test status
Simulation time 91248769 ps
CPU time 3.05 seconds
Started Oct 15 11:38:44 AM UTC 24
Finished Oct 15 11:38:48 AM UTC 24
Peak memory 227988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085899665 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.1085899665
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/3.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/3.edn_tl_intg_err.3518877707
Short name T309
Test name
Test status
Simulation time 199814018 ps
CPU time 2.28 seconds
Started Oct 15 11:38:44 AM UTC 24
Finished Oct 15 11:38:47 AM UTC 24
Peak memory 217820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518877707 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.3518877707
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/3.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/30.edn_intr_test.4176984869
Short name T1081
Test name
Test status
Simulation time 50286229 ps
CPU time 1.01 seconds
Started Oct 15 11:39:09 AM UTC 24
Finished Oct 15 11:39:11 AM UTC 24
Peak memory 216844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176984869 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.4176984869
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/30.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/31.edn_intr_test.109239745
Short name T1078
Test name
Test status
Simulation time 12932114 ps
CPU time 0.85 seconds
Started Oct 15 11:39:09 AM UTC 24
Finished Oct 15 11:39:11 AM UTC 24
Peak memory 216644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109239745 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.109239745
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/31.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/32.edn_intr_test.2624984098
Short name T1083
Test name
Test status
Simulation time 30410174 ps
CPU time 1.11 seconds
Started Oct 15 11:39:09 AM UTC 24
Finished Oct 15 11:39:11 AM UTC 24
Peak memory 216888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624984098 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.2624984098
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/32.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/33.edn_intr_test.2409256089
Short name T1079
Test name
Test status
Simulation time 52999025 ps
CPU time 0.82 seconds
Started Oct 15 11:39:09 AM UTC 24
Finished Oct 15 11:39:11 AM UTC 24
Peak memory 216888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409256089 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.2409256089
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/33.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/34.edn_intr_test.3209064410
Short name T1082
Test name
Test status
Simulation time 43996834 ps
CPU time 0.94 seconds
Started Oct 15 11:39:09 AM UTC 24
Finished Oct 15 11:39:11 AM UTC 24
Peak memory 216844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209064410 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.3209064410
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/34.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/35.edn_intr_test.2914708974
Short name T1085
Test name
Test status
Simulation time 75292949 ps
CPU time 1.16 seconds
Started Oct 15 11:39:09 AM UTC 24
Finished Oct 15 11:39:11 AM UTC 24
Peak memory 216888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914708974 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.2914708974
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/35.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/36.edn_intr_test.3318699636
Short name T1084
Test name
Test status
Simulation time 37030958 ps
CPU time 1.07 seconds
Started Oct 15 11:39:09 AM UTC 24
Finished Oct 15 11:39:11 AM UTC 24
Peak memory 216844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318699636 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.3318699636
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/36.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/37.edn_intr_test.3238512469
Short name T1086
Test name
Test status
Simulation time 34501564 ps
CPU time 1.05 seconds
Started Oct 15 11:39:09 AM UTC 24
Finished Oct 15 11:39:11 AM UTC 24
Peak memory 216888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238512469 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.3238512469
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/37.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/38.edn_intr_test.2409930904
Short name T1087
Test name
Test status
Simulation time 11695856 ps
CPU time 1 seconds
Started Oct 15 11:39:09 AM UTC 24
Finished Oct 15 11:39:11 AM UTC 24
Peak memory 216904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409930904 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.2409930904
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/38.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/39.edn_intr_test.460153144
Short name T1088
Test name
Test status
Simulation time 35915579 ps
CPU time 1.05 seconds
Started Oct 15 11:39:09 AM UTC 24
Finished Oct 15 11:39:11 AM UTC 24
Peak memory 216704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460153144 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.460153144
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/39.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_aliasing.4287295301
Short name T985
Test name
Test status
Simulation time 47887927 ps
CPU time 1.61 seconds
Started Oct 15 11:38:48 AM UTC 24
Finished Oct 15 11:38:50 AM UTC 24
Peak memory 216692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287295301 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.4287295301
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/4.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_bit_bash.2170058906
Short name T285
Test name
Test status
Simulation time 134838177 ps
CPU time 4.13 seconds
Started Oct 15 11:38:47 AM UTC 24
Finished Oct 15 11:38:53 AM UTC 24
Peak memory 217952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170058906 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.2170058906
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/4.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_hw_reset.72278099
Short name T982
Test name
Test status
Simulation time 14264820 ps
CPU time 1.35 seconds
Started Oct 15 11:38:46 AM UTC 24
Finished Oct 15 11:38:49 AM UTC 24
Peak memory 216720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72278099 -assert nopostproc +UVM_TESTNAME=edn_
base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ed
n-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.72278099
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/4.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.899434582
Short name T984
Test name
Test status
Simulation time 80945441 ps
CPU time 1.26 seconds
Started Oct 15 11:38:48 AM UTC 24
Finished Oct 15 11:38:50 AM UTC 24
Peak memory 227056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=899434582 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.899434582
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_rw.2350729444
Short name T281
Test name
Test status
Simulation time 34754440 ps
CPU time 1.1 seconds
Started Oct 15 11:38:47 AM UTC 24
Finished Oct 15 11:38:50 AM UTC 24
Peak memory 216644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350729444 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.2350729444
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/4.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/4.edn_intr_test.2154335498
Short name T981
Test name
Test status
Simulation time 41280618 ps
CPU time 1.23 seconds
Started Oct 15 11:38:46 AM UTC 24
Finished Oct 15 11:38:49 AM UTC 24
Peak memory 216720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154335498 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.2154335498
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/4.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/4.edn_same_csr_outstanding.1185997105
Short name T288
Test name
Test status
Simulation time 19705135 ps
CPU time 1.6 seconds
Started Oct 15 11:38:48 AM UTC 24
Finished Oct 15 11:38:50 AM UTC 24
Peak memory 216752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185997105 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_outstanding.1185997105
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/4.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/4.edn_tl_errors.4069292320
Short name T983
Test name
Test status
Simulation time 527681166 ps
CPU time 3.43 seconds
Started Oct 15 11:38:45 AM UTC 24
Finished Oct 15 11:38:50 AM UTC 24
Peak memory 227988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069292320 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.4069292320
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/4.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/40.edn_intr_test.4226231861
Short name T1089
Test name
Test status
Simulation time 14444321 ps
CPU time 1.1 seconds
Started Oct 15 11:39:09 AM UTC 24
Finished Oct 15 11:39:11 AM UTC 24
Peak memory 216844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226231861 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.4226231861
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/40.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/41.edn_intr_test.2006467589
Short name T1090
Test name
Test status
Simulation time 25251447 ps
CPU time 0.83 seconds
Started Oct 15 11:39:10 AM UTC 24
Finished Oct 15 11:39:12 AM UTC 24
Peak memory 216904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006467589 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.2006467589
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/41.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/42.edn_intr_test.3980550701
Short name T1095
Test name
Test status
Simulation time 17279012 ps
CPU time 1.31 seconds
Started Oct 15 11:39:10 AM UTC 24
Finished Oct 15 11:39:13 AM UTC 24
Peak memory 216904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980550701 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.3980550701
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/42.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/43.edn_intr_test.2827662571
Short name T1091
Test name
Test status
Simulation time 42841865 ps
CPU time 1.13 seconds
Started Oct 15 11:39:10 AM UTC 24
Finished Oct 15 11:39:13 AM UTC 24
Peak memory 216904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827662571 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.2827662571
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/43.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/44.edn_intr_test.2753818763
Short name T1092
Test name
Test status
Simulation time 24161876 ps
CPU time 1.05 seconds
Started Oct 15 11:39:10 AM UTC 24
Finished Oct 15 11:39:13 AM UTC 24
Peak memory 216844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753818763 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.2753818763
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/44.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/45.edn_intr_test.3909716357
Short name T1093
Test name
Test status
Simulation time 40986356 ps
CPU time 1.08 seconds
Started Oct 15 11:39:11 AM UTC 24
Finished Oct 15 11:39:13 AM UTC 24
Peak memory 216888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909716357 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.3909716357
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/45.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/46.edn_intr_test.373488536
Short name T1094
Test name
Test status
Simulation time 13409769 ps
CPU time 1.05 seconds
Started Oct 15 11:39:11 AM UTC 24
Finished Oct 15 11:39:13 AM UTC 24
Peak memory 216644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373488536 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.373488536
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/46.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/47.edn_intr_test.3362329177
Short name T1098
Test name
Test status
Simulation time 60734533 ps
CPU time 1.08 seconds
Started Oct 15 11:39:11 AM UTC 24
Finished Oct 15 11:39:13 AM UTC 24
Peak memory 216844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362329177 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.3362329177
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/47.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/48.edn_intr_test.2835930622
Short name T1096
Test name
Test status
Simulation time 34442238 ps
CPU time 1.05 seconds
Started Oct 15 11:39:11 AM UTC 24
Finished Oct 15 11:39:13 AM UTC 24
Peak memory 216888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835930622 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.2835930622
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/48.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/49.edn_intr_test.1552409779
Short name T1097
Test name
Test status
Simulation time 42880615 ps
CPU time 1.06 seconds
Started Oct 15 11:39:11 AM UTC 24
Finished Oct 15 11:39:13 AM UTC 24
Peak memory 216844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552409779 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.1552409779
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/49.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2529315293
Short name T988
Test name
Test status
Simulation time 34063414 ps
CPU time 1.53 seconds
Started Oct 15 11:38:49 AM UTC 24
Finished Oct 15 11:38:52 AM UTC 24
Peak memory 226956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2529315293 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.2529315293
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/5.edn_csr_rw.3511469972
Short name T987
Test name
Test status
Simulation time 39521200 ps
CPU time 1.26 seconds
Started Oct 15 11:38:49 AM UTC 24
Finished Oct 15 11:38:51 AM UTC 24
Peak memory 216644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511469972 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.3511469972
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/5.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/5.edn_intr_test.2096452989
Short name T986
Test name
Test status
Simulation time 14787577 ps
CPU time 1.2 seconds
Started Oct 15 11:38:49 AM UTC 24
Finished Oct 15 11:38:51 AM UTC 24
Peak memory 216720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096452989 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.2096452989
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/5.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/5.edn_same_csr_outstanding.1421771650
Short name T289
Test name
Test status
Simulation time 115303288 ps
CPU time 1.57 seconds
Started Oct 15 11:38:49 AM UTC 24
Finished Oct 15 11:38:52 AM UTC 24
Peak memory 216764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421771650 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_outstanding.1421771650
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/5.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/5.edn_tl_errors.2847467358
Short name T989
Test name
Test status
Simulation time 230063630 ps
CPU time 2.4 seconds
Started Oct 15 11:38:49 AM UTC 24
Finished Oct 15 11:38:52 AM UTC 24
Peak memory 228040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847467358 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.2847467358
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/5.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/5.edn_tl_intg_err.4265010238
Short name T307
Test name
Test status
Simulation time 87739702 ps
CPU time 2.11 seconds
Started Oct 15 11:38:49 AM UTC 24
Finished Oct 15 11:38:52 AM UTC 24
Peak memory 217808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265010238 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.4265010238
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/5.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.4189809944
Short name T991
Test name
Test status
Simulation time 29353928 ps
CPU time 1.15 seconds
Started Oct 15 11:38:50 AM UTC 24
Finished Oct 15 11:38:53 AM UTC 24
Peak memory 226956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=4189809944 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.4189809944
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/6.edn_csr_rw.4219545546
Short name T990
Test name
Test status
Simulation time 18279438 ps
CPU time 1.15 seconds
Started Oct 15 11:38:50 AM UTC 24
Finished Oct 15 11:38:52 AM UTC 24
Peak memory 216704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219545546 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.4219545546
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/6.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/6.edn_intr_test.2619794365
Short name T992
Test name
Test status
Simulation time 13109839 ps
CPU time 1.32 seconds
Started Oct 15 11:38:50 AM UTC 24
Finished Oct 15 11:38:53 AM UTC 24
Peak memory 216720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619794365 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.2619794365
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/6.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/6.edn_same_csr_outstanding.2581632361
Short name T290
Test name
Test status
Simulation time 18253209 ps
CPU time 1.46 seconds
Started Oct 15 11:38:50 AM UTC 24
Finished Oct 15 11:38:53 AM UTC 24
Peak memory 216764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581632361 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_outstanding.2581632361
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/6.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_errors.4070150845
Short name T993
Test name
Test status
Simulation time 247158901 ps
CPU time 2.67 seconds
Started Oct 15 11:38:49 AM UTC 24
Finished Oct 15 11:38:53 AM UTC 24
Peak memory 228112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070150845 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.4070150845
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/6.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_intg_err.539264501
Short name T308
Test name
Test status
Simulation time 145684948 ps
CPU time 2.19 seconds
Started Oct 15 11:38:50 AM UTC 24
Finished Oct 15 11:38:53 AM UTC 24
Peak memory 217768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539264501 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.539264501
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/6.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3521020620
Short name T999
Test name
Test status
Simulation time 81110240 ps
CPU time 1.31 seconds
Started Oct 15 11:38:53 AM UTC 24
Finished Oct 15 11:38:55 AM UTC 24
Peak memory 226956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3521020620 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.3521020620
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_rw.442592876
Short name T994
Test name
Test status
Simulation time 15412482 ps
CPU time 0.99 seconds
Started Oct 15 11:38:52 AM UTC 24
Finished Oct 15 11:38:54 AM UTC 24
Peak memory 216644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442592876 -assert nopostproc +UVM_TESTNAME=edn_base_
test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.442592876
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/7.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/7.edn_intr_test.4024551446
Short name T995
Test name
Test status
Simulation time 14334351 ps
CPU time 1.21 seconds
Started Oct 15 11:38:52 AM UTC 24
Finished Oct 15 11:38:54 AM UTC 24
Peak memory 216708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024551446 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.4024551446
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/7.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/7.edn_same_csr_outstanding.3185517831
Short name T996
Test name
Test status
Simulation time 21929339 ps
CPU time 1.65 seconds
Started Oct 15 11:38:52 AM UTC 24
Finished Oct 15 11:38:54 AM UTC 24
Peak memory 216720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185517831 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_outstanding.3185517831
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/7.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_errors.3622957836
Short name T1001
Test name
Test status
Simulation time 277585413 ps
CPU time 3.08 seconds
Started Oct 15 11:38:52 AM UTC 24
Finished Oct 15 11:38:56 AM UTC 24
Peak memory 228312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622957836 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.3622957836
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/7.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_intg_err.1110299980
Short name T997
Test name
Test status
Simulation time 146741349 ps
CPU time 2.13 seconds
Started Oct 15 11:38:52 AM UTC 24
Finished Oct 15 11:38:55 AM UTC 24
Peak memory 217808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110299980 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.1110299980
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/7.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.4029876119
Short name T1007
Test name
Test status
Simulation time 79198914 ps
CPU time 1.5 seconds
Started Oct 15 11:38:54 AM UTC 24
Finished Oct 15 11:38:57 AM UTC 24
Peak memory 226956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=4029876119 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.4029876119
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_rw.973083878
Short name T998
Test name
Test status
Simulation time 15622403 ps
CPU time 1.06 seconds
Started Oct 15 11:38:53 AM UTC 24
Finished Oct 15 11:38:55 AM UTC 24
Peak memory 216720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973083878 -assert nopostproc +UVM_TESTNAME=edn_base_
test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.973083878
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/8.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/8.edn_intr_test.3655137906
Short name T1000
Test name
Test status
Simulation time 23534991 ps
CPU time 1.22 seconds
Started Oct 15 11:38:53 AM UTC 24
Finished Oct 15 11:38:55 AM UTC 24
Peak memory 216720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655137906 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.3655137906
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/8.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/8.edn_same_csr_outstanding.3513073479
Short name T1004
Test name
Test status
Simulation time 87756460 ps
CPU time 1.15 seconds
Started Oct 15 11:38:54 AM UTC 24
Finished Oct 15 11:38:57 AM UTC 24
Peak memory 216720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513073479 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_outstanding.3513073479
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/8.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_errors.3747788077
Short name T1002
Test name
Test status
Simulation time 152267733 ps
CPU time 2.13 seconds
Started Oct 15 11:38:53 AM UTC 24
Finished Oct 15 11:38:56 AM UTC 24
Peak memory 228252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747788077 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.3747788077
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/8.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_intg_err.829652598
Short name T310
Test name
Test status
Simulation time 163201945 ps
CPU time 2.24 seconds
Started Oct 15 11:38:53 AM UTC 24
Finished Oct 15 11:38:56 AM UTC 24
Peak memory 218024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829652598 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.829652598
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/8.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.981416641
Short name T1009
Test name
Test status
Simulation time 106210782 ps
CPU time 2.02 seconds
Started Oct 15 11:38:54 AM UTC 24
Finished Oct 15 11:38:58 AM UTC 24
Peak memory 228236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=981416641 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.981416641
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_rw.1659082192
Short name T1005
Test name
Test status
Simulation time 21792351 ps
CPU time 1.08 seconds
Started Oct 15 11:38:54 AM UTC 24
Finished Oct 15 11:38:57 AM UTC 24
Peak memory 216644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659082192 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.1659082192
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/9.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/9.edn_intr_test.3289426931
Short name T1006
Test name
Test status
Simulation time 12554050 ps
CPU time 1.24 seconds
Started Oct 15 11:38:54 AM UTC 24
Finished Oct 15 11:38:57 AM UTC 24
Peak memory 216632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289426931 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.3289426931
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/9.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/9.edn_same_csr_outstanding.1682853304
Short name T1008
Test name
Test status
Simulation time 72435174 ps
CPU time 1.39 seconds
Started Oct 15 11:38:54 AM UTC 24
Finished Oct 15 11:38:57 AM UTC 24
Peak memory 216764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682853304 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_outstanding.1682853304
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/9.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_errors.719030700
Short name T1014
Test name
Test status
Simulation time 496841322 ps
CPU time 3.59 seconds
Started Oct 15 11:38:54 AM UTC 24
Finished Oct 15 11:38:59 AM UTC 24
Peak memory 228304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719030700 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.719030700
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/9.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_intg_err.1155183768
Short name T1012
Test name
Test status
Simulation time 964754985 ps
CPU time 3.12 seconds
Started Oct 15 11:38:54 AM UTC 24
Finished Oct 15 11:38:59 AM UTC 24
Peak memory 217804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155183768 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.1155183768
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/9.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/0.edn_alert_test.4101674398
Short name T59
Test name
Test status
Simulation time 33420436 ps
CPU time 1.47 seconds
Started Oct 15 11:24:47 AM UTC 24
Finished Oct 15 11:24:50 AM UTC 24
Peak memory 217952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101674398 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.4101674398
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/0.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/0.edn_err.3928272159
Short name T5
Test name
Test status
Simulation time 65248007 ps
CPU time 1.23 seconds
Started Oct 15 11:24:44 AM UTC 24
Finished Oct 15 11:24:46 AM UTC 24
Peak memory 229912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928272159 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 0.edn_err.3928272159
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/0.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/0.edn_genbits.2211436798
Short name T3
Test name
Test status
Simulation time 56062946 ps
CPU time 1.53 seconds
Started Oct 15 11:24:40 AM UTC 24
Finished Oct 15 11:24:43 AM UTC 24
Peak memory 229896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211436798 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_genbits.2211436798
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/0.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/0.edn_intr.801876215
Short name T4
Test name
Test status
Simulation time 21191019 ps
CPU time 1.34 seconds
Started Oct 15 11:24:43 AM UTC 24
Finished Oct 15 11:24:45 AM UTC 24
Peak memory 229972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801876215 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 0.edn_intr.801876215
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/0.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/0.edn_regwen.382829995
Short name T2
Test name
Test status
Simulation time 167142133 ps
CPU time 1.34 seconds
Started Oct 15 11:24:39 AM UTC 24
Finished Oct 15 11:24:42 AM UTC 24
Peak memory 217740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382829995 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 0.edn_regwen.382829995
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/0.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/0.edn_sec_cm.11960454
Short name T15
Test name
Test status
Simulation time 226400588 ps
CPU time 6.5 seconds
Started Oct 15 11:24:46 AM UTC 24
Finished Oct 15 11:24:54 AM UTC 24
Peak memory 259800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11960454 -assert nopostproc +UVM_TESTNAME=edn_base_
test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.11960454
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/0.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/0.edn_smoke.290657736
Short name T1
Test name
Test status
Simulation time 46395310 ps
CPU time 1.36 seconds
Started Oct 15 11:24:38 AM UTC 24
Finished Oct 15 11:24:41 AM UTC 24
Peak memory 228404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290657736 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 0.edn_smoke.290657736
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/0.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/1.edn_alert.1717971873
Short name T10
Test name
Test status
Simulation time 154881663 ps
CPU time 1.64 seconds
Started Oct 15 11:24:50 AM UTC 24
Finished Oct 15 11:24:53 AM UTC 24
Peak memory 232076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717971873 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 1.edn_alert.1717971873
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/1.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/1.edn_alert_test.3675729926
Short name T67
Test name
Test status
Simulation time 12627174 ps
CPU time 1.3 seconds
Started Oct 15 11:24:54 AM UTC 24
Finished Oct 15 11:24:56 AM UTC 24
Peak memory 218300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675729926 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.3675729926
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/1.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/1.edn_disable.123027927
Short name T38
Test name
Test status
Simulation time 12392823 ps
CPU time 1.14 seconds
Started Oct 15 11:24:53 AM UTC 24
Finished Oct 15 11:24:55 AM UTC 24
Peak memory 228036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123027927 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.123027927
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/1.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/1.edn_err.3857777767
Short name T17
Test name
Test status
Simulation time 75464487 ps
CPU time 1.62 seconds
Started Oct 15 11:24:51 AM UTC 24
Finished Oct 15 11:24:53 AM UTC 24
Peak memory 231960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857777767 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 1.edn_err.3857777767
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/1.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/1.edn_intr.2414241420
Short name T28
Test name
Test status
Simulation time 22629518 ps
CPU time 1.55 seconds
Started Oct 15 11:24:50 AM UTC 24
Finished Oct 15 11:24:53 AM UTC 24
Peak memory 229968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414241420 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 1.edn_intr.2414241420
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/1.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/1.edn_regwen.3312539125
Short name T25
Test name
Test status
Simulation time 16680417 ps
CPU time 1.47 seconds
Started Oct 15 11:24:47 AM UTC 24
Finished Oct 15 11:24:50 AM UTC 24
Peak memory 217760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312539125 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 1.edn_regwen.3312539125
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/1.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/1.edn_smoke.2763098974
Short name T71
Test name
Test status
Simulation time 19537439 ps
CPU time 1.46 seconds
Started Oct 15 11:24:47 AM UTC 24
Finished Oct 15 11:24:50 AM UTC 24
Peak memory 227860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763098974 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 1.edn_smoke.2763098974
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/1.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/1.edn_stress_all.1221674045
Short name T60
Test name
Test status
Simulation time 42833956 ps
CPU time 2.08 seconds
Started Oct 15 11:24:48 AM UTC 24
Finished Oct 15 11:24:51 AM UTC 24
Peak memory 218212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221674045 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.1221674045
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/1.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/10.edn_alert.2723660110
Short name T84
Test name
Test status
Simulation time 47611712 ps
CPU time 1.49 seconds
Started Oct 15 11:25:30 AM UTC 24
Finished Oct 15 11:25:32 AM UTC 24
Peak memory 232080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723660110 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 10.edn_alert.2723660110
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/10.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/10.edn_alert_test.3514885189
Short name T372
Test name
Test status
Simulation time 19477803 ps
CPU time 0.97 seconds
Started Oct 15 11:25:31 AM UTC 24
Finished Oct 15 11:25:33 AM UTC 24
Peak memory 217920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514885189 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.3514885189
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/10.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/10.edn_disable_auto_req_mode.3006410502
Short name T85
Test name
Test status
Simulation time 74357033 ps
CPU time 1.48 seconds
Started Oct 15 11:25:31 AM UTC 24
Finished Oct 15 11:25:33 AM UTC 24
Peak memory 231952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006410502 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable_auto_req_mode.3006410502
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/10.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/10.edn_err.2633647454
Short name T161
Test name
Test status
Simulation time 39175349 ps
CPU time 1.31 seconds
Started Oct 15 11:25:30 AM UTC 24
Finished Oct 15 11:25:32 AM UTC 24
Peak memory 227864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633647454 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 10.edn_err.2633647454
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/10.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/10.edn_genbits.3134991073
Short name T303
Test name
Test status
Simulation time 70188577 ps
CPU time 1.33 seconds
Started Oct 15 11:25:29 AM UTC 24
Finished Oct 15 11:25:31 AM UTC 24
Peak memory 230044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134991073 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_genbits.3134991073
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/10.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/10.edn_smoke.883971787
Short name T370
Test name
Test status
Simulation time 42846771 ps
CPU time 1.29 seconds
Started Oct 15 11:25:28 AM UTC 24
Finished Oct 15 11:25:31 AM UTC 24
Peak memory 227848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883971787 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 10.edn_smoke.883971787
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/10.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/10.edn_stress_all_with_rand_reset.3254539748
Short name T36
Test name
Test status
Simulation time 2374115740 ps
CPU time 57.18 seconds
Started Oct 15 11:25:29 AM UTC 24
Finished Oct 15 11:26:27 AM UTC 24
Peak memory 233672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3254539748 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all
_with_rand_reset.3254539748
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/10.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/100.edn_alert.655067418
Short name T694
Test name
Test status
Simulation time 35731776 ps
CPU time 1.34 seconds
Started Oct 15 11:27:51 AM UTC 24
Finished Oct 15 11:27:54 AM UTC 24
Peak memory 230032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655067418 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 100.edn_alert.655067418
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/100.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/100.edn_genbits.2463305056
Short name T693
Test name
Test status
Simulation time 63735088 ps
CPU time 1.28 seconds
Started Oct 15 11:27:51 AM UTC 24
Finished Oct 15 11:27:54 AM UTC 24
Peak memory 227844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463305056 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 100.edn_genbits.2463305056
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/100.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/101.edn_alert.475978789
Short name T697
Test name
Test status
Simulation time 62520544 ps
CPU time 1.38 seconds
Started Oct 15 11:27:53 AM UTC 24
Finished Oct 15 11:27:55 AM UTC 24
Peak memory 232080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475978789 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 101.edn_alert.475978789
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/101.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/101.edn_genbits.660270031
Short name T695
Test name
Test status
Simulation time 48716991 ps
CPU time 1.29 seconds
Started Oct 15 11:27:51 AM UTC 24
Finished Oct 15 11:27:54 AM UTC 24
Peak memory 229968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660270031 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 101.edn_genbits.660270031
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/101.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/102.edn_alert.1568352208
Short name T272
Test name
Test status
Simulation time 49466452 ps
CPU time 1.3 seconds
Started Oct 15 11:27:53 AM UTC 24
Finished Oct 15 11:27:55 AM UTC 24
Peak memory 227960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568352208 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 102.edn_alert.1568352208
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/102.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/102.edn_genbits.3427447472
Short name T696
Test name
Test status
Simulation time 37231820 ps
CPU time 1.27 seconds
Started Oct 15 11:27:53 AM UTC 24
Finished Oct 15 11:27:55 AM UTC 24
Peak memory 230104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427447472 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 102.edn_genbits.3427447472
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/102.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/103.edn_alert.1286390900
Short name T700
Test name
Test status
Simulation time 220700264 ps
CPU time 1.75 seconds
Started Oct 15 11:27:53 AM UTC 24
Finished Oct 15 11:27:56 AM UTC 24
Peak memory 227960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286390900 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 103.edn_alert.1286390900
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/103.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/104.edn_alert.410509642
Short name T698
Test name
Test status
Simulation time 75275049 ps
CPU time 1.22 seconds
Started Oct 15 11:27:53 AM UTC 24
Finished Oct 15 11:27:55 AM UTC 24
Peak memory 232080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410509642 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 104.edn_alert.410509642
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/104.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/104.edn_genbits.3874130487
Short name T702
Test name
Test status
Simulation time 125197028 ps
CPU time 1.79 seconds
Started Oct 15 11:27:53 AM UTC 24
Finished Oct 15 11:27:56 AM UTC 24
Peak memory 229688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874130487 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 104.edn_genbits.3874130487
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/104.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/105.edn_alert.993924280
Short name T706
Test name
Test status
Simulation time 70128651 ps
CPU time 1.48 seconds
Started Oct 15 11:27:54 AM UTC 24
Finished Oct 15 11:27:57 AM UTC 24
Peak memory 232080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993924280 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 105.edn_alert.993924280
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/105.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/105.edn_genbits.3164465986
Short name T710
Test name
Test status
Simulation time 29450084 ps
CPU time 1.85 seconds
Started Oct 15 11:27:54 AM UTC 24
Finished Oct 15 11:27:57 AM UTC 24
Peak memory 231944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164465986 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 105.edn_genbits.3164465986
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/105.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/106.edn_alert.1332368203
Short name T707
Test name
Test status
Simulation time 66678918 ps
CPU time 1.47 seconds
Started Oct 15 11:27:54 AM UTC 24
Finished Oct 15 11:27:57 AM UTC 24
Peak memory 232076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332368203 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 106.edn_alert.1332368203
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/106.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/106.edn_genbits.928001336
Short name T709
Test name
Test status
Simulation time 30887556 ps
CPU time 1.56 seconds
Started Oct 15 11:27:54 AM UTC 24
Finished Oct 15 11:27:57 AM UTC 24
Peak memory 232152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928001336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 106.edn_genbits.928001336
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/106.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/107.edn_alert.1733670652
Short name T294
Test name
Test status
Simulation time 270927617 ps
CPU time 1.24 seconds
Started Oct 15 11:27:54 AM UTC 24
Finished Oct 15 11:27:56 AM UTC 24
Peak memory 232076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733670652 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 107.edn_alert.1733670652
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/107.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/107.edn_genbits.1342442666
Short name T703
Test name
Test status
Simulation time 71301985 ps
CPU time 1.15 seconds
Started Oct 15 11:27:54 AM UTC 24
Finished Oct 15 11:27:56 AM UTC 24
Peak memory 229900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342442666 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 107.edn_genbits.1342442666
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/107.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/108.edn_alert.1146803469
Short name T704
Test name
Test status
Simulation time 169060240 ps
CPU time 1.23 seconds
Started Oct 15 11:27:54 AM UTC 24
Finished Oct 15 11:27:57 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146803469 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 108.edn_alert.1146803469
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/108.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/108.edn_genbits.1643409432
Short name T711
Test name
Test status
Simulation time 94072165 ps
CPU time 1.67 seconds
Started Oct 15 11:27:54 AM UTC 24
Finished Oct 15 11:27:57 AM UTC 24
Peak memory 229908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643409432 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 108.edn_genbits.1643409432
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/108.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/109.edn_alert.2014341618
Short name T712
Test name
Test status
Simulation time 38664458 ps
CPU time 1.62 seconds
Started Oct 15 11:27:54 AM UTC 24
Finished Oct 15 11:27:57 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014341618 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 109.edn_alert.2014341618
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/109.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/109.edn_genbits.2977709456
Short name T708
Test name
Test status
Simulation time 95397952 ps
CPU time 1.35 seconds
Started Oct 15 11:27:54 AM UTC 24
Finished Oct 15 11:27:57 AM UTC 24
Peak memory 230044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977709456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 109.edn_genbits.2977709456
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/109.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/11.edn_alert.4177587050
Short name T96
Test name
Test status
Simulation time 92422141 ps
CPU time 1.48 seconds
Started Oct 15 11:25:32 AM UTC 24
Finished Oct 15 11:25:35 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177587050 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 11.edn_alert.4177587050
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/11.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/11.edn_alert_test.1895974545
Short name T375
Test name
Test status
Simulation time 54284394 ps
CPU time 1.42 seconds
Started Oct 15 11:25:33 AM UTC 24
Finished Oct 15 11:25:36 AM UTC 24
Peak memory 217892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895974545 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.1895974545
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/11.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/11.edn_disable.3455014685
Short name T104
Test name
Test status
Simulation time 25445270 ps
CPU time 1.12 seconds
Started Oct 15 11:25:32 AM UTC 24
Finished Oct 15 11:25:34 AM UTC 24
Peak memory 227916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455014685 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.3455014685
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/11.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/11.edn_disable_auto_req_mode.529347634
Short name T374
Test name
Test status
Simulation time 46742447 ps
CPU time 2.11 seconds
Started Oct 15 11:25:32 AM UTC 24
Finished Oct 15 11:25:35 AM UTC 24
Peak memory 229368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529347634 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable_auto_req_mode.529347634
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/11.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/11.edn_err.1647877286
Short name T162
Test name
Test status
Simulation time 30259184 ps
CPU time 1.84 seconds
Started Oct 15 11:25:32 AM UTC 24
Finished Oct 15 11:25:35 AM UTC 24
Peak memory 244316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647877286 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 11.edn_err.1647877286
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/11.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/11.edn_genbits.2524676011
Short name T42
Test name
Test status
Simulation time 56329853 ps
CPU time 1.62 seconds
Started Oct 15 11:25:31 AM UTC 24
Finished Oct 15 11:25:34 AM UTC 24
Peak memory 230104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524676011 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_genbits.2524676011
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/11.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/11.edn_intr.3631330170
Short name T105
Test name
Test status
Simulation time 23682863 ps
CPU time 1.46 seconds
Started Oct 15 11:25:32 AM UTC 24
Finished Oct 15 11:25:35 AM UTC 24
Peak memory 228288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631330170 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 11.edn_intr.3631330170
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/11.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/11.edn_smoke.2320947012
Short name T373
Test name
Test status
Simulation time 43635056 ps
CPU time 1.3 seconds
Started Oct 15 11:25:31 AM UTC 24
Finished Oct 15 11:25:33 AM UTC 24
Peak memory 227864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320947012 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 11.edn_smoke.2320947012
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/11.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/11.edn_stress_all.1634004744
Short name T116
Test name
Test status
Simulation time 303261137 ps
CPU time 4.77 seconds
Started Oct 15 11:25:31 AM UTC 24
Finished Oct 15 11:25:37 AM UTC 24
Peak memory 228868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634004744 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.1634004744
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/11.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/110.edn_alert.2671774626
Short name T172
Test name
Test status
Simulation time 113563747 ps
CPU time 1.53 seconds
Started Oct 15 11:27:54 AM UTC 24
Finished Oct 15 11:27:57 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671774626 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 110.edn_alert.2671774626
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/110.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/110.edn_genbits.2254285080
Short name T705
Test name
Test status
Simulation time 27034280 ps
CPU time 1.13 seconds
Started Oct 15 11:27:54 AM UTC 24
Finished Oct 15 11:27:57 AM UTC 24
Peak memory 227848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254285080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 110.edn_genbits.2254285080
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/110.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/112.edn_alert.898494936
Short name T295
Test name
Test status
Simulation time 27163562 ps
CPU time 1.33 seconds
Started Oct 15 11:27:56 AM UTC 24
Finished Oct 15 11:27:58 AM UTC 24
Peak memory 230032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898494936 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 112.edn_alert.898494936
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/112.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/112.edn_genbits.124716513
Short name T714
Test name
Test status
Simulation time 102283852 ps
CPU time 1.2 seconds
Started Oct 15 11:27:56 AM UTC 24
Finished Oct 15 11:27:58 AM UTC 24
Peak memory 229904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124716513 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 112.edn_genbits.124716513
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/112.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/113.edn_alert.3069220105
Short name T713
Test name
Test status
Simulation time 104867782 ps
CPU time 1.14 seconds
Started Oct 15 11:27:56 AM UTC 24
Finished Oct 15 11:27:58 AM UTC 24
Peak memory 227980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069220105 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 113.edn_alert.3069220105
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/113.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/113.edn_genbits.4071362979
Short name T716
Test name
Test status
Simulation time 66611978 ps
CPU time 2.08 seconds
Started Oct 15 11:27:56 AM UTC 24
Finished Oct 15 11:27:59 AM UTC 24
Peak memory 231096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071362979 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 113.edn_genbits.4071362979
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/113.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/114.edn_alert.2009243810
Short name T717
Test name
Test status
Simulation time 190113838 ps
CPU time 1.2 seconds
Started Oct 15 11:27:57 AM UTC 24
Finished Oct 15 11:27:59 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009243810 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 114.edn_alert.2009243810
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/114.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/114.edn_genbits.925960010
Short name T715
Test name
Test status
Simulation time 29019178 ps
CPU time 1.32 seconds
Started Oct 15 11:27:56 AM UTC 24
Finished Oct 15 11:27:58 AM UTC 24
Peak memory 230044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925960010 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 114.edn_genbits.925960010
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/114.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/115.edn_alert.582825719
Short name T718
Test name
Test status
Simulation time 51092253 ps
CPU time 1.2 seconds
Started Oct 15 11:27:57 AM UTC 24
Finished Oct 15 11:27:59 AM UTC 24
Peak memory 232076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582825719 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 115.edn_alert.582825719
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/115.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/115.edn_genbits.2876518932
Short name T720
Test name
Test status
Simulation time 37369301 ps
CPU time 1.46 seconds
Started Oct 15 11:27:57 AM UTC 24
Finished Oct 15 11:27:59 AM UTC 24
Peak memory 231956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876518932 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 115.edn_genbits.2876518932
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/115.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/116.edn_alert.3292456222
Short name T719
Test name
Test status
Simulation time 91408672 ps
CPU time 1.14 seconds
Started Oct 15 11:27:57 AM UTC 24
Finished Oct 15 11:27:59 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292456222 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 116.edn_alert.3292456222
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/116.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/116.edn_genbits.1865971061
Short name T722
Test name
Test status
Simulation time 53956524 ps
CPU time 1.37 seconds
Started Oct 15 11:27:57 AM UTC 24
Finished Oct 15 11:28:02 AM UTC 24
Peak memory 229904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865971061 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 116.edn_genbits.1865971061
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/116.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/117.edn_genbits.4222774195
Short name T729
Test name
Test status
Simulation time 90235566 ps
CPU time 1.28 seconds
Started Oct 15 11:27:57 AM UTC 24
Finished Oct 15 11:28:02 AM UTC 24
Peak memory 231956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222774195 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 117.edn_genbits.4222774195
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/117.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/118.edn_alert.3478887425
Short name T730
Test name
Test status
Simulation time 50004974 ps
CPU time 1.23 seconds
Started Oct 15 11:27:57 AM UTC 24
Finished Oct 15 11:28:03 AM UTC 24
Peak memory 232076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478887425 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 118.edn_alert.3478887425
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/118.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/119.edn_alert.2569023907
Short name T296
Test name
Test status
Simulation time 162350121 ps
CPU time 1.15 seconds
Started Oct 15 11:27:58 AM UTC 24
Finished Oct 15 11:28:04 AM UTC 24
Peak memory 232076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569023907 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 119.edn_alert.2569023907
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/119.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/119.edn_genbits.2752574745
Short name T735
Test name
Test status
Simulation time 38238903 ps
CPU time 1.21 seconds
Started Oct 15 11:27:58 AM UTC 24
Finished Oct 15 11:28:04 AM UTC 24
Peak memory 230104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752574745 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 119.edn_genbits.2752574745
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/119.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/12.edn_alert_test.3019075214
Short name T378
Test name
Test status
Simulation time 13624340 ps
CPU time 1.11 seconds
Started Oct 15 11:25:36 AM UTC 24
Finished Oct 15 11:25:38 AM UTC 24
Peak memory 218296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019075214 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.3019075214
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/12.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/12.edn_disable_auto_req_mode.496228739
Short name T166
Test name
Test status
Simulation time 60613092 ps
CPU time 2.11 seconds
Started Oct 15 11:25:36 AM UTC 24
Finished Oct 15 11:25:39 AM UTC 24
Peak memory 229344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496228739 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable_auto_req_mode.496228739
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/12.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/12.edn_genbits.359979525
Short name T377
Test name
Test status
Simulation time 34235764 ps
CPU time 2.16 seconds
Started Oct 15 11:25:34 AM UTC 24
Finished Oct 15 11:25:37 AM UTC 24
Peak memory 231416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359979525 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.edn_genbits.359979525
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/12.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/12.edn_intr.2995589688
Short name T75
Test name
Test status
Simulation time 20497554 ps
CPU time 1.77 seconds
Started Oct 15 11:25:35 AM UTC 24
Finished Oct 15 11:25:38 AM UTC 24
Peak memory 238500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995589688 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 12.edn_intr.2995589688
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/12.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/12.edn_smoke.2967552055
Short name T376
Test name
Test status
Simulation time 15031709 ps
CPU time 1.39 seconds
Started Oct 15 11:25:33 AM UTC 24
Finished Oct 15 11:25:36 AM UTC 24
Peak memory 227816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967552055 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 12.edn_smoke.2967552055
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/12.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/12.edn_stress_all.1168242319
Short name T326
Test name
Test status
Simulation time 200349045 ps
CPU time 2.68 seconds
Started Oct 15 11:25:34 AM UTC 24
Finished Oct 15 11:25:37 AM UTC 24
Peak memory 228912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168242319 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.1168242319
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/12.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/12.edn_stress_all_with_rand_reset.722947862
Short name T241
Test name
Test status
Simulation time 7234282917 ps
CPU time 81.64 seconds
Started Oct 15 11:25:34 AM UTC 24
Finished Oct 15 11:26:57 AM UTC 24
Peak memory 229284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=722947862 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_
with_rand_reset.722947862
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/12.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/120.edn_genbits.651936303
Short name T736
Test name
Test status
Simulation time 35816149 ps
CPU time 1.24 seconds
Started Oct 15 11:27:58 AM UTC 24
Finished Oct 15 11:28:04 AM UTC 24
Peak memory 229900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651936303 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 120.edn_genbits.651936303
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/120.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/121.edn_alert.3986975417
Short name T737
Test name
Test status
Simulation time 29979069 ps
CPU time 1.33 seconds
Started Oct 15 11:27:58 AM UTC 24
Finished Oct 15 11:28:04 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986975417 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 121.edn_alert.3986975417
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/121.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/121.edn_genbits.2439977370
Short name T738
Test name
Test status
Simulation time 64587575 ps
CPU time 1.17 seconds
Started Oct 15 11:27:58 AM UTC 24
Finished Oct 15 11:28:07 AM UTC 24
Peak memory 231956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439977370 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 121.edn_genbits.2439977370
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/121.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/122.edn_genbits.644642863
Short name T739
Test name
Test status
Simulation time 23733987 ps
CPU time 1.22 seconds
Started Oct 15 11:27:58 AM UTC 24
Finished Oct 15 11:28:07 AM UTC 24
Peak memory 229900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644642863 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 122.edn_genbits.644642863
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/122.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/123.edn_alert.3397939923
Short name T741
Test name
Test status
Simulation time 26313344 ps
CPU time 1.32 seconds
Started Oct 15 11:27:58 AM UTC 24
Finished Oct 15 11:28:07 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397939923 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 123.edn_alert.3397939923
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/123.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/124.edn_alert.346682724
Short name T731
Test name
Test status
Simulation time 49741627 ps
CPU time 1.27 seconds
Started Oct 15 11:28:00 AM UTC 24
Finished Oct 15 11:28:03 AM UTC 24
Peak memory 230032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346682724 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 124.edn_alert.346682724
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/124.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/124.edn_genbits.1974303522
Short name T740
Test name
Test status
Simulation time 59011010 ps
CPU time 1.41 seconds
Started Oct 15 11:27:58 AM UTC 24
Finished Oct 15 11:28:07 AM UTC 24
Peak memory 230044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974303522 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 124.edn_genbits.1974303522
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/124.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/125.edn_genbits.1451580598
Short name T725
Test name
Test status
Simulation time 98245209 ps
CPU time 1.21 seconds
Started Oct 15 11:28:00 AM UTC 24
Finished Oct 15 11:28:02 AM UTC 24
Peak memory 230200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451580598 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 125.edn_genbits.1451580598
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/125.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/126.edn_alert.4274877276
Short name T728
Test name
Test status
Simulation time 39381826 ps
CPU time 1.23 seconds
Started Oct 15 11:28:00 AM UTC 24
Finished Oct 15 11:28:02 AM UTC 24
Peak memory 232076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274877276 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 126.edn_alert.4274877276
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/126.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/126.edn_genbits.2220954902
Short name T733
Test name
Test status
Simulation time 163000579 ps
CPU time 2.51 seconds
Started Oct 15 11:28:00 AM UTC 24
Finished Oct 15 11:28:03 AM UTC 24
Peak memory 233116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220954902 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 126.edn_genbits.2220954902
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/126.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/127.edn_alert.1039279812
Short name T727
Test name
Test status
Simulation time 96825887 ps
CPU time 1.13 seconds
Started Oct 15 11:28:00 AM UTC 24
Finished Oct 15 11:28:02 AM UTC 24
Peak memory 231720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039279812 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 127.edn_alert.1039279812
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/127.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/127.edn_genbits.3907572132
Short name T724
Test name
Test status
Simulation time 47580392 ps
CPU time 1.05 seconds
Started Oct 15 11:28:00 AM UTC 24
Finished Oct 15 11:28:02 AM UTC 24
Peak memory 229904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907572132 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 127.edn_genbits.3907572132
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/127.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/128.edn_alert.2029248053
Short name T732
Test name
Test status
Simulation time 42736351 ps
CPU time 1.15 seconds
Started Oct 15 11:28:01 AM UTC 24
Finished Oct 15 11:28:03 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029248053 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 128.edn_alert.2029248053
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/128.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/128.edn_genbits.14018738
Short name T726
Test name
Test status
Simulation time 340230194 ps
CPU time 1.03 seconds
Started Oct 15 11:28:00 AM UTC 24
Finished Oct 15 11:28:02 AM UTC 24
Peak memory 229908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14018738 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 128.edn_genbits.14018738
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/128.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/129.edn_alert.880627211
Short name T760
Test name
Test status
Simulation time 27973531 ps
CPU time 1.43 seconds
Started Oct 15 11:28:03 AM UTC 24
Finished Oct 15 11:28:13 AM UTC 24
Peak memory 227528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880627211 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 129.edn_alert.880627211
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/129.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/129.edn_genbits.2514183639
Short name T751
Test name
Test status
Simulation time 72103415 ps
CPU time 1.24 seconds
Started Oct 15 11:28:03 AM UTC 24
Finished Oct 15 11:28:11 AM UTC 24
Peak memory 227512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514183639 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 129.edn_genbits.2514183639
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/129.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/13.edn_alert.3016172402
Short name T76
Test name
Test status
Simulation time 97710438 ps
CPU time 1.24 seconds
Started Oct 15 11:25:37 AM UTC 24
Finished Oct 15 11:25:40 AM UTC 24
Peak memory 230032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016172402 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 13.edn_alert.3016172402
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/13.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/13.edn_alert_test.1613675271
Short name T382
Test name
Test status
Simulation time 16358174 ps
CPU time 1.29 seconds
Started Oct 15 11:25:38 AM UTC 24
Finished Oct 15 11:25:41 AM UTC 24
Peak memory 217920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613675271 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.1613675271
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/13.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/13.edn_disable.1773894079
Short name T381
Test name
Test status
Simulation time 11005341 ps
CPU time 1.32 seconds
Started Oct 15 11:25:38 AM UTC 24
Finished Oct 15 11:25:41 AM UTC 24
Peak memory 217736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773894079 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.1773894079
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/13.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/13.edn_disable_auto_req_mode.1129048391
Short name T314
Test name
Test status
Simulation time 83625549 ps
CPU time 1.64 seconds
Started Oct 15 11:25:38 AM UTC 24
Finished Oct 15 11:25:41 AM UTC 24
Peak memory 227848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129048391 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable_auto_req_mode.1129048391
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/13.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/13.edn_err.1509618326
Short name T384
Test name
Test status
Simulation time 24365481 ps
CPU time 1.55 seconds
Started Oct 15 11:25:38 AM UTC 24
Finished Oct 15 11:25:41 AM UTC 24
Peak memory 238444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509618326 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 13.edn_err.1509618326
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/13.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/13.edn_genbits.2417180689
Short name T106
Test name
Test status
Simulation time 85672934 ps
CPU time 1.78 seconds
Started Oct 15 11:25:36 AM UTC 24
Finished Oct 15 11:25:39 AM UTC 24
Peak memory 227844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417180689 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_genbits.2417180689
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/13.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/13.edn_intr.454351826
Short name T380
Test name
Test status
Simulation time 31953814 ps
CPU time 1.47 seconds
Started Oct 15 11:25:37 AM UTC 24
Finished Oct 15 11:25:40 AM UTC 24
Peak memory 238304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454351826 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 13.edn_intr.454351826
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/13.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/13.edn_smoke.933269828
Short name T379
Test name
Test status
Simulation time 15179428 ps
CPU time 1.44 seconds
Started Oct 15 11:25:36 AM UTC 24
Finished Oct 15 11:25:38 AM UTC 24
Peak memory 227860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933269828 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 13.edn_smoke.933269828
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/13.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/13.edn_stress_all.3035122068
Short name T130
Test name
Test status
Simulation time 208031219 ps
CPU time 6.52 seconds
Started Oct 15 11:25:36 AM UTC 24
Finished Oct 15 11:25:44 AM UTC 24
Peak memory 229040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035122068 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.3035122068
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/13.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/130.edn_alert.3847320581
Short name T750
Test name
Test status
Simulation time 39383618 ps
CPU time 1.05 seconds
Started Oct 15 11:28:03 AM UTC 24
Finished Oct 15 11:28:11 AM UTC 24
Peak memory 232076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847320581 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 130.edn_alert.3847320581
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/130.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/130.edn_genbits.1548968060
Short name T752
Test name
Test status
Simulation time 40551212 ps
CPU time 1.28 seconds
Started Oct 15 11:28:03 AM UTC 24
Finished Oct 15 11:28:12 AM UTC 24
Peak memory 230104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548968060 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 130.edn_genbits.1548968060
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/130.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/131.edn_alert.1859902427
Short name T758
Test name
Test status
Simulation time 48615753 ps
CPU time 1.21 seconds
Started Oct 15 11:28:03 AM UTC 24
Finished Oct 15 11:28:13 AM UTC 24
Peak memory 232012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859902427 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 131.edn_alert.1859902427
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/131.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/131.edn_genbits.2598924792
Short name T762
Test name
Test status
Simulation time 76525693 ps
CPU time 1.32 seconds
Started Oct 15 11:28:03 AM UTC 24
Finished Oct 15 11:28:13 AM UTC 24
Peak memory 227796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598924792 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 131.edn_genbits.2598924792
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/131.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/132.edn_alert.3640240699
Short name T768
Test name
Test status
Simulation time 82637238 ps
CPU time 1.59 seconds
Started Oct 15 11:28:03 AM UTC 24
Finished Oct 15 11:28:13 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640240699 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 132.edn_alert.3640240699
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/132.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/132.edn_genbits.2949928019
Short name T767
Test name
Test status
Simulation time 52431830 ps
CPU time 1.49 seconds
Started Oct 15 11:28:03 AM UTC 24
Finished Oct 15 11:28:13 AM UTC 24
Peak memory 229968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949928019 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 132.edn_genbits.2949928019
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/132.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/133.edn_genbits.3257331866
Short name T774
Test name
Test status
Simulation time 70632582 ps
CPU time 1.95 seconds
Started Oct 15 11:28:03 AM UTC 24
Finished Oct 15 11:28:13 AM UTC 24
Peak memory 230200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257331866 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 133.edn_genbits.3257331866
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/133.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/135.edn_alert.2050933358
Short name T743
Test name
Test status
Simulation time 74532629 ps
CPU time 1.11 seconds
Started Oct 15 11:28:04 AM UTC 24
Finished Oct 15 11:28:08 AM UTC 24
Peak memory 232076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050933358 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 135.edn_alert.2050933358
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/135.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/135.edn_genbits.3877627565
Short name T742
Test name
Test status
Simulation time 38501139 ps
CPU time 1.08 seconds
Started Oct 15 11:28:04 AM UTC 24
Finished Oct 15 11:28:08 AM UTC 24
Peak memory 229896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877627565 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 135.edn_genbits.3877627565
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/135.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/136.edn_alert.3767507220
Short name T746
Test name
Test status
Simulation time 42823388 ps
CPU time 1.45 seconds
Started Oct 15 11:28:05 AM UTC 24
Finished Oct 15 11:28:08 AM UTC 24
Peak memory 232076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767507220 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 136.edn_alert.3767507220
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/136.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/136.edn_genbits.8918161
Short name T747
Test name
Test status
Simulation time 95074468 ps
CPU time 1.42 seconds
Started Oct 15 11:28:04 AM UTC 24
Finished Oct 15 11:28:08 AM UTC 24
Peak memory 229916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8918161 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_
genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 136.edn_genbits.8918161
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/136.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/137.edn_genbits.1965917883
Short name T748
Test name
Test status
Simulation time 45575346 ps
CPU time 1.51 seconds
Started Oct 15 11:28:05 AM UTC 24
Finished Oct 15 11:28:08 AM UTC 24
Peak memory 230104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965917883 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 137.edn_genbits.1965917883
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/137.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/138.edn_alert.2224316819
Short name T745
Test name
Test status
Simulation time 133809830 ps
CPU time 1.16 seconds
Started Oct 15 11:28:05 AM UTC 24
Finished Oct 15 11:28:08 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224316819 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 138.edn_alert.2224316819
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/138.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/138.edn_genbits.3326022354
Short name T780
Test name
Test status
Simulation time 65059106 ps
CPU time 1.47 seconds
Started Oct 15 11:28:05 AM UTC 24
Finished Oct 15 11:28:15 AM UTC 24
Peak memory 229984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326022354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 138.edn_genbits.3326022354
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/138.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/139.edn_alert.3757937613
Short name T772
Test name
Test status
Simulation time 23325254 ps
CPU time 1.28 seconds
Started Oct 15 11:28:08 AM UTC 24
Finished Oct 15 11:28:13 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757937613 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 139.edn_alert.3757937613
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/139.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/14.edn_alert.648764431
Short name T131
Test name
Test status
Simulation time 25806310 ps
CPU time 1.74 seconds
Started Oct 15 11:25:40 AM UTC 24
Finished Oct 15 11:25:42 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648764431 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 14.edn_alert.648764431
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/14.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/14.edn_alert_test.2726921512
Short name T385
Test name
Test status
Simulation time 14103730 ps
CPU time 1.37 seconds
Started Oct 15 11:25:41 AM UTC 24
Finished Oct 15 11:25:43 AM UTC 24
Peak memory 228580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726921512 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.2726921512
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/14.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/14.edn_disable.3041058515
Short name T97
Test name
Test status
Simulation time 17138775 ps
CPU time 1.24 seconds
Started Oct 15 11:25:41 AM UTC 24
Finished Oct 15 11:25:43 AM UTC 24
Peak memory 217620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041058515 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.3041058515
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/14.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/14.edn_disable_auto_req_mode.3639798671
Short name T148
Test name
Test status
Simulation time 56461209 ps
CPU time 1.24 seconds
Started Oct 15 11:25:41 AM UTC 24
Finished Oct 15 11:25:43 AM UTC 24
Peak memory 227848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639798671 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable_auto_req_mode.3639798671
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/14.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/14.edn_err.3909986631
Short name T225
Test name
Test status
Simulation time 21362611 ps
CPU time 1.5 seconds
Started Oct 15 11:25:40 AM UTC 24
Finished Oct 15 11:25:42 AM UTC 24
Peak memory 229912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909986631 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 14.edn_err.3909986631
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/14.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/14.edn_genbits.3866893007
Short name T355
Test name
Test status
Simulation time 78620266 ps
CPU time 1.19 seconds
Started Oct 15 11:25:39 AM UTC 24
Finished Oct 15 11:25:41 AM UTC 24
Peak memory 231956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866893007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_genbits.3866893007
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/14.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/14.edn_intr.862228612
Short name T48
Test name
Test status
Simulation time 25413420 ps
CPU time 1.29 seconds
Started Oct 15 11:25:40 AM UTC 24
Finished Oct 15 11:25:42 AM UTC 24
Peak memory 230388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862228612 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 14.edn_intr.862228612
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/14.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/14.edn_smoke.1509571788
Short name T383
Test name
Test status
Simulation time 29172912 ps
CPU time 1.27 seconds
Started Oct 15 11:25:39 AM UTC 24
Finished Oct 15 11:25:41 AM UTC 24
Peak memory 227852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509571788 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 14.edn_smoke.1509571788
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/14.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/14.edn_stress_all.3759646080
Short name T299
Test name
Test status
Simulation time 338916527 ps
CPU time 5.86 seconds
Started Oct 15 11:25:39 AM UTC 24
Finished Oct 15 11:25:46 AM UTC 24
Peak memory 229316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759646080 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.3759646080
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/14.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/140.edn_alert.3198535082
Short name T770
Test name
Test status
Simulation time 43968710 ps
CPU time 1.28 seconds
Started Oct 15 11:28:08 AM UTC 24
Finished Oct 15 11:28:13 AM UTC 24
Peak memory 232076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198535082 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 140.edn_alert.3198535082
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/140.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/140.edn_genbits.81862449
Short name T775
Test name
Test status
Simulation time 45651252 ps
CPU time 1.43 seconds
Started Oct 15 11:28:08 AM UTC 24
Finished Oct 15 11:28:13 AM UTC 24
Peak memory 232192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81862449 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 140.edn_genbits.81862449
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/140.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/141.edn_alert.659402860
Short name T771
Test name
Test status
Simulation time 74592550 ps
CPU time 1.12 seconds
Started Oct 15 11:28:08 AM UTC 24
Finished Oct 15 11:28:13 AM UTC 24
Peak memory 232080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659402860 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 141.edn_alert.659402860
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/141.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/141.edn_genbits.1349970386
Short name T769
Test name
Test status
Simulation time 69591995 ps
CPU time 1.06 seconds
Started Oct 15 11:28:08 AM UTC 24
Finished Oct 15 11:28:13 AM UTC 24
Peak memory 229908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349970386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 141.edn_genbits.1349970386
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/141.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/142.edn_alert.2719574959
Short name T761
Test name
Test status
Simulation time 28427966 ps
CPU time 1.46 seconds
Started Oct 15 11:28:09 AM UTC 24
Finished Oct 15 11:28:13 AM UTC 24
Peak memory 230024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719574959 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 142.edn_alert.2719574959
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/142.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/142.edn_genbits.2258086034
Short name T776
Test name
Test status
Simulation time 167578626 ps
CPU time 1.25 seconds
Started Oct 15 11:28:08 AM UTC 24
Finished Oct 15 11:28:13 AM UTC 24
Peak memory 231948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258086034 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 142.edn_genbits.2258086034
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/142.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/143.edn_alert.1266513173
Short name T764
Test name
Test status
Simulation time 79904140 ps
CPU time 1.58 seconds
Started Oct 15 11:28:09 AM UTC 24
Finished Oct 15 11:28:13 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266513173 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 143.edn_alert.1266513173
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/143.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/143.edn_genbits.3006955427
Short name T763
Test name
Test status
Simulation time 52109798 ps
CPU time 1.5 seconds
Started Oct 15 11:28:09 AM UTC 24
Finished Oct 15 11:28:13 AM UTC 24
Peak memory 229984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006955427 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 143.edn_genbits.3006955427
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/143.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/144.edn_alert.3546642456
Short name T756
Test name
Test status
Simulation time 122137187 ps
CPU time 1.14 seconds
Started Oct 15 11:28:09 AM UTC 24
Finished Oct 15 11:28:12 AM UTC 24
Peak memory 232040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546642456 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 144.edn_alert.3546642456
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/144.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/144.edn_genbits.3920315784
Short name T755
Test name
Test status
Simulation time 30221147 ps
CPU time 1.12 seconds
Started Oct 15 11:28:09 AM UTC 24
Finished Oct 15 11:28:12 AM UTC 24
Peak memory 232248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920315784 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 144.edn_genbits.3920315784
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/144.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/145.edn_alert.3748166549
Short name T759
Test name
Test status
Simulation time 22720219 ps
CPU time 1.2 seconds
Started Oct 15 11:28:09 AM UTC 24
Finished Oct 15 11:28:13 AM UTC 24
Peak memory 232076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748166549 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 145.edn_alert.3748166549
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/145.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/145.edn_genbits.3529411945
Short name T352
Test name
Test status
Simulation time 87412424 ps
CPU time 1.57 seconds
Started Oct 15 11:28:09 AM UTC 24
Finished Oct 15 11:28:13 AM UTC 24
Peak memory 232152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529411945 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 145.edn_genbits.3529411945
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/145.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/146.edn_alert.369085718
Short name T757
Test name
Test status
Simulation time 147549984 ps
CPU time 1.13 seconds
Started Oct 15 11:28:09 AM UTC 24
Finished Oct 15 11:28:12 AM UTC 24
Peak memory 232076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369085718 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 146.edn_alert.369085718
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/146.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/146.edn_genbits.3889814439
Short name T754
Test name
Test status
Simulation time 48060468 ps
CPU time 1.03 seconds
Started Oct 15 11:28:09 AM UTC 24
Finished Oct 15 11:28:12 AM UTC 24
Peak memory 229908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889814439 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 146.edn_genbits.3889814439
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/146.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/147.edn_alert.2692667639
Short name T777
Test name
Test status
Simulation time 22037101 ps
CPU time 1.13 seconds
Started Oct 15 11:28:12 AM UTC 24
Finished Oct 15 11:28:15 AM UTC 24
Peak memory 227980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692667639 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 147.edn_alert.2692667639
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/147.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/147.edn_genbits.4093113847
Short name T766
Test name
Test status
Simulation time 39496346 ps
CPU time 1.32 seconds
Started Oct 15 11:28:10 AM UTC 24
Finished Oct 15 11:28:13 AM UTC 24
Peak memory 232016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093113847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 147.edn_genbits.4093113847
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/147.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/148.edn_alert.3070297343
Short name T778
Test name
Test status
Simulation time 27338689 ps
CPU time 1.29 seconds
Started Oct 15 11:28:12 AM UTC 24
Finished Oct 15 11:28:15 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070297343 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 148.edn_alert.3070297343
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/148.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/148.edn_genbits.1301264447
Short name T779
Test name
Test status
Simulation time 65833803 ps
CPU time 1.5 seconds
Started Oct 15 11:28:12 AM UTC 24
Finished Oct 15 11:28:15 AM UTC 24
Peak memory 229984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301264447 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 148.edn_genbits.1301264447
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/148.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/149.edn_alert.1688233953
Short name T782
Test name
Test status
Simulation time 26481738 ps
CPU time 1.19 seconds
Started Oct 15 11:28:14 AM UTC 24
Finished Oct 15 11:28:17 AM UTC 24
Peak memory 232076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688233953 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 149.edn_alert.1688233953
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/149.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/149.edn_genbits.1148593629
Short name T781
Test name
Test status
Simulation time 110163760 ps
CPU time 1.04 seconds
Started Oct 15 11:28:14 AM UTC 24
Finished Oct 15 11:28:17 AM UTC 24
Peak memory 229900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148593629 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 149.edn_genbits.1148593629
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/149.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/15.edn_alert.2608805325
Short name T182
Test name
Test status
Simulation time 69546223 ps
CPU time 1.62 seconds
Started Oct 15 11:25:42 AM UTC 24
Finished Oct 15 11:25:45 AM UTC 24
Peak memory 232080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608805325 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 15.edn_alert.2608805325
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/15.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/15.edn_alert_test.2585906204
Short name T389
Test name
Test status
Simulation time 25878770 ps
CPU time 1.22 seconds
Started Oct 15 11:25:44 AM UTC 24
Finished Oct 15 11:25:46 AM UTC 24
Peak memory 217920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585906204 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.2585906204
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/15.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/15.edn_disable.4167894776
Short name T98
Test name
Test status
Simulation time 11781284 ps
CPU time 1.37 seconds
Started Oct 15 11:25:43 AM UTC 24
Finished Oct 15 11:25:46 AM UTC 24
Peak memory 227976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167894776 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.4167894776
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/15.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/15.edn_err.998134451
Short name T388
Test name
Test status
Simulation time 23838668 ps
CPU time 1.58 seconds
Started Oct 15 11:25:42 AM UTC 24
Finished Oct 15 11:25:45 AM UTC 24
Peak memory 238424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998134451 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 15.edn_err.998134451
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/15.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/15.edn_intr.2141992982
Short name T387
Test name
Test status
Simulation time 32860100 ps
CPU time 1.38 seconds
Started Oct 15 11:25:42 AM UTC 24
Finished Oct 15 11:25:45 AM UTC 24
Peak memory 227928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141992982 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 15.edn_intr.2141992982
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/15.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/15.edn_smoke.2819213035
Short name T386
Test name
Test status
Simulation time 18048793 ps
CPU time 1.5 seconds
Started Oct 15 11:25:41 AM UTC 24
Finished Oct 15 11:25:44 AM UTC 24
Peak memory 227864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819213035 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 15.edn_smoke.2819213035
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/15.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/15.edn_stress_all.2046880843
Short name T121
Test name
Test status
Simulation time 61267351 ps
CPU time 2.53 seconds
Started Oct 15 11:25:42 AM UTC 24
Finished Oct 15 11:25:46 AM UTC 24
Peak memory 229036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046880843 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.2046880843
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/15.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/150.edn_alert.2971108390
Short name T784
Test name
Test status
Simulation time 27725578 ps
CPU time 1.3 seconds
Started Oct 15 11:28:14 AM UTC 24
Finished Oct 15 11:28:17 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971108390 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 150.edn_alert.2971108390
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/150.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/150.edn_genbits.4026350036
Short name T787
Test name
Test status
Simulation time 53361329 ps
CPU time 1.67 seconds
Started Oct 15 11:28:14 AM UTC 24
Finished Oct 15 11:28:17 AM UTC 24
Peak memory 230104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026350036 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 150.edn_genbits.4026350036
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/150.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/151.edn_alert.575766521
Short name T783
Test name
Test status
Simulation time 25299236 ps
CPU time 1.14 seconds
Started Oct 15 11:28:14 AM UTC 24
Finished Oct 15 11:28:17 AM UTC 24
Peak memory 229936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575766521 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 151.edn_alert.575766521
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/151.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/151.edn_genbits.1366217828
Short name T786
Test name
Test status
Simulation time 30590021 ps
CPU time 1.31 seconds
Started Oct 15 11:28:14 AM UTC 24
Finished Oct 15 11:28:17 AM UTC 24
Peak memory 229984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366217828 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 151.edn_genbits.1366217828
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/151.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/152.edn_alert.3523966464
Short name T785
Test name
Test status
Simulation time 28662877 ps
CPU time 1.22 seconds
Started Oct 15 11:28:14 AM UTC 24
Finished Oct 15 11:28:17 AM UTC 24
Peak memory 227876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523966464 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 152.edn_alert.3523966464
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/152.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/152.edn_genbits.1268944324
Short name T788
Test name
Test status
Simulation time 76077175 ps
CPU time 2.44 seconds
Started Oct 15 11:28:14 AM UTC 24
Finished Oct 15 11:28:18 AM UTC 24
Peak memory 233404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268944324 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 152.edn_genbits.1268944324
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/152.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/153.edn_genbits.3582155899
Short name T799
Test name
Test status
Simulation time 123103845 ps
CPU time 1.16 seconds
Started Oct 15 11:28:14 AM UTC 24
Finished Oct 15 11:28:24 AM UTC 24
Peak memory 231956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582155899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 153.edn_genbits.3582155899
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/153.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/154.edn_alert.1000606629
Short name T803
Test name
Test status
Simulation time 126905677 ps
CPU time 1.29 seconds
Started Oct 15 11:28:14 AM UTC 24
Finished Oct 15 11:28:27 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000606629 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 154.edn_alert.1000606629
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/154.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/154.edn_genbits.450958125
Short name T798
Test name
Test status
Simulation time 88787625 ps
CPU time 1.02 seconds
Started Oct 15 11:28:14 AM UTC 24
Finished Oct 15 11:28:24 AM UTC 24
Peak memory 229968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450958125 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 154.edn_genbits.450958125
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/154.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/155.edn_alert.2629338963
Short name T801
Test name
Test status
Simulation time 46119421 ps
CPU time 1.12 seconds
Started Oct 15 11:28:14 AM UTC 24
Finished Oct 15 11:28:27 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629338963 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 155.edn_alert.2629338963
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/155.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/156.edn_alert.874780963
Short name T802
Test name
Test status
Simulation time 24797801 ps
CPU time 1.07 seconds
Started Oct 15 11:28:14 AM UTC 24
Finished Oct 15 11:28:27 AM UTC 24
Peak memory 230032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874780963 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 156.edn_alert.874780963
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/156.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/156.edn_genbits.2529641648
Short name T805
Test name
Test status
Simulation time 38944688 ps
CPU time 1.28 seconds
Started Oct 15 11:28:14 AM UTC 24
Finished Oct 15 11:28:27 AM UTC 24
Peak memory 227192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529641648 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 156.edn_genbits.2529641648
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/156.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/157.edn_alert.2646974534
Short name T806
Test name
Test status
Simulation time 71285293 ps
CPU time 1.13 seconds
Started Oct 15 11:28:14 AM UTC 24
Finished Oct 15 11:28:27 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646974534 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 157.edn_alert.2646974534
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/157.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/157.edn_genbits.3875647765
Short name T804
Test name
Test status
Simulation time 32504123 ps
CPU time 1.19 seconds
Started Oct 15 11:28:14 AM UTC 24
Finished Oct 15 11:28:27 AM UTC 24
Peak memory 230140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875647765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 157.edn_genbits.3875647765
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/157.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/158.edn_alert.2196329308
Short name T807
Test name
Test status
Simulation time 69678333 ps
CPU time 1.09 seconds
Started Oct 15 11:28:14 AM UTC 24
Finished Oct 15 11:28:28 AM UTC 24
Peak memory 232076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196329308 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 158.edn_alert.2196329308
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/158.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/158.edn_genbits.3456436535
Short name T810
Test name
Test status
Simulation time 40635634 ps
CPU time 1.58 seconds
Started Oct 15 11:28:14 AM UTC 24
Finished Oct 15 11:28:28 AM UTC 24
Peak memory 230044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456436535 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 158.edn_genbits.3456436535
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/158.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/159.edn_alert.40712487
Short name T808
Test name
Test status
Simulation time 26942129 ps
CPU time 1.15 seconds
Started Oct 15 11:28:14 AM UTC 24
Finished Oct 15 11:28:28 AM UTC 24
Peak memory 232080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40712487 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a
lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 159.edn_alert.40712487
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/159.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/159.edn_genbits.2982157647
Short name T329
Test name
Test status
Simulation time 97819972 ps
CPU time 1.38 seconds
Started Oct 15 11:28:14 AM UTC 24
Finished Oct 15 11:28:28 AM UTC 24
Peak memory 229968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982157647 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 159.edn_genbits.2982157647
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/159.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/16.edn_alert_test.1862849468
Short name T392
Test name
Test status
Simulation time 15744147 ps
CPU time 1.24 seconds
Started Oct 15 11:25:46 AM UTC 24
Finished Oct 15 11:25:48 AM UTC 24
Peak memory 228612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862849468 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.1862849468
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/16.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/16.edn_disable_auto_req_mode.2479967761
Short name T393
Test name
Test status
Simulation time 49762789 ps
CPU time 1.56 seconds
Started Oct 15 11:25:46 AM UTC 24
Finished Oct 15 11:25:49 AM UTC 24
Peak memory 227856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479967761 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable_auto_req_mode.2479967761
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/16.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/16.edn_smoke.103832547
Short name T390
Test name
Test status
Simulation time 39003715 ps
CPU time 1.37 seconds
Started Oct 15 11:25:45 AM UTC 24
Finished Oct 15 11:25:47 AM UTC 24
Peak memory 227848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103832547 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 16.edn_smoke.103832547
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/16.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/16.edn_stress_all.673328994
Short name T391
Test name
Test status
Simulation time 313763355 ps
CPU time 2.55 seconds
Started Oct 15 11:25:45 AM UTC 24
Finished Oct 15 11:25:48 AM UTC 24
Peak memory 231080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673328994 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.673328994
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/16.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/160.edn_alert.2248510744
Short name T828
Test name
Test status
Simulation time 46293954 ps
CPU time 1.07 seconds
Started Oct 15 11:28:15 AM UTC 24
Finished Oct 15 11:28:38 AM UTC 24
Peak memory 232076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248510744 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 160.edn_alert.2248510744
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/160.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/161.edn_alert.1083597759
Short name T818
Test name
Test status
Simulation time 51951037 ps
CPU time 1.18 seconds
Started Oct 15 11:28:15 AM UTC 24
Finished Oct 15 11:28:32 AM UTC 24
Peak memory 227980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083597759 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 161.edn_alert.1083597759
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/161.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/161.edn_genbits.549588831
Short name T815
Test name
Test status
Simulation time 91169639 ps
CPU time 1.09 seconds
Started Oct 15 11:28:15 AM UTC 24
Finished Oct 15 11:28:32 AM UTC 24
Peak memory 230104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549588831 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 161.edn_genbits.549588831
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/161.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/162.edn_alert.1279934168
Short name T830
Test name
Test status
Simulation time 63192227 ps
CPU time 0.99 seconds
Started Oct 15 11:28:16 AM UTC 24
Finished Oct 15 11:28:38 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279934168 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 162.edn_alert.1279934168
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/162.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/162.edn_genbits.523197352
Short name T814
Test name
Test status
Simulation time 115313697 ps
CPU time 1.05 seconds
Started Oct 15 11:28:16 AM UTC 24
Finished Oct 15 11:28:32 AM UTC 24
Peak memory 229908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523197352 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 162.edn_genbits.523197352
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/162.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/163.edn_alert.433232393
Short name T789
Test name
Test status
Simulation time 41402077 ps
CPU time 0.99 seconds
Started Oct 15 11:28:17 AM UTC 24
Finished Oct 15 11:28:22 AM UTC 24
Peak memory 230032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433232393 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 163.edn_alert.433232393
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/163.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/163.edn_genbits.3820972091
Short name T834
Test name
Test status
Simulation time 59092261 ps
CPU time 0.98 seconds
Started Oct 15 11:28:16 AM UTC 24
Finished Oct 15 11:28:38 AM UTC 24
Peak memory 229908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820972091 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 163.edn_genbits.3820972091
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/163.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/164.edn_alert.2763483188
Short name T205
Test name
Test status
Simulation time 86476177 ps
CPU time 1.09 seconds
Started Oct 15 11:28:18 AM UTC 24
Finished Oct 15 11:28:23 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763483188 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 164.edn_alert.2763483188
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/164.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/165.edn_alert.3926475980
Short name T791
Test name
Test status
Simulation time 41056366 ps
CPU time 1 seconds
Started Oct 15 11:28:18 AM UTC 24
Finished Oct 15 11:28:23 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926475980 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 165.edn_alert.3926475980
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/165.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/165.edn_genbits.688937896
Short name T795
Test name
Test status
Simulation time 51398800 ps
CPU time 1.11 seconds
Started Oct 15 11:28:18 AM UTC 24
Finished Oct 15 11:28:23 AM UTC 24
Peak memory 229908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688937896 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 165.edn_genbits.688937896
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/165.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/166.edn_alert.2145891060
Short name T792
Test name
Test status
Simulation time 27687557 ps
CPU time 1.02 seconds
Started Oct 15 11:28:18 AM UTC 24
Finished Oct 15 11:28:23 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145891060 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 166.edn_alert.2145891060
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/166.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/166.edn_genbits.3748301568
Short name T797
Test name
Test status
Simulation time 39719383 ps
CPU time 1.67 seconds
Started Oct 15 11:28:18 AM UTC 24
Finished Oct 15 11:28:24 AM UTC 24
Peak memory 230044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748301568 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 166.edn_genbits.3748301568
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/166.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/167.edn_alert.1408963461
Short name T796
Test name
Test status
Simulation time 41400685 ps
CPU time 1.03 seconds
Started Oct 15 11:28:18 AM UTC 24
Finished Oct 15 11:28:23 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408963461 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 167.edn_alert.1408963461
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/167.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/167.edn_genbits.2757107962
Short name T793
Test name
Test status
Simulation time 221034082 ps
CPU time 1 seconds
Started Oct 15 11:28:18 AM UTC 24
Finished Oct 15 11:28:23 AM UTC 24
Peak memory 231956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757107962 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 167.edn_genbits.2757107962
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/167.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/168.edn_alert.591564394
Short name T790
Test name
Test status
Simulation time 26832844 ps
CPU time 1.07 seconds
Started Oct 15 11:28:19 AM UTC 24
Finished Oct 15 11:28:22 AM UTC 24
Peak memory 230032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591564394 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 168.edn_alert.591564394
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/168.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/168.edn_genbits.4216716081
Short name T794
Test name
Test status
Simulation time 176845949 ps
CPU time 1.05 seconds
Started Oct 15 11:28:18 AM UTC 24
Finished Oct 15 11:28:23 AM UTC 24
Peak memory 227844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216716081 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 168.edn_genbits.4216716081
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/168.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/169.edn_alert.2061604073
Short name T859
Test name
Test status
Simulation time 30283413 ps
CPU time 1.49 seconds
Started Oct 15 11:28:23 AM UTC 24
Finished Oct 15 11:28:43 AM UTC 24
Peak memory 231472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061604073 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 169.edn_alert.2061604073
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/169.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/169.edn_genbits.3041033390
Short name T864
Test name
Test status
Simulation time 27535682 ps
CPU time 1.6 seconds
Started Oct 15 11:28:23 AM UTC 24
Finished Oct 15 11:28:43 AM UTC 24
Peak memory 230044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041033390 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 169.edn_genbits.3041033390
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/169.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/17.edn_alert.2399596954
Short name T159
Test name
Test status
Simulation time 38183914 ps
CPU time 1.69 seconds
Started Oct 15 11:25:48 AM UTC 24
Finished Oct 15 11:25:50 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399596954 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 17.edn_alert.2399596954
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/17.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/17.edn_alert_test.3481546188
Short name T395
Test name
Test status
Simulation time 32047698 ps
CPU time 0.99 seconds
Started Oct 15 11:25:50 AM UTC 24
Finished Oct 15 11:25:52 AM UTC 24
Peak memory 217920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481546188 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.3481546188
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/17.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/17.edn_disable.3117317602
Short name T231
Test name
Test status
Simulation time 90074314 ps
CPU time 1.1 seconds
Started Oct 15 11:25:49 AM UTC 24
Finished Oct 15 11:25:51 AM UTC 24
Peak memory 228036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117317602 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.3117317602
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/17.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/17.edn_err.2483716142
Short name T120
Test name
Test status
Simulation time 19770356 ps
CPU time 1.18 seconds
Started Oct 15 11:25:49 AM UTC 24
Finished Oct 15 11:25:51 AM UTC 24
Peak memory 229912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483716142 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 17.edn_err.2483716142
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/17.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/17.edn_genbits.1771562517
Short name T78
Test name
Test status
Simulation time 280230987 ps
CPU time 2.19 seconds
Started Oct 15 11:25:47 AM UTC 24
Finished Oct 15 11:25:50 AM UTC 24
Peak memory 233144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771562517 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_genbits.1771562517
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/17.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/17.edn_smoke.2945801034
Short name T394
Test name
Test status
Simulation time 15412914 ps
CPU time 1.42 seconds
Started Oct 15 11:25:46 AM UTC 24
Finished Oct 15 11:25:49 AM UTC 24
Peak memory 227852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945801034 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 17.edn_smoke.2945801034
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/17.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/17.edn_stress_all.3635824190
Short name T300
Test name
Test status
Simulation time 87657139 ps
CPU time 2.49 seconds
Started Oct 15 11:25:47 AM UTC 24
Finished Oct 15 11:25:51 AM UTC 24
Peak memory 229060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635824190 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.3635824190
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/17.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/170.edn_alert.3110026272
Short name T809
Test name
Test status
Simulation time 33364120 ps
CPU time 1.17 seconds
Started Oct 15 11:28:24 AM UTC 24
Finished Oct 15 11:28:28 AM UTC 24
Peak memory 232076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110026272 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 170.edn_alert.3110026272
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/170.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/170.edn_genbits.2888038387
Short name T851
Test name
Test status
Simulation time 61898232 ps
CPU time 0.9 seconds
Started Oct 15 11:28:23 AM UTC 24
Finished Oct 15 11:28:42 AM UTC 24
Peak memory 229228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888038387 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 170.edn_genbits.2888038387
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/170.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/171.edn_alert.1615209723
Short name T829
Test name
Test status
Simulation time 38014074 ps
CPU time 1.11 seconds
Started Oct 15 11:28:24 AM UTC 24
Finished Oct 15 11:28:38 AM UTC 24
Peak memory 232076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615209723 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 171.edn_alert.1615209723
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/171.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/171.edn_genbits.932382647
Short name T811
Test name
Test status
Simulation time 44921135 ps
CPU time 1.73 seconds
Started Oct 15 11:28:24 AM UTC 24
Finished Oct 15 11:28:28 AM UTC 24
Peak memory 230104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932382647 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 171.edn_genbits.932382647
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/171.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/172.edn_alert.2810586627
Short name T833
Test name
Test status
Simulation time 345257422 ps
CPU time 1.25 seconds
Started Oct 15 11:28:24 AM UTC 24
Finished Oct 15 11:28:38 AM UTC 24
Peak memory 230008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810586627 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 172.edn_alert.2810586627
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/172.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/172.edn_genbits.3555949171
Short name T832
Test name
Test status
Simulation time 33022651 ps
CPU time 1.25 seconds
Started Oct 15 11:28:24 AM UTC 24
Finished Oct 15 11:28:38 AM UTC 24
Peak memory 227828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555949171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 172.edn_genbits.3555949171
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/172.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/173.edn_alert.78968199
Short name T273
Test name
Test status
Simulation time 31921853 ps
CPU time 1.16 seconds
Started Oct 15 11:28:24 AM UTC 24
Finished Oct 15 11:28:38 AM UTC 24
Peak memory 230032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78968199 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a
lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 173.edn_alert.78968199
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/173.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/173.edn_genbits.3101543525
Short name T831
Test name
Test status
Simulation time 81353940 ps
CPU time 1.21 seconds
Started Oct 15 11:28:24 AM UTC 24
Finished Oct 15 11:28:38 AM UTC 24
Peak memory 229900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101543525 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 173.edn_genbits.3101543525
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/173.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/174.edn_alert.2753575218
Short name T835
Test name
Test status
Simulation time 112077146 ps
CPU time 1.02 seconds
Started Oct 15 11:28:26 AM UTC 24
Finished Oct 15 11:28:38 AM UTC 24
Peak memory 232076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753575218 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 174.edn_alert.2753575218
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/174.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/174.edn_genbits.3287884091
Short name T836
Test name
Test status
Simulation time 41905424 ps
CPU time 1.49 seconds
Started Oct 15 11:28:24 AM UTC 24
Finished Oct 15 11:28:38 AM UTC 24
Peak memory 230044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287884091 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 174.edn_genbits.3287884091
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/174.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/175.edn_alert.1453039681
Short name T813
Test name
Test status
Simulation time 41788324 ps
CPU time 1.13 seconds
Started Oct 15 11:28:27 AM UTC 24
Finished Oct 15 11:28:32 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453039681 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 175.edn_alert.1453039681
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/175.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/175.edn_genbits.1856729527
Short name T837
Test name
Test status
Simulation time 37202077 ps
CPU time 1.54 seconds
Started Oct 15 11:28:26 AM UTC 24
Finished Oct 15 11:28:38 AM UTC 24
Peak memory 231944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856729527 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 175.edn_genbits.1856729527
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/175.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/176.edn_alert.4284018770
Short name T826
Test name
Test status
Simulation time 295411827 ps
CPU time 1.1 seconds
Started Oct 15 11:28:28 AM UTC 24
Finished Oct 15 11:28:37 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284018770 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 176.edn_alert.4284018770
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/176.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/176.edn_genbits.3414291751
Short name T825
Test name
Test status
Simulation time 64585448 ps
CPU time 1.04 seconds
Started Oct 15 11:28:28 AM UTC 24
Finished Oct 15 11:28:37 AM UTC 24
Peak memory 227844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414291751 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 176.edn_genbits.3414291751
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/176.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/177.edn_alert.992675530
Short name T817
Test name
Test status
Simulation time 80519464 ps
CPU time 1.15 seconds
Started Oct 15 11:28:29 AM UTC 24
Finished Oct 15 11:28:32 AM UTC 24
Peak memory 232076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992675530 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 177.edn_alert.992675530
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/177.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/177.edn_genbits.3989205094
Short name T827
Test name
Test status
Simulation time 32689422 ps
CPU time 1.13 seconds
Started Oct 15 11:28:28 AM UTC 24
Finished Oct 15 11:28:37 AM UTC 24
Peak memory 230044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989205094 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 177.edn_genbits.3989205094
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/177.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/178.edn_alert.4168255967
Short name T819
Test name
Test status
Simulation time 68440486 ps
CPU time 1.24 seconds
Started Oct 15 11:28:29 AM UTC 24
Finished Oct 15 11:28:32 AM UTC 24
Peak memory 232076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168255967 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 178.edn_alert.4168255967
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/178.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/178.edn_genbits.2272939327
Short name T824
Test name
Test status
Simulation time 126357294 ps
CPU time 1.78 seconds
Started Oct 15 11:28:29 AM UTC 24
Finished Oct 15 11:28:33 AM UTC 24
Peak memory 229900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272939327 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 178.edn_genbits.2272939327
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/178.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/179.edn_alert.3485076625
Short name T816
Test name
Test status
Simulation time 49169495 ps
CPU time 1.09 seconds
Started Oct 15 11:28:29 AM UTC 24
Finished Oct 15 11:28:32 AM UTC 24
Peak memory 227980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485076625 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 179.edn_alert.3485076625
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/179.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/179.edn_genbits.580516162
Short name T821
Test name
Test status
Simulation time 51336704 ps
CPU time 1.23 seconds
Started Oct 15 11:28:29 AM UTC 24
Finished Oct 15 11:28:32 AM UTC 24
Peak memory 229968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580516162 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 179.edn_genbits.580516162
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/179.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/18.edn_alert_test.2386224078
Short name T398
Test name
Test status
Simulation time 18262928 ps
CPU time 1.2 seconds
Started Oct 15 11:25:51 AM UTC 24
Finished Oct 15 11:25:53 AM UTC 24
Peak memory 217852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386224078 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.2386224078
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/18.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/18.edn_disable.3488823332
Short name T119
Test name
Test status
Simulation time 21961073 ps
CPU time 1.36 seconds
Started Oct 15 11:25:51 AM UTC 24
Finished Oct 15 11:25:54 AM UTC 24
Peak memory 227920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488823332 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.3488823332
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/18.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/18.edn_disable_auto_req_mode.1242786030
Short name T399
Test name
Test status
Simulation time 30807717 ps
CPU time 1.41 seconds
Started Oct 15 11:25:51 AM UTC 24
Finished Oct 15 11:25:54 AM UTC 24
Peak memory 229908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242786030 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable_auto_req_mode.1242786030
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/18.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/18.edn_err.866398861
Short name T218
Test name
Test status
Simulation time 75583164 ps
CPU time 1.43 seconds
Started Oct 15 11:25:51 AM UTC 24
Finished Oct 15 11:25:54 AM UTC 24
Peak memory 231956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866398861 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 18.edn_err.866398861
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/18.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/18.edn_genbits.199912260
Short name T118
Test name
Test status
Simulation time 119192040 ps
CPU time 1.69 seconds
Started Oct 15 11:25:50 AM UTC 24
Finished Oct 15 11:25:53 AM UTC 24
Peak memory 229892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199912260 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 18.edn_genbits.199912260
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/18.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/18.edn_intr.482154026
Short name T53
Test name
Test status
Simulation time 38525976 ps
CPU time 1.27 seconds
Started Oct 15 11:25:50 AM UTC 24
Finished Oct 15 11:25:53 AM UTC 24
Peak memory 229968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482154026 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 18.edn_intr.482154026
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/18.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/18.edn_smoke.3223912588
Short name T396
Test name
Test status
Simulation time 25085766 ps
CPU time 1.26 seconds
Started Oct 15 11:25:50 AM UTC 24
Finished Oct 15 11:25:53 AM UTC 24
Peak memory 227852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223912588 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 18.edn_smoke.3223912588
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/18.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/18.edn_stress_all.2376043488
Short name T353
Test name
Test status
Simulation time 922478940 ps
CPU time 4.52 seconds
Started Oct 15 11:25:50 AM UTC 24
Finished Oct 15 11:25:56 AM UTC 24
Peak memory 231064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376043488 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.2376043488
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/18.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/18.edn_stress_all_with_rand_reset.3759138
Short name T605
Test name
Test status
Simulation time 29185021238 ps
CPU time 95.65 seconds
Started Oct 15 11:25:50 AM UTC 24
Finished Oct 15 11:27:28 AM UTC 24
Peak memory 231536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3759138 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_wi
th_rand_reset.3759138
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/18.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/180.edn_alert.3497706752
Short name T173
Test name
Test status
Simulation time 60180938 ps
CPU time 1.03 seconds
Started Oct 15 11:28:29 AM UTC 24
Finished Oct 15 11:28:32 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497706752 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 180.edn_alert.3497706752
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/180.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/181.edn_alert.3433609310
Short name T820
Test name
Test status
Simulation time 61744332 ps
CPU time 1.07 seconds
Started Oct 15 11:28:29 AM UTC 24
Finished Oct 15 11:28:32 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433609310 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 181.edn_alert.3433609310
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/181.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/181.edn_genbits.2101001867
Short name T823
Test name
Test status
Simulation time 39718606 ps
CPU time 1.38 seconds
Started Oct 15 11:28:29 AM UTC 24
Finished Oct 15 11:28:32 AM UTC 24
Peak memory 230100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101001867 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 181.edn_genbits.2101001867
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/181.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/182.edn_alert.1435063233
Short name T868
Test name
Test status
Simulation time 92515249 ps
CPU time 1.14 seconds
Started Oct 15 11:28:31 AM UTC 24
Finished Oct 15 11:28:43 AM UTC 24
Peak memory 227980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435063233 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 182.edn_alert.1435063233
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/182.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/182.edn_genbits.1578636378
Short name T822
Test name
Test status
Simulation time 42065573 ps
CPU time 1.13 seconds
Started Oct 15 11:28:29 AM UTC 24
Finished Oct 15 11:28:32 AM UTC 24
Peak memory 229968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578636378 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 182.edn_genbits.1578636378
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/182.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/183.edn_alert.3439241818
Short name T841
Test name
Test status
Simulation time 130291776 ps
CPU time 1.17 seconds
Started Oct 15 11:28:33 AM UTC 24
Finished Oct 15 11:28:42 AM UTC 24
Peak memory 232076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439241818 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 183.edn_alert.3439241818
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/183.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/183.edn_genbits.1883957214
Short name T842
Test name
Test status
Simulation time 52960850 ps
CPU time 1.31 seconds
Started Oct 15 11:28:33 AM UTC 24
Finished Oct 15 11:28:42 AM UTC 24
Peak memory 230044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883957214 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 183.edn_genbits.1883957214
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/183.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/184.edn_alert.1586395048
Short name T840
Test name
Test status
Simulation time 62210660 ps
CPU time 1.11 seconds
Started Oct 15 11:28:33 AM UTC 24
Finished Oct 15 11:28:42 AM UTC 24
Peak memory 227980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586395048 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 184.edn_alert.1586395048
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/184.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/184.edn_genbits.4259886430
Short name T839
Test name
Test status
Simulation time 39442648 ps
CPU time 1.05 seconds
Started Oct 15 11:28:33 AM UTC 24
Finished Oct 15 11:28:41 AM UTC 24
Peak memory 230044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259886430 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 184.edn_genbits.4259886430
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/184.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/185.edn_alert.768569548
Short name T845
Test name
Test status
Simulation time 27852725 ps
CPU time 1.2 seconds
Started Oct 15 11:28:33 AM UTC 24
Finished Oct 15 11:28:42 AM UTC 24
Peak memory 232048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768569548 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 185.edn_alert.768569548
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/185.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/185.edn_genbits.4045877614
Short name T862
Test name
Test status
Simulation time 64614980 ps
CPU time 2.34 seconds
Started Oct 15 11:28:33 AM UTC 24
Finished Oct 15 11:28:43 AM UTC 24
Peak memory 233468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045877614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 185.edn_genbits.4045877614
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/185.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/186.edn_alert.2775322472
Short name T843
Test name
Test status
Simulation time 47506802 ps
CPU time 1.1 seconds
Started Oct 15 11:28:33 AM UTC 24
Finished Oct 15 11:28:42 AM UTC 24
Peak memory 232076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775322472 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 186.edn_alert.2775322472
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/186.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/186.edn_genbits.97861094
Short name T331
Test name
Test status
Simulation time 48297741 ps
CPU time 1.19 seconds
Started Oct 15 11:28:33 AM UTC 24
Finished Oct 15 11:28:42 AM UTC 24
Peak memory 232164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97861094 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 186.edn_genbits.97861094
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/186.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/187.edn_alert.2941550361
Short name T857
Test name
Test status
Simulation time 68894267 ps
CPU time 1.1 seconds
Started Oct 15 11:28:33 AM UTC 24
Finished Oct 15 11:28:43 AM UTC 24
Peak memory 232076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941550361 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 187.edn_alert.2941550361
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/187.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/187.edn_genbits.2495043076
Short name T847
Test name
Test status
Simulation time 108744472 ps
CPU time 1.25 seconds
Started Oct 15 11:28:33 AM UTC 24
Finished Oct 15 11:28:42 AM UTC 24
Peak memory 232152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495043076 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 187.edn_genbits.2495043076
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/187.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/188.edn_alert.1945936653
Short name T858
Test name
Test status
Simulation time 42410627 ps
CPU time 1.04 seconds
Started Oct 15 11:28:33 AM UTC 24
Finished Oct 15 11:28:43 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945936653 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 188.edn_alert.1945936653
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/188.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/188.edn_genbits.1501836347
Short name T849
Test name
Test status
Simulation time 93728879 ps
CPU time 1.39 seconds
Started Oct 15 11:28:33 AM UTC 24
Finished Oct 15 11:28:42 AM UTC 24
Peak memory 229904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501836347 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 188.edn_genbits.1501836347
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/188.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/189.edn_alert.3778699945
Short name T863
Test name
Test status
Simulation time 37134570 ps
CPU time 1.22 seconds
Started Oct 15 11:28:33 AM UTC 24
Finished Oct 15 11:28:43 AM UTC 24
Peak memory 232076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778699945 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 189.edn_alert.3778699945
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/189.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/189.edn_genbits.252062298
Short name T871
Test name
Test status
Simulation time 259668186 ps
CPU time 3.3 seconds
Started Oct 15 11:28:33 AM UTC 24
Finished Oct 15 11:28:44 AM UTC 24
Peak memory 231100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252062298 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 189.edn_genbits.252062298
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/189.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/19.edn_alert_test.1000331223
Short name T400
Test name
Test status
Simulation time 46490655 ps
CPU time 0.83 seconds
Started Oct 15 11:25:54 AM UTC 24
Finished Oct 15 11:25:56 AM UTC 24
Peak memory 228444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000331223 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.1000331223
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/19.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/19.edn_disable_auto_req_mode.2625262654
Short name T401
Test name
Test status
Simulation time 24638498 ps
CPU time 1.33 seconds
Started Oct 15 11:25:54 AM UTC 24
Finished Oct 15 11:25:57 AM UTC 24
Peak memory 230148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625262654 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable_auto_req_mode.2625262654
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/19.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/19.edn_err.1667003083
Short name T153
Test name
Test status
Simulation time 32251055 ps
CPU time 1.49 seconds
Started Oct 15 11:25:54 AM UTC 24
Finished Oct 15 11:25:57 AM UTC 24
Peak memory 231832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667003083 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 19.edn_err.1667003083
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/19.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/19.edn_genbits.2714400970
Short name T95
Test name
Test status
Simulation time 122102682 ps
CPU time 1.12 seconds
Started Oct 15 11:25:51 AM UTC 24
Finished Oct 15 11:25:54 AM UTC 24
Peak memory 227848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714400970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_genbits.2714400970
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/19.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/19.edn_intr.2432468447
Short name T137
Test name
Test status
Simulation time 20214020 ps
CPU time 1.46 seconds
Started Oct 15 11:25:54 AM UTC 24
Finished Oct 15 11:25:56 AM UTC 24
Peak memory 229976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432468447 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 19.edn_intr.2432468447
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/19.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/19.edn_smoke.953091551
Short name T397
Test name
Test status
Simulation time 153449830 ps
CPU time 1.07 seconds
Started Oct 15 11:25:51 AM UTC 24
Finished Oct 15 11:25:53 AM UTC 24
Peak memory 217620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953091551 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 19.edn_smoke.953091551
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/19.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/19.edn_stress_all.3563809196
Short name T406
Test name
Test status
Simulation time 298279292 ps
CPU time 7.21 seconds
Started Oct 15 11:25:52 AM UTC 24
Finished Oct 15 11:26:01 AM UTC 24
Peak memory 231472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563809196 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.3563809196
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/19.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/19.edn_stress_all_with_rand_reset.162362896
Short name T37
Test name
Test status
Simulation time 3354842270 ps
CPU time 41.73 seconds
Started Oct 15 11:25:52 AM UTC 24
Finished Oct 15 11:26:36 AM UTC 24
Peak memory 233348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=162362896 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_
with_rand_reset.162362896
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/19.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/190.edn_alert.612689208
Short name T861
Test name
Test status
Simulation time 71366050 ps
CPU time 1.19 seconds
Started Oct 15 11:28:38 AM UTC 24
Finished Oct 15 11:28:43 AM UTC 24
Peak memory 230032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612689208 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 190.edn_alert.612689208
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/190.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/190.edn_genbits.28470572
Short name T867
Test name
Test status
Simulation time 48114451 ps
CPU time 1.57 seconds
Started Oct 15 11:28:38 AM UTC 24
Finished Oct 15 11:28:43 AM UTC 24
Peak memory 229900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28470572 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 190.edn_genbits.28470572
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/190.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/191.edn_alert.3729163980
Short name T866
Test name
Test status
Simulation time 108941515 ps
CPU time 1.33 seconds
Started Oct 15 11:28:38 AM UTC 24
Finished Oct 15 11:28:43 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729163980 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 191.edn_alert.3729163980
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/191.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/191.edn_genbits.2989025054
Short name T870
Test name
Test status
Simulation time 40118096 ps
CPU time 1.72 seconds
Started Oct 15 11:28:38 AM UTC 24
Finished Oct 15 11:28:44 AM UTC 24
Peak memory 229908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989025054 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 191.edn_genbits.2989025054
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/191.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/192.edn_alert.3516627607
Short name T850
Test name
Test status
Simulation time 65657767 ps
CPU time 1.34 seconds
Started Oct 15 11:28:39 AM UTC 24
Finished Oct 15 11:28:42 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516627607 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 192.edn_alert.3516627607
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/192.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/192.edn_genbits.4153320149
Short name T869
Test name
Test status
Simulation time 174712530 ps
CPU time 2.56 seconds
Started Oct 15 11:28:39 AM UTC 24
Finished Oct 15 11:28:43 AM UTC 24
Peak memory 233392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153320149 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 192.edn_genbits.4153320149
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/192.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/193.edn_alert.481607827
Short name T848
Test name
Test status
Simulation time 98756379 ps
CPU time 1.09 seconds
Started Oct 15 11:28:39 AM UTC 24
Finished Oct 15 11:28:42 AM UTC 24
Peak memory 230032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481607827 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 193.edn_alert.481607827
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/193.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/193.edn_genbits.483905892
Short name T846
Test name
Test status
Simulation time 58834924 ps
CPU time 0.99 seconds
Started Oct 15 11:28:39 AM UTC 24
Finished Oct 15 11:28:42 AM UTC 24
Peak memory 229908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483905892 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 193.edn_genbits.483905892
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/193.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/194.edn_alert.3736564537
Short name T852
Test name
Test status
Simulation time 46486278 ps
CPU time 1.19 seconds
Started Oct 15 11:28:39 AM UTC 24
Finished Oct 15 11:28:42 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736564537 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 194.edn_alert.3736564537
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/194.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/194.edn_genbits.1554519744
Short name T860
Test name
Test status
Simulation time 40759097 ps
CPU time 1.77 seconds
Started Oct 15 11:28:39 AM UTC 24
Finished Oct 15 11:28:43 AM UTC 24
Peak memory 229908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554519744 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 194.edn_genbits.1554519744
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/194.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/195.edn_alert.863481171
Short name T855
Test name
Test status
Simulation time 103665421 ps
CPU time 1.53 seconds
Started Oct 15 11:28:39 AM UTC 24
Finished Oct 15 11:28:43 AM UTC 24
Peak memory 232080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863481171 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 195.edn_alert.863481171
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/195.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/195.edn_genbits.1264512875
Short name T853
Test name
Test status
Simulation time 41684718 ps
CPU time 1.3 seconds
Started Oct 15 11:28:39 AM UTC 24
Finished Oct 15 11:28:42 AM UTC 24
Peak memory 229896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264512875 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 195.edn_genbits.1264512875
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/195.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/196.edn_alert.1732163850
Short name T170
Test name
Test status
Simulation time 22444991 ps
CPU time 1.18 seconds
Started Oct 15 11:28:39 AM UTC 24
Finished Oct 15 11:28:42 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732163850 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 196.edn_alert.1732163850
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/196.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/196.edn_genbits.444931960
Short name T856
Test name
Test status
Simulation time 63549387 ps
CPU time 1.33 seconds
Started Oct 15 11:28:39 AM UTC 24
Finished Oct 15 11:28:43 AM UTC 24
Peak memory 231952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444931960 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 196.edn_genbits.444931960
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/196.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/197.edn_alert.371551534
Short name T854
Test name
Test status
Simulation time 83061063 ps
CPU time 1.15 seconds
Started Oct 15 11:28:39 AM UTC 24
Finished Oct 15 11:28:42 AM UTC 24
Peak memory 232080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371551534 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 197.edn_alert.371551534
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/197.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/197.edn_genbits.1658649764
Short name T865
Test name
Test status
Simulation time 105357395 ps
CPU time 1.83 seconds
Started Oct 15 11:28:39 AM UTC 24
Finished Oct 15 11:28:43 AM UTC 24
Peak memory 229908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658649764 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 197.edn_genbits.1658649764
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/197.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/198.edn_alert.2088583937
Short name T302
Test name
Test status
Simulation time 57150453 ps
CPU time 1.32 seconds
Started Oct 15 11:28:42 AM UTC 24
Finished Oct 15 11:28:45 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088583937 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 198.edn_alert.2088583937
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/198.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/198.edn_genbits.1591558878
Short name T872
Test name
Test status
Simulation time 75172145 ps
CPU time 1.2 seconds
Started Oct 15 11:28:42 AM UTC 24
Finished Oct 15 11:28:44 AM UTC 24
Peak memory 229900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591558878 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 198.edn_genbits.1591558878
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/198.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/199.edn_alert.580015609
Short name T873
Test name
Test status
Simulation time 41530798 ps
CPU time 1.16 seconds
Started Oct 15 11:28:42 AM UTC 24
Finished Oct 15 11:28:45 AM UTC 24
Peak memory 230032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580015609 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 199.edn_alert.580015609
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/199.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/199.edn_genbits.1285938131
Short name T349
Test name
Test status
Simulation time 47042102 ps
CPU time 1.57 seconds
Started Oct 15 11:28:42 AM UTC 24
Finished Oct 15 11:28:45 AM UTC 24
Peak memory 230104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285938131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 199.edn_genbits.1285938131
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/199.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/2.edn_alert.246265025
Short name T27
Test name
Test status
Simulation time 28768606 ps
CPU time 1.57 seconds
Started Oct 15 11:24:57 AM UTC 24
Finished Oct 15 11:25:00 AM UTC 24
Peak memory 232080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246265025 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 2.edn_alert.246265025
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/2.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/2.edn_alert_test.489103273
Short name T70
Test name
Test status
Simulation time 55210841 ps
CPU time 1.23 seconds
Started Oct 15 11:24:59 AM UTC 24
Finished Oct 15 11:25:02 AM UTC 24
Peak memory 228608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489103273 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.489103273
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/2.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/2.edn_disable_auto_req_mode.2840059340
Short name T19
Test name
Test status
Simulation time 23690754 ps
CPU time 1.21 seconds
Started Oct 15 11:24:57 AM UTC 24
Finished Oct 15 11:25:00 AM UTC 24
Peak memory 231956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840059340 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable_auto_req_mode.2840059340
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/2.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/2.edn_err.1057378221
Short name T72
Test name
Test status
Simulation time 18785409 ps
CPU time 1.54 seconds
Started Oct 15 11:24:57 AM UTC 24
Finished Oct 15 11:25:00 AM UTC 24
Peak memory 229912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057378221 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 2.edn_err.1057378221
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/2.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/2.edn_genbits.3114627951
Short name T11
Test name
Test status
Simulation time 41553490 ps
CPU time 2.13 seconds
Started Oct 15 11:24:55 AM UTC 24
Finished Oct 15 11:24:58 AM UTC 24
Peak memory 233488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114627951 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_genbits.3114627951
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/2.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/2.edn_intr.854690555
Short name T29
Test name
Test status
Simulation time 23727371 ps
CPU time 1.4 seconds
Started Oct 15 11:24:56 AM UTC 24
Finished Oct 15 11:24:59 AM UTC 24
Peak memory 230392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854690555 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 2.edn_intr.854690555
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/2.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/2.edn_regwen.1289130750
Short name T69
Test name
Test status
Simulation time 92034035 ps
CPU time 1.39 seconds
Started Oct 15 11:24:54 AM UTC 24
Finished Oct 15 11:24:56 AM UTC 24
Peak memory 217624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289130750 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 2.edn_regwen.1289130750
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/2.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/2.edn_sec_cm.1049513768
Short name T18
Test name
Test status
Simulation time 586214042 ps
CPU time 9.3 seconds
Started Oct 15 11:24:59 AM UTC 24
Finished Oct 15 11:25:10 AM UTC 24
Peak memory 261740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049513768 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.1049513768
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/2.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/2.edn_smoke.1120518967
Short name T68
Test name
Test status
Simulation time 19234929 ps
CPU time 1.48 seconds
Started Oct 15 11:24:54 AM UTC 24
Finished Oct 15 11:24:56 AM UTC 24
Peak memory 227860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120518967 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 2.edn_smoke.1120518967
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/2.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/2.edn_stress_all.2710877644
Short name T61
Test name
Test status
Simulation time 274662218 ps
CPU time 7.83 seconds
Started Oct 15 11:24:56 AM UTC 24
Finished Oct 15 11:25:05 AM UTC 24
Peak memory 231096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710877644 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.2710877644
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/2.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/2.edn_stress_all_with_rand_reset.1184444695
Short name T238
Test name
Test status
Simulation time 5038818768 ps
CPU time 106.33 seconds
Started Oct 15 11:24:56 AM UTC 24
Finished Oct 15 11:26:45 AM UTC 24
Peak memory 231564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1184444695 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_
with_rand_reset.1184444695
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/2.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/20.edn_alert.2162340893
Short name T235
Test name
Test status
Simulation time 47264064 ps
CPU time 1.73 seconds
Started Oct 15 11:25:55 AM UTC 24
Finished Oct 15 11:25:58 AM UTC 24
Peak memory 230032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162340893 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 20.edn_alert.2162340893
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/20.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/20.edn_alert_test.45377255
Short name T404
Test name
Test status
Simulation time 57780698 ps
CPU time 1.28 seconds
Started Oct 15 11:25:57 AM UTC 24
Finished Oct 15 11:26:00 AM UTC 24
Peak memory 228552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45377255 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.45377255
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/20.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/20.edn_disable.1531042576
Short name T233
Test name
Test status
Simulation time 17503495 ps
CPU time 1.09 seconds
Started Oct 15 11:25:55 AM UTC 24
Finished Oct 15 11:25:58 AM UTC 24
Peak memory 227920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531042576 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.1531042576
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/20.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/20.edn_disable_auto_req_mode.2494055819
Short name T168
Test name
Test status
Simulation time 110935591 ps
CPU time 1.18 seconds
Started Oct 15 11:25:56 AM UTC 24
Finished Oct 15 11:25:59 AM UTC 24
Peak memory 227860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494055819 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable_auto_req_mode.2494055819
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/20.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/20.edn_err.3447364503
Short name T219
Test name
Test status
Simulation time 27010386 ps
CPU time 1.38 seconds
Started Oct 15 11:25:55 AM UTC 24
Finished Oct 15 11:25:58 AM UTC 24
Peak memory 229912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447364503 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 20.edn_err.3447364503
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/20.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/20.edn_genbits.3647089679
Short name T87
Test name
Test status
Simulation time 64311144 ps
CPU time 1.33 seconds
Started Oct 15 11:25:55 AM UTC 24
Finished Oct 15 11:25:58 AM UTC 24
Peak memory 227844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647089679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_genbits.3647089679
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/20.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/20.edn_intr.3882536847
Short name T402
Test name
Test status
Simulation time 22697816 ps
CPU time 1.49 seconds
Started Oct 15 11:25:55 AM UTC 24
Finished Oct 15 11:25:58 AM UTC 24
Peak memory 238312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882536847 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 20.edn_intr.3882536847
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/20.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/20.edn_smoke.3738980478
Short name T117
Test name
Test status
Simulation time 74819415 ps
CPU time 1.39 seconds
Started Oct 15 11:25:55 AM UTC 24
Finished Oct 15 11:25:58 AM UTC 24
Peak memory 217760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738980478 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 20.edn_smoke.3738980478
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/20.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/20.edn_stress_all.1291503209
Short name T259
Test name
Test status
Simulation time 124814728 ps
CPU time 3.07 seconds
Started Oct 15 11:25:55 AM UTC 24
Finished Oct 15 11:25:59 AM UTC 24
Peak memory 229352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291503209 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.1291503209
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/20.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/200.edn_genbits.3760734971
Short name T883
Test name
Test status
Simulation time 80185759 ps
CPU time 1.22 seconds
Started Oct 15 11:28:42 AM UTC 24
Finished Oct 15 11:28:52 AM UTC 24
Peak memory 229896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760734971 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 200.edn_genbits.3760734971
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/200.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/201.edn_genbits.1540352607
Short name T882
Test name
Test status
Simulation time 75447580 ps
CPU time 1.05 seconds
Started Oct 15 11:28:42 AM UTC 24
Finished Oct 15 11:28:52 AM UTC 24
Peak memory 231948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540352607 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 201.edn_genbits.1540352607
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/201.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/202.edn_genbits.2862739753
Short name T890
Test name
Test status
Simulation time 132589559 ps
CPU time 2.27 seconds
Started Oct 15 11:28:42 AM UTC 24
Finished Oct 15 11:28:53 AM UTC 24
Peak memory 233140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862739753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 202.edn_genbits.2862739753
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/202.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/203.edn_genbits.2283335325
Short name T887
Test name
Test status
Simulation time 87103112 ps
CPU time 1.61 seconds
Started Oct 15 11:28:42 AM UTC 24
Finished Oct 15 11:28:52 AM UTC 24
Peak memory 232208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283335325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 203.edn_genbits.2283335325
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/203.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/204.edn_genbits.3414269379
Short name T896
Test name
Test status
Simulation time 113339702 ps
CPU time 2.77 seconds
Started Oct 15 11:28:42 AM UTC 24
Finished Oct 15 11:28:53 AM UTC 24
Peak memory 233144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414269379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 204.edn_genbits.3414269379
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/204.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/205.edn_genbits.702813238
Short name T874
Test name
Test status
Simulation time 83083501 ps
CPU time 1.09 seconds
Started Oct 15 11:28:44 AM UTC 24
Finished Oct 15 11:28:47 AM UTC 24
Peak memory 227860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702813238 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 205.edn_genbits.702813238
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/205.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/206.edn_genbits.3987899925
Short name T880
Test name
Test status
Simulation time 324612872 ps
CPU time 2.6 seconds
Started Oct 15 11:28:44 AM UTC 24
Finished Oct 15 11:28:48 AM UTC 24
Peak memory 231084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987899925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 206.edn_genbits.3987899925
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/206.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/207.edn_genbits.3876170355
Short name T878
Test name
Test status
Simulation time 90838910 ps
CPU time 1.19 seconds
Started Oct 15 11:28:44 AM UTC 24
Finished Oct 15 11:28:47 AM UTC 24
Peak memory 229908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876170355 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 207.edn_genbits.3876170355
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/207.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/208.edn_genbits.2036393628
Short name T335
Test name
Test status
Simulation time 26983169 ps
CPU time 1.17 seconds
Started Oct 15 11:28:44 AM UTC 24
Finished Oct 15 11:28:47 AM UTC 24
Peak memory 229984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036393628 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 208.edn_genbits.2036393628
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/208.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/209.edn_genbits.1079451142
Short name T875
Test name
Test status
Simulation time 114829354 ps
CPU time 1.03 seconds
Started Oct 15 11:28:44 AM UTC 24
Finished Oct 15 11:28:47 AM UTC 24
Peak memory 227852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079451142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 209.edn_genbits.1079451142
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/209.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/21.edn_alert.2053537682
Short name T313
Test name
Test status
Simulation time 97068004 ps
CPU time 1.85 seconds
Started Oct 15 11:25:59 AM UTC 24
Finished Oct 15 11:26:02 AM UTC 24
Peak memory 230032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053537682 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 21.edn_alert.2053537682
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/21.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/21.edn_alert_test.4169929654
Short name T410
Test name
Test status
Simulation time 266001302 ps
CPU time 5.27 seconds
Started Oct 15 11:25:59 AM UTC 24
Finished Oct 15 11:26:05 AM UTC 24
Peak memory 218664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169929654 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.4169929654
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/21.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/21.edn_disable.78395558
Short name T107
Test name
Test status
Simulation time 46293052 ps
CPU time 1.29 seconds
Started Oct 15 11:25:59 AM UTC 24
Finished Oct 15 11:26:01 AM UTC 24
Peak memory 227924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78395558 -assert nopostproc +UVM_TESTNAME=edn_disab
le_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.78395558
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/21.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/21.edn_disable_auto_req_mode.50680498
Short name T292
Test name
Test status
Simulation time 34213630 ps
CPU time 1.64 seconds
Started Oct 15 11:25:59 AM UTC 24
Finished Oct 15 11:26:02 AM UTC 24
Peak memory 229968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50680498 -assert nopostproc +UVM_TESTNAME=edn_disab
le_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable_auto_req_mode.50680498
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/21.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/21.edn_err.2867039851
Short name T226
Test name
Test status
Simulation time 33145502 ps
CPU time 1.29 seconds
Started Oct 15 11:25:59 AM UTC 24
Finished Oct 15 11:26:01 AM UTC 24
Peak memory 229912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867039851 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 21.edn_err.2867039851
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/21.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/21.edn_genbits.1672361738
Short name T407
Test name
Test status
Simulation time 47791508 ps
CPU time 2.12 seconds
Started Oct 15 11:25:57 AM UTC 24
Finished Oct 15 11:26:01 AM UTC 24
Peak memory 233388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672361738 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_genbits.1672361738
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/21.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/21.edn_intr.3383904256
Short name T405
Test name
Test status
Simulation time 38192147 ps
CPU time 1.21 seconds
Started Oct 15 11:25:58 AM UTC 24
Finished Oct 15 11:26:00 AM UTC 24
Peak memory 230036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383904256 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 21.edn_intr.3383904256
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/21.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/21.edn_smoke.1778995758
Short name T403
Test name
Test status
Simulation time 29067316 ps
CPU time 1.24 seconds
Started Oct 15 11:25:57 AM UTC 24
Finished Oct 15 11:26:00 AM UTC 24
Peak memory 227852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778995758 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 21.edn_smoke.1778995758
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/21.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/21.edn_stress_all.2427273088
Short name T245
Test name
Test status
Simulation time 217751695 ps
CPU time 5.69 seconds
Started Oct 15 11:25:58 AM UTC 24
Finished Oct 15 11:26:05 AM UTC 24
Peak memory 233240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427273088 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.2427273088
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/21.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/21.edn_stress_all_with_rand_reset.3659172839
Short name T237
Test name
Test status
Simulation time 3690230812 ps
CPU time 42.52 seconds
Started Oct 15 11:25:58 AM UTC 24
Finished Oct 15 11:26:42 AM UTC 24
Peak memory 231256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3659172839 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all
_with_rand_reset.3659172839
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/21.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/210.edn_genbits.2594211673
Short name T879
Test name
Test status
Simulation time 47786623 ps
CPU time 1.34 seconds
Started Oct 15 11:28:44 AM UTC 24
Finished Oct 15 11:28:47 AM UTC 24
Peak memory 230104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594211673 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 210.edn_genbits.2594211673
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/210.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/211.edn_genbits.1915460429
Short name T876
Test name
Test status
Simulation time 38561436 ps
CPU time 0.98 seconds
Started Oct 15 11:28:44 AM UTC 24
Finished Oct 15 11:28:47 AM UTC 24
Peak memory 227860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915460429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 211.edn_genbits.1915460429
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/211.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/212.edn_genbits.1760031613
Short name T881
Test name
Test status
Simulation time 135419169 ps
CPU time 2.65 seconds
Started Oct 15 11:28:44 AM UTC 24
Finished Oct 15 11:28:49 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760031613 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 212.edn_genbits.1760031613
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/212.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/213.edn_genbits.1903004581
Short name T900
Test name
Test status
Simulation time 39707577 ps
CPU time 1.39 seconds
Started Oct 15 11:28:44 AM UTC 24
Finished Oct 15 11:28:54 AM UTC 24
Peak memory 232152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903004581 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 213.edn_genbits.1903004581
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/213.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/214.edn_genbits.3837505853
Short name T903
Test name
Test status
Simulation time 103382993 ps
CPU time 1.77 seconds
Started Oct 15 11:28:44 AM UTC 24
Finished Oct 15 11:28:55 AM UTC 24
Peak memory 229984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837505853 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 214.edn_genbits.3837505853
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/214.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/215.edn_genbits.1970819702
Short name T902
Test name
Test status
Simulation time 120949530 ps
CPU time 1.59 seconds
Started Oct 15 11:28:44 AM UTC 24
Finished Oct 15 11:28:55 AM UTC 24
Peak memory 230104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970819702 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 215.edn_genbits.1970819702
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/215.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/216.edn_genbits.351482608
Short name T877
Test name
Test status
Simulation time 214275288 ps
CPU time 0.98 seconds
Started Oct 15 11:28:44 AM UTC 24
Finished Oct 15 11:28:47 AM UTC 24
Peak memory 229908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351482608 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 216.edn_genbits.351482608
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/216.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/217.edn_genbits.3533857389
Short name T901
Test name
Test status
Simulation time 35462598 ps
CPU time 1.4 seconds
Started Oct 15 11:28:44 AM UTC 24
Finished Oct 15 11:28:55 AM UTC 24
Peak memory 229896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533857389 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 217.edn_genbits.3533857389
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/217.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/218.edn_genbits.1386171638
Short name T844
Test name
Test status
Simulation time 74093577 ps
CPU time 1.54 seconds
Started Oct 15 11:28:44 AM UTC 24
Finished Oct 15 11:28:58 AM UTC 24
Peak memory 230044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386171638 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 218.edn_genbits.1386171638
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/218.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/219.edn_genbits.4185267094
Short name T899
Test name
Test status
Simulation time 91151064 ps
CPU time 1.37 seconds
Started Oct 15 11:28:44 AM UTC 24
Finished Oct 15 11:28:54 AM UTC 24
Peak memory 229984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185267094 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 219.edn_genbits.4185267094
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/219.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/22.edn_alert.2177416679
Short name T108
Test name
Test status
Simulation time 43944571 ps
CPU time 1.51 seconds
Started Oct 15 11:26:01 AM UTC 24
Finished Oct 15 11:26:04 AM UTC 24
Peak memory 229952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177416679 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 22.edn_alert.2177416679
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/22.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/22.edn_alert_test.3063416041
Short name T246
Test name
Test status
Simulation time 16955748 ps
CPU time 1.41 seconds
Started Oct 15 11:26:02 AM UTC 24
Finished Oct 15 11:26:05 AM UTC 24
Peak memory 228552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063416041 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.3063416041
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/22.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/22.edn_disable.3987823723
Short name T243
Test name
Test status
Simulation time 13126652 ps
CPU time 0.95 seconds
Started Oct 15 11:26:01 AM UTC 24
Finished Oct 15 11:26:03 AM UTC 24
Peak memory 227976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987823723 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.3987823723
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/22.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/22.edn_disable_auto_req_mode.2277885331
Short name T248
Test name
Test status
Simulation time 75761373 ps
CPU time 1.69 seconds
Started Oct 15 11:26:02 AM UTC 24
Finished Oct 15 11:26:05 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277885331 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable_auto_req_mode.2277885331
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/22.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/22.edn_err.1425751906
Short name T221
Test name
Test status
Simulation time 75070600 ps
CPU time 1.61 seconds
Started Oct 15 11:26:01 AM UTC 24
Finished Oct 15 11:26:04 AM UTC 24
Peak memory 244340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425751906 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 22.edn_err.1425751906
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/22.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/22.edn_genbits.2259757143
Short name T79
Test name
Test status
Simulation time 39604006 ps
CPU time 1.94 seconds
Started Oct 15 11:25:59 AM UTC 24
Finished Oct 15 11:26:02 AM UTC 24
Peak memory 231956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2259757143 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_genbits.2259757143
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/22.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/22.edn_intr.822056602
Short name T244
Test name
Test status
Simulation time 20577794 ps
CPU time 1.18 seconds
Started Oct 15 11:26:01 AM UTC 24
Finished Oct 15 11:26:04 AM UTC 24
Peak memory 229968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822056602 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 22.edn_intr.822056602
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/22.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/22.edn_smoke.4075177708
Short name T408
Test name
Test status
Simulation time 25185887 ps
CPU time 1.1 seconds
Started Oct 15 11:25:59 AM UTC 24
Finished Oct 15 11:26:01 AM UTC 24
Peak memory 217624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075177708 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 22.edn_smoke.4075177708
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/22.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/22.edn_stress_all.3354241543
Short name T415
Test name
Test status
Simulation time 245439325 ps
CPU time 6.69 seconds
Started Oct 15 11:26:00 AM UTC 24
Finished Oct 15 11:26:08 AM UTC 24
Peak memory 233144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354241543 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.3354241543
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/22.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/22.edn_stress_all_with_rand_reset.376722657
Short name T250
Test name
Test status
Simulation time 4045680113 ps
CPU time 83.3 seconds
Started Oct 15 11:26:00 AM UTC 24
Finished Oct 15 11:27:25 AM UTC 24
Peak memory 231300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=376722657 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_
with_rand_reset.376722657
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/22.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/220.edn_genbits.373560759
Short name T904
Test name
Test status
Simulation time 106105798 ps
CPU time 1.03 seconds
Started Oct 15 11:28:44 AM UTC 24
Finished Oct 15 11:28:57 AM UTC 24
Peak memory 230048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373560759 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 220.edn_genbits.373560759
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/220.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/221.edn_genbits.2573123981
Short name T909
Test name
Test status
Simulation time 156575200 ps
CPU time 1.52 seconds
Started Oct 15 11:28:44 AM UTC 24
Finished Oct 15 11:28:58 AM UTC 24
Peak memory 229956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573123981 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 221.edn_genbits.2573123981
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/221.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/222.edn_genbits.2682125732
Short name T905
Test name
Test status
Simulation time 45778514 ps
CPU time 1.04 seconds
Started Oct 15 11:28:44 AM UTC 24
Finished Oct 15 11:28:57 AM UTC 24
Peak memory 229616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682125732 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 222.edn_genbits.2682125732
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/222.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/223.edn_genbits.2823180894
Short name T912
Test name
Test status
Simulation time 301347832 ps
CPU time 2.89 seconds
Started Oct 15 11:28:44 AM UTC 24
Finished Oct 15 11:28:59 AM UTC 24
Peak memory 230972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823180894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 223.edn_genbits.2823180894
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/223.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/225.edn_genbits.1610042566
Short name T911
Test name
Test status
Simulation time 39065217 ps
CPU time 1.51 seconds
Started Oct 15 11:28:44 AM UTC 24
Finished Oct 15 11:28:58 AM UTC 24
Peak memory 229908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610042566 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 225.edn_genbits.1610042566
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/225.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/23.edn_alert_test.110821639
Short name T413
Test name
Test status
Simulation time 18380693 ps
CPU time 1.21 seconds
Started Oct 15 11:26:05 AM UTC 24
Finished Oct 15 11:26:07 AM UTC 24
Peak memory 228588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110821639 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.110821639
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/23.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/23.edn_disable_auto_req_mode.3342713286
Short name T414
Test name
Test status
Simulation time 93798596 ps
CPU time 1.56 seconds
Started Oct 15 11:26:05 AM UTC 24
Finished Oct 15 11:26:08 AM UTC 24
Peak memory 229968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342713286 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable_auto_req_mode.3342713286
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/23.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/23.edn_err.1973001274
Short name T193
Test name
Test status
Simulation time 45144629 ps
CPU time 1.11 seconds
Started Oct 15 11:26:04 AM UTC 24
Finished Oct 15 11:26:06 AM UTC 24
Peak memory 238248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973001274 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 23.edn_err.1973001274
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/23.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/23.edn_genbits.3075011394
Short name T249
Test name
Test status
Simulation time 65647365 ps
CPU time 1.68 seconds
Started Oct 15 11:26:03 AM UTC 24
Finished Oct 15 11:26:05 AM UTC 24
Peak memory 230104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075011394 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_genbits.3075011394
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/23.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/23.edn_intr.3036889189
Short name T411
Test name
Test status
Simulation time 36311822 ps
CPU time 1.02 seconds
Started Oct 15 11:26:04 AM UTC 24
Finished Oct 15 11:26:06 AM UTC 24
Peak memory 227988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036889189 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 23.edn_intr.3036889189
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/23.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/23.edn_smoke.1178169911
Short name T247
Test name
Test status
Simulation time 16901881 ps
CPU time 1.49 seconds
Started Oct 15 11:26:03 AM UTC 24
Finished Oct 15 11:26:05 AM UTC 24
Peak memory 227852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178169911 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 23.edn_smoke.1178169911
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/23.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/23.edn_stress_all.2735158068
Short name T409
Test name
Test status
Simulation time 113145443 ps
CPU time 1.84 seconds
Started Oct 15 11:26:03 AM UTC 24
Finished Oct 15 11:26:05 AM UTC 24
Peak memory 227860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735158068 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.2735158068
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/23.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/23.edn_stress_all_with_rand_reset.1202709657
Short name T251
Test name
Test status
Simulation time 4924506321 ps
CPU time 107.86 seconds
Started Oct 15 11:26:03 AM UTC 24
Finished Oct 15 11:27:53 AM UTC 24
Peak memory 231304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1202709657 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all
_with_rand_reset.1202709657
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/23.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/233.edn_genbits.1821974142
Short name T913
Test name
Test status
Simulation time 95532309 ps
CPU time 0.88 seconds
Started Oct 15 11:28:45 AM UTC 24
Finished Oct 15 11:29:02 AM UTC 24
Peak memory 227852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821974142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 233.edn_genbits.1821974142
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/233.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/234.edn_genbits.3392707004
Short name T889
Test name
Test status
Simulation time 57101583 ps
CPU time 1.18 seconds
Started Oct 15 11:28:47 AM UTC 24
Finished Oct 15 11:28:53 AM UTC 24
Peak memory 229908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392707004 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 234.edn_genbits.3392707004
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/234.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/235.edn_genbits.2633964760
Short name T895
Test name
Test status
Simulation time 46127169 ps
CPU time 1.65 seconds
Started Oct 15 11:28:48 AM UTC 24
Finished Oct 15 11:28:53 AM UTC 24
Peak memory 230044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633964760 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 235.edn_genbits.2633964760
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/235.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/236.edn_genbits.863235638
Short name T892
Test name
Test status
Simulation time 53974236 ps
CPU time 1.21 seconds
Started Oct 15 11:28:48 AM UTC 24
Finished Oct 15 11:28:53 AM UTC 24
Peak memory 231832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863235638 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 236.edn_genbits.863235638
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/236.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/237.edn_genbits.1563035603
Short name T888
Test name
Test status
Simulation time 69518172 ps
CPU time 0.96 seconds
Started Oct 15 11:28:48 AM UTC 24
Finished Oct 15 11:28:53 AM UTC 24
Peak memory 227844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563035603 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 237.edn_genbits.1563035603
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/237.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/238.edn_genbits.2150429373
Short name T891
Test name
Test status
Simulation time 47669799 ps
CPU time 1.06 seconds
Started Oct 15 11:28:48 AM UTC 24
Finished Oct 15 11:28:53 AM UTC 24
Peak memory 231956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150429373 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 238.edn_genbits.2150429373
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/238.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/239.edn_genbits.2971075530
Short name T893
Test name
Test status
Simulation time 30209948 ps
CPU time 1.12 seconds
Started Oct 15 11:28:48 AM UTC 24
Finished Oct 15 11:28:53 AM UTC 24
Peak memory 227844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971075530 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 239.edn_genbits.2971075530
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/239.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/24.edn_alert.603335511
Short name T320
Test name
Test status
Simulation time 28194784 ps
CPU time 1.77 seconds
Started Oct 15 11:26:06 AM UTC 24
Finished Oct 15 11:26:09 AM UTC 24
Peak memory 227656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603335511 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 24.edn_alert.603335511
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/24.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/24.edn_alert_test.965101990
Short name T418
Test name
Test status
Simulation time 43505317 ps
CPU time 1.27 seconds
Started Oct 15 11:26:08 AM UTC 24
Finished Oct 15 11:26:10 AM UTC 24
Peak memory 217852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965101990 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.965101990
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/24.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/24.edn_disable.2385258511
Short name T416
Test name
Test status
Simulation time 30153744 ps
CPU time 1.09 seconds
Started Oct 15 11:26:06 AM UTC 24
Finished Oct 15 11:26:09 AM UTC 24
Peak memory 227916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385258511 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.2385258511
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/24.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/24.edn_disable_auto_req_mode.3087897049
Short name T419
Test name
Test status
Simulation time 44181579 ps
CPU time 1.54 seconds
Started Oct 15 11:26:08 AM UTC 24
Finished Oct 15 11:26:10 AM UTC 24
Peak memory 230148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087897049 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable_auto_req_mode.3087897049
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/24.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/24.edn_err.2483690596
Short name T417
Test name
Test status
Simulation time 43923223 ps
CPU time 1.56 seconds
Started Oct 15 11:26:06 AM UTC 24
Finished Oct 15 11:26:09 AM UTC 24
Peak memory 231960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483690596 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 24.edn_err.2483690596
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/24.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/24.edn_genbits.3782753162
Short name T88
Test name
Test status
Simulation time 95183853 ps
CPU time 1.41 seconds
Started Oct 15 11:26:06 AM UTC 24
Finished Oct 15 11:26:09 AM UTC 24
Peak memory 229904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782753162 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_genbits.3782753162
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/24.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/24.edn_intr.3743743808
Short name T112
Test name
Test status
Simulation time 20650025 ps
CPU time 1.36 seconds
Started Oct 15 11:26:06 AM UTC 24
Finished Oct 15 11:26:09 AM UTC 24
Peak memory 229976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743743808 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 24.edn_intr.3743743808
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/24.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/24.edn_smoke.1774430783
Short name T412
Test name
Test status
Simulation time 27088298 ps
CPU time 1.01 seconds
Started Oct 15 11:26:05 AM UTC 24
Finished Oct 15 11:26:07 AM UTC 24
Peak memory 227832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774430783 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 24.edn_smoke.1774430783
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/24.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/24.edn_stress_all.1642712982
Short name T421
Test name
Test status
Simulation time 159570250 ps
CPU time 3.32 seconds
Started Oct 15 11:26:06 AM UTC 24
Finished Oct 15 11:26:11 AM UTC 24
Peak memory 229044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642712982 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.1642712982
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/24.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/24.edn_stress_all_with_rand_reset.2327329393
Short name T239
Test name
Test status
Simulation time 8796860896 ps
CPU time 37.3 seconds
Started Oct 15 11:26:06 AM UTC 24
Finished Oct 15 11:26:45 AM UTC 24
Peak memory 235864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2327329393 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all
_with_rand_reset.2327329393
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/24.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/240.edn_genbits.2327612789
Short name T894
Test name
Test status
Simulation time 64055519 ps
CPU time 1.33 seconds
Started Oct 15 11:28:48 AM UTC 24
Finished Oct 15 11:28:53 AM UTC 24
Peak memory 229736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327612789 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 240.edn_genbits.2327612789
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/240.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/241.edn_genbits.3968313992
Short name T884
Test name
Test status
Simulation time 29168965 ps
CPU time 1.07 seconds
Started Oct 15 11:28:49 AM UTC 24
Finished Oct 15 11:28:52 AM UTC 24
Peak memory 227860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968313992 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 241.edn_genbits.3968313992
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/241.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/242.edn_genbits.696428558
Short name T885
Test name
Test status
Simulation time 68253515 ps
CPU time 1.18 seconds
Started Oct 15 11:28:49 AM UTC 24
Finished Oct 15 11:28:52 AM UTC 24
Peak memory 230104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696428558 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 242.edn_genbits.696428558
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/242.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/243.edn_genbits.4137042183
Short name T886
Test name
Test status
Simulation time 31891737 ps
CPU time 1.34 seconds
Started Oct 15 11:28:50 AM UTC 24
Finished Oct 15 11:28:52 AM UTC 24
Peak memory 230044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137042183 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 243.edn_genbits.4137042183
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/243.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/244.edn_genbits.2342205474
Short name T897
Test name
Test status
Simulation time 71732885 ps
CPU time 0.94 seconds
Started Oct 15 11:28:52 AM UTC 24
Finished Oct 15 11:28:54 AM UTC 24
Peak memory 231956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342205474 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 244.edn_genbits.2342205474
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/244.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/245.edn_genbits.475387969
Short name T950
Test name
Test status
Simulation time 45916378 ps
CPU time 1.46 seconds
Started Oct 15 11:28:53 AM UTC 24
Finished Oct 15 11:29:13 AM UTC 24
Peak memory 229972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475387969 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 245.edn_genbits.475387969
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/245.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/246.edn_genbits.995546576
Short name T350
Test name
Test status
Simulation time 65064099 ps
CPU time 1.37 seconds
Started Oct 15 11:28:53 AM UTC 24
Finished Oct 15 11:29:03 AM UTC 24
Peak memory 229772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995546576 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 246.edn_genbits.995546576
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/246.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/247.edn_genbits.2484700744
Short name T918
Test name
Test status
Simulation time 79824265 ps
CPU time 1.28 seconds
Started Oct 15 11:28:53 AM UTC 24
Finished Oct 15 11:29:03 AM UTC 24
Peak memory 229756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484700744 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 247.edn_genbits.2484700744
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/247.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/248.edn_genbits.1685861146
Short name T915
Test name
Test status
Simulation time 94433996 ps
CPU time 1.07 seconds
Started Oct 15 11:28:53 AM UTC 24
Finished Oct 15 11:29:02 AM UTC 24
Peak memory 231964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685861146 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 248.edn_genbits.1685861146
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/248.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/249.edn_genbits.669167002
Short name T923
Test name
Test status
Simulation time 60161867 ps
CPU time 1.99 seconds
Started Oct 15 11:28:53 AM UTC 24
Finished Oct 15 11:29:04 AM UTC 24
Peak memory 232152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669167002 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 249.edn_genbits.669167002
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/249.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/25.edn_alert.2306019575
Short name T423
Test name
Test status
Simulation time 88846373 ps
CPU time 1.72 seconds
Started Oct 15 11:26:09 AM UTC 24
Finished Oct 15 11:26:12 AM UTC 24
Peak memory 230032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306019575 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 25.edn_alert.2306019575
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/25.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/25.edn_alert_test.527452456
Short name T425
Test name
Test status
Simulation time 64297496 ps
CPU time 1.35 seconds
Started Oct 15 11:26:10 AM UTC 24
Finished Oct 15 11:26:13 AM UTC 24
Peak memory 228576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527452456 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.527452456
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/25.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/25.edn_disable.415897078
Short name T424
Test name
Test status
Simulation time 16906843 ps
CPU time 1.21 seconds
Started Oct 15 11:26:10 AM UTC 24
Finished Oct 15 11:26:13 AM UTC 24
Peak memory 227916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415897078 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.415897078
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/25.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/25.edn_disable_auto_req_mode.1290374488
Short name T232
Test name
Test status
Simulation time 259586095 ps
CPU time 1.62 seconds
Started Oct 15 11:26:10 AM UTC 24
Finished Oct 15 11:26:13 AM UTC 24
Peak memory 231956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290374488 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable_auto_req_mode.1290374488
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/25.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/25.edn_err.1591586292
Short name T185
Test name
Test status
Simulation time 18765803 ps
CPU time 1.58 seconds
Started Oct 15 11:26:10 AM UTC 24
Finished Oct 15 11:26:13 AM UTC 24
Peak memory 229912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591586292 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 25.edn_err.1591586292
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/25.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/25.edn_genbits.1745199777
Short name T80
Test name
Test status
Simulation time 70711917 ps
CPU time 2.01 seconds
Started Oct 15 11:26:08 AM UTC 24
Finished Oct 15 11:26:11 AM UTC 24
Peak memory 229788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745199777 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_genbits.1745199777
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/25.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/25.edn_intr.3729077989
Short name T422
Test name
Test status
Simulation time 22464327 ps
CPU time 1.3 seconds
Started Oct 15 11:26:09 AM UTC 24
Finished Oct 15 11:26:11 AM UTC 24
Peak memory 228168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729077989 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 25.edn_intr.3729077989
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/25.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/25.edn_smoke.3702560761
Short name T420
Test name
Test status
Simulation time 17965974 ps
CPU time 1.42 seconds
Started Oct 15 11:26:08 AM UTC 24
Finished Oct 15 11:26:10 AM UTC 24
Peak memory 227864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702560761 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 25.edn_smoke.3702560761
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/25.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/25.edn_stress_all.1868406745
Short name T357
Test name
Test status
Simulation time 576094077 ps
CPU time 3.51 seconds
Started Oct 15 11:26:08 AM UTC 24
Finished Oct 15 11:26:12 AM UTC 24
Peak memory 231384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868406745 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.1868406745
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/25.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/250.edn_genbits.2113754894
Short name T906
Test name
Test status
Simulation time 60912285 ps
CPU time 1.09 seconds
Started Oct 15 11:28:54 AM UTC 24
Finished Oct 15 11:28:57 AM UTC 24
Peak memory 229176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113754894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 250.edn_genbits.2113754894
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/250.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/251.edn_genbits.1679880454
Short name T907
Test name
Test status
Simulation time 96792907 ps
CPU time 1.29 seconds
Started Oct 15 11:28:54 AM UTC 24
Finished Oct 15 11:28:58 AM UTC 24
Peak memory 229900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679880454 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 251.edn_genbits.1679880454
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/251.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/252.edn_genbits.1631304967
Short name T908
Test name
Test status
Simulation time 46507714 ps
CPU time 1.46 seconds
Started Oct 15 11:28:54 AM UTC 24
Finished Oct 15 11:28:58 AM UTC 24
Peak memory 227580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631304967 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 252.edn_genbits.1631304967
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/252.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/253.edn_genbits.2198449726
Short name T838
Test name
Test status
Simulation time 37363604 ps
CPU time 1.29 seconds
Started Oct 15 11:28:54 AM UTC 24
Finished Oct 15 11:28:58 AM UTC 24
Peak memory 227844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198449726 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 253.edn_genbits.2198449726
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/253.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/254.edn_genbits.3855316028
Short name T910
Test name
Test status
Simulation time 74237335 ps
CPU time 1.43 seconds
Started Oct 15 11:28:54 AM UTC 24
Finished Oct 15 11:28:58 AM UTC 24
Peak memory 229784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855316028 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 254.edn_genbits.3855316028
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/254.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/255.edn_genbits.1538075887
Short name T932
Test name
Test status
Simulation time 94530476 ps
CPU time 1.29 seconds
Started Oct 15 11:28:54 AM UTC 24
Finished Oct 15 11:29:08 AM UTC 24
Peak memory 230040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538075887 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 255.edn_genbits.1538075887
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/255.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/256.edn_genbits.1908470689
Short name T934
Test name
Test status
Simulation time 36764769 ps
CPU time 1.29 seconds
Started Oct 15 11:28:54 AM UTC 24
Finished Oct 15 11:29:08 AM UTC 24
Peak memory 230104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908470689 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 256.edn_genbits.1908470689
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/256.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/257.edn_genbits.2768977663
Short name T930
Test name
Test status
Simulation time 83554836 ps
CPU time 1.11 seconds
Started Oct 15 11:28:54 AM UTC 24
Finished Oct 15 11:29:08 AM UTC 24
Peak memory 229900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768977663 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 257.edn_genbits.2768977663
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/257.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/258.edn_genbits.2275550224
Short name T939
Test name
Test status
Simulation time 68983600 ps
CPU time 1.55 seconds
Started Oct 15 11:28:54 AM UTC 24
Finished Oct 15 11:29:08 AM UTC 24
Peak memory 230044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275550224 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 258.edn_genbits.2275550224
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/258.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/259.edn_genbits.3546821170
Short name T936
Test name
Test status
Simulation time 61902372 ps
CPU time 1.38 seconds
Started Oct 15 11:28:55 AM UTC 24
Finished Oct 15 11:29:08 AM UTC 24
Peak memory 232248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546821170 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 259.edn_genbits.3546821170
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/259.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/26.edn_alert.1817799407
Short name T177
Test name
Test status
Simulation time 24596447 ps
CPU time 1.72 seconds
Started Oct 15 11:26:11 AM UTC 24
Finished Oct 15 11:26:14 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817799407 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 26.edn_alert.1817799407
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/26.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/26.edn_alert_test.46328805
Short name T432
Test name
Test status
Simulation time 23010357 ps
CPU time 1.6 seconds
Started Oct 15 11:26:14 AM UTC 24
Finished Oct 15 11:26:16 AM UTC 24
Peak memory 217852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46328805 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.46328805
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/26.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/26.edn_disable.4060224919
Short name T429
Test name
Test status
Simulation time 32804288 ps
CPU time 1.17 seconds
Started Oct 15 11:26:13 AM UTC 24
Finished Oct 15 11:26:15 AM UTC 24
Peak memory 228036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060224919 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.4060224919
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/26.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/26.edn_disable_auto_req_mode.606784202
Short name T430
Test name
Test status
Simulation time 29245848 ps
CPU time 1.76 seconds
Started Oct 15 11:26:13 AM UTC 24
Finished Oct 15 11:26:16 AM UTC 24
Peak memory 227848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606784202 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable_auto_req_mode.606784202
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/26.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/26.edn_err.947221544
Short name T258
Test name
Test status
Simulation time 100508242 ps
CPU time 1.88 seconds
Started Oct 15 11:26:13 AM UTC 24
Finished Oct 15 11:26:16 AM UTC 24
Peak memory 244312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947221544 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 26.edn_err.947221544
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/26.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/26.edn_genbits.1855610377
Short name T428
Test name
Test status
Simulation time 196267189 ps
CPU time 2.24 seconds
Started Oct 15 11:26:11 AM UTC 24
Finished Oct 15 11:26:15 AM UTC 24
Peak memory 231340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855610377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_genbits.1855610377
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/26.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/26.edn_intr.3398456707
Short name T427
Test name
Test status
Simulation time 39305770 ps
CPU time 1.29 seconds
Started Oct 15 11:26:11 AM UTC 24
Finished Oct 15 11:26:14 AM UTC 24
Peak memory 230040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398456707 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 26.edn_intr.3398456707
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/26.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/26.edn_smoke.3884314866
Short name T426
Test name
Test status
Simulation time 18993867 ps
CPU time 1.38 seconds
Started Oct 15 11:26:10 AM UTC 24
Finished Oct 15 11:26:13 AM UTC 24
Peak memory 227848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884314866 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 26.edn_smoke.3884314866
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/26.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/26.edn_stress_all.3045170867
Short name T435
Test name
Test status
Simulation time 328776945 ps
CPU time 5.03 seconds
Started Oct 15 11:26:11 AM UTC 24
Finished Oct 15 11:26:18 AM UTC 24
Peak memory 231424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045170867 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.3045170867
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/26.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/26.edn_stress_all_with_rand_reset.895033697
Short name T568
Test name
Test status
Simulation time 4937552456 ps
CPU time 61.37 seconds
Started Oct 15 11:26:11 AM UTC 24
Finished Oct 15 11:27:15 AM UTC 24
Peak memory 231300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=895033697 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_
with_rand_reset.895033697
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/26.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/260.edn_genbits.2372863210
Short name T933
Test name
Test status
Simulation time 63717508 ps
CPU time 1.08 seconds
Started Oct 15 11:28:55 AM UTC 24
Finished Oct 15 11:29:08 AM UTC 24
Peak memory 230044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372863210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 260.edn_genbits.2372863210
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/260.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/261.edn_genbits.3001249901
Short name T937
Test name
Test status
Simulation time 37136532 ps
CPU time 1.42 seconds
Started Oct 15 11:28:55 AM UTC 24
Finished Oct 15 11:29:08 AM UTC 24
Peak memory 229968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001249901 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 261.edn_genbits.3001249901
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/261.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/262.edn_genbits.1782874159
Short name T938
Test name
Test status
Simulation time 41086102 ps
CPU time 1.36 seconds
Started Oct 15 11:28:55 AM UTC 24
Finished Oct 15 11:29:08 AM UTC 24
Peak memory 229908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782874159 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 262.edn_genbits.1782874159
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/262.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/263.edn_genbits.3774140881
Short name T961
Test name
Test status
Simulation time 34536200 ps
CPU time 0.95 seconds
Started Oct 15 11:28:56 AM UTC 24
Finished Oct 15 11:29:15 AM UTC 24
Peak memory 230044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774140881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 263.edn_genbits.3774140881
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/263.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/264.edn_genbits.1423100853
Short name T940
Test name
Test status
Simulation time 129180771 ps
CPU time 2.35 seconds
Started Oct 15 11:28:56 AM UTC 24
Finished Oct 15 11:29:09 AM UTC 24
Peak memory 233144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423100853 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 264.edn_genbits.1423100853
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/264.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/266.edn_genbits.2455260535
Short name T951
Test name
Test status
Simulation time 72651329 ps
CPU time 1.15 seconds
Started Oct 15 11:28:58 AM UTC 24
Finished Oct 15 11:29:13 AM UTC 24
Peak memory 230104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455260535 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 266.edn_genbits.2455260535
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/266.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/267.edn_genbits.683055373
Short name T952
Test name
Test status
Simulation time 67622958 ps
CPU time 1.33 seconds
Started Oct 15 11:28:58 AM UTC 24
Finished Oct 15 11:29:13 AM UTC 24
Peak memory 230108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683055373 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 267.edn_genbits.683055373
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/267.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/268.edn_genbits.1558284852
Short name T953
Test name
Test status
Simulation time 43613075 ps
CPU time 1.73 seconds
Started Oct 15 11:28:58 AM UTC 24
Finished Oct 15 11:29:14 AM UTC 24
Peak memory 229908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558284852 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1558284852
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/268.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/269.edn_genbits.4027488155
Short name T917
Test name
Test status
Simulation time 59020897 ps
CPU time 1.34 seconds
Started Oct 15 11:28:59 AM UTC 24
Finished Oct 15 11:29:03 AM UTC 24
Peak memory 231692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027488155 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 269.edn_genbits.4027488155
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/269.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/27.edn_alert.2024653561
Short name T293
Test name
Test status
Simulation time 26258561 ps
CPU time 1.84 seconds
Started Oct 15 11:26:15 AM UTC 24
Finished Oct 15 11:26:18 AM UTC 24
Peak memory 230032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024653561 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 27.edn_alert.2024653561
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/27.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/27.edn_alert_test.4267837851
Short name T438
Test name
Test status
Simulation time 125245212 ps
CPU time 1.27 seconds
Started Oct 15 11:26:16 AM UTC 24
Finished Oct 15 11:26:18 AM UTC 24
Peak memory 217948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267837851 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.4267837851
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/27.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/27.edn_disable.2350111216
Short name T437
Test name
Test status
Simulation time 13959678 ps
CPU time 1.01 seconds
Started Oct 15 11:26:16 AM UTC 24
Finished Oct 15 11:26:18 AM UTC 24
Peak memory 228036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350111216 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.2350111216
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/27.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/27.edn_disable_auto_req_mode.62135350
Short name T356
Test name
Test status
Simulation time 135432498 ps
CPU time 1.28 seconds
Started Oct 15 11:26:16 AM UTC 24
Finished Oct 15 11:26:18 AM UTC 24
Peak memory 229908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62135350 -assert nopostproc +UVM_TESTNAME=edn_disab
le_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable_auto_req_mode.62135350
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/27.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/27.edn_err.2059805616
Short name T439
Test name
Test status
Simulation time 18319481 ps
CPU time 1.67 seconds
Started Oct 15 11:26:16 AM UTC 24
Finished Oct 15 11:26:19 AM UTC 24
Peak memory 238444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059805616 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 27.edn_err.2059805616
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/27.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/27.edn_genbits.3138158069
Short name T433
Test name
Test status
Simulation time 77221636 ps
CPU time 1.55 seconds
Started Oct 15 11:26:14 AM UTC 24
Finished Oct 15 11:26:17 AM UTC 24
Peak memory 227844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138158069 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_genbits.3138158069
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/27.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/27.edn_intr.1639942983
Short name T436
Test name
Test status
Simulation time 20091951 ps
CPU time 1.62 seconds
Started Oct 15 11:26:15 AM UTC 24
Finished Oct 15 11:26:18 AM UTC 24
Peak memory 230036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639942983 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 27.edn_intr.1639942983
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/27.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/27.edn_smoke.3460136443
Short name T431
Test name
Test status
Simulation time 80192777 ps
CPU time 1.39 seconds
Started Oct 15 11:26:14 AM UTC 24
Finished Oct 15 11:26:16 AM UTC 24
Peak memory 227864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460136443 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 27.edn_smoke.3460136443
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/27.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/27.edn_stress_all.2346749089
Short name T434
Test name
Test status
Simulation time 195707174 ps
CPU time 2.33 seconds
Started Oct 15 11:26:14 AM UTC 24
Finished Oct 15 11:26:17 AM UTC 24
Peak memory 228992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346749089 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.2346749089
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/27.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/270.edn_genbits.1257888366
Short name T919
Test name
Test status
Simulation time 47128464 ps
CPU time 1.38 seconds
Started Oct 15 11:28:59 AM UTC 24
Finished Oct 15 11:29:03 AM UTC 24
Peak memory 227860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257888366 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 270.edn_genbits.1257888366
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/270.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/271.edn_genbits.2990298745
Short name T914
Test name
Test status
Simulation time 39103120 ps
CPU time 0.98 seconds
Started Oct 15 11:28:59 AM UTC 24
Finished Oct 15 11:29:02 AM UTC 24
Peak memory 229764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990298745 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 271.edn_genbits.2990298745
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/271.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/272.edn_genbits.3556900424
Short name T924
Test name
Test status
Simulation time 381968679 ps
CPU time 2.37 seconds
Started Oct 15 11:28:59 AM UTC 24
Finished Oct 15 11:29:04 AM UTC 24
Peak memory 232984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556900424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 272.edn_genbits.3556900424
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/272.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/273.edn_genbits.116415555
Short name T922
Test name
Test status
Simulation time 43314395 ps
CPU time 1.57 seconds
Started Oct 15 11:28:59 AM UTC 24
Finished Oct 15 11:29:03 AM UTC 24
Peak memory 229968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116415555 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 273.edn_genbits.116415555
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/273.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/274.edn_genbits.3126754431
Short name T920
Test name
Test status
Simulation time 39293443 ps
CPU time 1.31 seconds
Started Oct 15 11:28:59 AM UTC 24
Finished Oct 15 11:29:03 AM UTC 24
Peak memory 229904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126754431 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 274.edn_genbits.3126754431
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/274.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/275.edn_genbits.4037625340
Short name T921
Test name
Test status
Simulation time 49006316 ps
CPU time 1.39 seconds
Started Oct 15 11:28:59 AM UTC 24
Finished Oct 15 11:29:03 AM UTC 24
Peak memory 229660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037625340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 275.edn_genbits.4037625340
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/275.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/276.edn_genbits.1965875126
Short name T916
Test name
Test status
Simulation time 172908851 ps
CPU time 1.05 seconds
Started Oct 15 11:29:00 AM UTC 24
Finished Oct 15 11:29:03 AM UTC 24
Peak memory 231952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965875126 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 276.edn_genbits.1965875126
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/276.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/277.edn_genbits.1142079311
Short name T949
Test name
Test status
Simulation time 40328606 ps
CPU time 1.64 seconds
Started Oct 15 11:29:03 AM UTC 24
Finished Oct 15 11:29:13 AM UTC 24
Peak memory 227996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142079311 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 277.edn_genbits.1142079311
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/277.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/278.edn_genbits.3441670161
Short name T946
Test name
Test status
Simulation time 49804948 ps
CPU time 1.18 seconds
Started Oct 15 11:29:03 AM UTC 24
Finished Oct 15 11:29:12 AM UTC 24
Peak memory 227844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441670161 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 278.edn_genbits.3441670161
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/278.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/279.edn_genbits.1330546103
Short name T948
Test name
Test status
Simulation time 36355491 ps
CPU time 1.44 seconds
Started Oct 15 11:29:03 AM UTC 24
Finished Oct 15 11:29:13 AM UTC 24
Peak memory 230044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330546103 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 279.edn_genbits.1330546103
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/279.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/28.edn_alert.3362343163
Short name T312
Test name
Test status
Simulation time 28778115 ps
CPU time 1.84 seconds
Started Oct 15 11:26:19 AM UTC 24
Finished Oct 15 11:26:21 AM UTC 24
Peak memory 232080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362343163 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 28.edn_alert.3362343163
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/28.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/28.edn_alert_test.1341520451
Short name T444
Test name
Test status
Simulation time 30427092 ps
CPU time 1.2 seconds
Started Oct 15 11:26:19 AM UTC 24
Finished Oct 15 11:26:21 AM UTC 24
Peak memory 217920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341520451 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.1341520451
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/28.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/28.edn_disable.1829616288
Short name T443
Test name
Test status
Simulation time 10621710 ps
CPU time 1.08 seconds
Started Oct 15 11:26:19 AM UTC 24
Finished Oct 15 11:26:21 AM UTC 24
Peak memory 227916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829616288 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.1829616288
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/28.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/28.edn_disable_auto_req_mode.246436085
Short name T220
Test name
Test status
Simulation time 113661141 ps
CPU time 1.75 seconds
Started Oct 15 11:26:19 AM UTC 24
Finished Oct 15 11:26:22 AM UTC 24
Peak memory 227856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246436085 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable_auto_req_mode.246436085
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/28.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/28.edn_err.2098390688
Short name T445
Test name
Test status
Simulation time 26593328 ps
CPU time 1.43 seconds
Started Oct 15 11:26:19 AM UTC 24
Finished Oct 15 11:26:21 AM UTC 24
Peak memory 230268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098390688 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 28.edn_err.2098390688
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/28.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/28.edn_genbits.2978648248
Short name T441
Test name
Test status
Simulation time 71685563 ps
CPU time 1.6 seconds
Started Oct 15 11:26:17 AM UTC 24
Finished Oct 15 11:26:20 AM UTC 24
Peak memory 229896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978648248 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_genbits.2978648248
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/28.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/28.edn_intr.1889442197
Short name T442
Test name
Test status
Simulation time 20508734 ps
CPU time 1.12 seconds
Started Oct 15 11:26:19 AM UTC 24
Finished Oct 15 11:26:21 AM UTC 24
Peak memory 227928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889442197 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 28.edn_intr.1889442197
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/28.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/28.edn_smoke.3367256675
Short name T440
Test name
Test status
Simulation time 64818785 ps
CPU time 1.35 seconds
Started Oct 15 11:26:17 AM UTC 24
Finished Oct 15 11:26:20 AM UTC 24
Peak memory 227852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367256675 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 28.edn_smoke.3367256675
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/28.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/28.edn_stress_all.4063532269
Short name T446
Test name
Test status
Simulation time 72523683 ps
CPU time 2.91 seconds
Started Oct 15 11:26:17 AM UTC 24
Finished Oct 15 11:26:21 AM UTC 24
Peak memory 229140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063532269 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.4063532269
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/28.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/28.edn_stress_all_with_rand_reset.1645857102
Short name T242
Test name
Test status
Simulation time 1599482654 ps
CPU time 39.74 seconds
Started Oct 15 11:26:17 AM UTC 24
Finished Oct 15 11:26:59 AM UTC 24
Peak memory 229448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1645857102 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all
_with_rand_reset.1645857102
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/28.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/280.edn_genbits.3976676438
Short name T954
Test name
Test status
Simulation time 76345122 ps
CPU time 2.53 seconds
Started Oct 15 11:29:03 AM UTC 24
Finished Oct 15 11:29:14 AM UTC 24
Peak memory 233144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976676438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 280.edn_genbits.3976676438
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/280.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/281.edn_genbits.4210074938
Short name T958
Test name
Test status
Simulation time 195454471 ps
CPU time 3.21 seconds
Started Oct 15 11:29:03 AM UTC 24
Finished Oct 15 11:29:15 AM UTC 24
Peak memory 233408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210074938 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 281.edn_genbits.4210074938
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/281.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/282.edn_genbits.2602754146
Short name T947
Test name
Test status
Simulation time 77800652 ps
CPU time 1.22 seconds
Started Oct 15 11:29:03 AM UTC 24
Finished Oct 15 11:29:13 AM UTC 24
Peak memory 227860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602754146 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 282.edn_genbits.2602754146
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/282.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/283.edn_genbits.3365768622
Short name T925
Test name
Test status
Simulation time 50155247 ps
CPU time 1.04 seconds
Started Oct 15 11:29:04 AM UTC 24
Finished Oct 15 11:29:07 AM UTC 24
Peak memory 229900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365768622 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 283.edn_genbits.3365768622
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/283.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/284.edn_genbits.1143965076
Short name T928
Test name
Test status
Simulation time 77596150 ps
CPU time 1.25 seconds
Started Oct 15 11:29:04 AM UTC 24
Finished Oct 15 11:29:07 AM UTC 24
Peak memory 229908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143965076 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 284.edn_genbits.1143965076
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/284.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/285.edn_genbits.2912519700
Short name T929
Test name
Test status
Simulation time 57651615 ps
CPU time 1.28 seconds
Started Oct 15 11:29:04 AM UTC 24
Finished Oct 15 11:29:07 AM UTC 24
Peak memory 230124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912519700 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 285.edn_genbits.2912519700
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/285.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/286.edn_genbits.1366046987
Short name T931
Test name
Test status
Simulation time 50748598 ps
CPU time 1.21 seconds
Started Oct 15 11:29:04 AM UTC 24
Finished Oct 15 11:29:08 AM UTC 24
Peak memory 232188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366046987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 286.edn_genbits.1366046987
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/286.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/287.edn_genbits.2178226351
Short name T935
Test name
Test status
Simulation time 34599652 ps
CPU time 1.42 seconds
Started Oct 15 11:29:04 AM UTC 24
Finished Oct 15 11:29:08 AM UTC 24
Peak memory 229952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178226351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 287.edn_genbits.2178226351
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/287.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/288.edn_genbits.1150032681
Short name T927
Test name
Test status
Simulation time 83001147 ps
CPU time 1.02 seconds
Started Oct 15 11:29:04 AM UTC 24
Finished Oct 15 11:29:07 AM UTC 24
Peak memory 229908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150032681 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 288.edn_genbits.1150032681
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/288.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/289.edn_genbits.202270771
Short name T926
Test name
Test status
Simulation time 66154579 ps
CPU time 0.91 seconds
Started Oct 15 11:29:05 AM UTC 24
Finished Oct 15 11:29:07 AM UTC 24
Peak memory 229908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202270771 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 289.edn_genbits.202270771
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/289.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/29.edn_alert.958448447
Short name T191
Test name
Test status
Simulation time 25705447 ps
CPU time 1.75 seconds
Started Oct 15 11:26:21 AM UTC 24
Finished Oct 15 11:26:24 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958448447 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 29.edn_alert.958448447
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/29.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/29.edn_alert_test.359741109
Short name T450
Test name
Test status
Simulation time 22932892 ps
CPU time 1.29 seconds
Started Oct 15 11:26:22 AM UTC 24
Finished Oct 15 11:26:25 AM UTC 24
Peak memory 228636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359741109 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.359741109
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/29.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/29.edn_disable.1491521959
Short name T224
Test name
Test status
Simulation time 21783180 ps
CPU time 1.26 seconds
Started Oct 15 11:26:22 AM UTC 24
Finished Oct 15 11:26:25 AM UTC 24
Peak memory 227716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491521959 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.1491521959
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/29.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/29.edn_disable_auto_req_mode.3462662981
Short name T452
Test name
Test status
Simulation time 49443542 ps
CPU time 1.68 seconds
Started Oct 15 11:26:22 AM UTC 24
Finished Oct 15 11:26:25 AM UTC 24
Peak memory 231956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462662981 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable_auto_req_mode.3462662981
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/29.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/29.edn_err.1094433901
Short name T178
Test name
Test status
Simulation time 17928833 ps
CPU time 1.69 seconds
Started Oct 15 11:26:22 AM UTC 24
Finished Oct 15 11:26:25 AM UTC 24
Peak memory 238444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094433901 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 29.edn_err.1094433901
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/29.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/29.edn_genbits.1527829197
Short name T304
Test name
Test status
Simulation time 45107561 ps
CPU time 1.77 seconds
Started Oct 15 11:26:20 AM UTC 24
Finished Oct 15 11:26:23 AM UTC 24
Peak memory 227848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527829197 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_genbits.1527829197
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/29.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/29.edn_intr.2708897599
Short name T448
Test name
Test status
Simulation time 21721165 ps
CPU time 1.64 seconds
Started Oct 15 11:26:21 AM UTC 24
Finished Oct 15 11:26:24 AM UTC 24
Peak memory 227928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708897599 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 29.edn_intr.2708897599
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/29.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/29.edn_smoke.1083143415
Short name T447
Test name
Test status
Simulation time 25523365 ps
CPU time 1.36 seconds
Started Oct 15 11:26:20 AM UTC 24
Finished Oct 15 11:26:22 AM UTC 24
Peak memory 227864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083143415 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 29.edn_smoke.1083143415
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/29.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/29.edn_stress_all.1401886278
Short name T449
Test name
Test status
Simulation time 351308068 ps
CPU time 2.86 seconds
Started Oct 15 11:26:20 AM UTC 24
Finished Oct 15 11:26:24 AM UTC 24
Peak memory 228964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401886278 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.1401886278
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/29.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/290.edn_genbits.2590174997
Short name T959
Test name
Test status
Simulation time 336714915 ps
CPU time 3.15 seconds
Started Oct 15 11:29:07 AM UTC 24
Finished Oct 15 11:29:15 AM UTC 24
Peak memory 233072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590174997 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 290.edn_genbits.2590174997
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/290.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/291.edn_genbits.2564713499
Short name T955
Test name
Test status
Simulation time 35486040 ps
CPU time 1.32 seconds
Started Oct 15 11:29:08 AM UTC 24
Finished Oct 15 11:29:14 AM UTC 24
Peak memory 227844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564713499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 291.edn_genbits.2564713499
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/291.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/292.edn_genbits.382430245
Short name T956
Test name
Test status
Simulation time 77772622 ps
CPU time 1.11 seconds
Started Oct 15 11:29:08 AM UTC 24
Finished Oct 15 11:29:14 AM UTC 24
Peak memory 229908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382430245 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 292.edn_genbits.382430245
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/292.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/293.edn_genbits.1897230220
Short name T957
Test name
Test status
Simulation time 81621391 ps
CPU time 1.17 seconds
Started Oct 15 11:29:09 AM UTC 24
Finished Oct 15 11:29:14 AM UTC 24
Peak memory 229704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897230220 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 293.edn_genbits.1897230220
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/293.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/294.edn_genbits.3926511284
Short name T962
Test name
Test status
Simulation time 210987373 ps
CPU time 2.67 seconds
Started Oct 15 11:29:09 AM UTC 24
Finished Oct 15 11:29:16 AM UTC 24
Peak memory 233032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926511284 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 294.edn_genbits.3926511284
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/294.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/295.edn_genbits.2956021568
Short name T960
Test name
Test status
Simulation time 52543038 ps
CPU time 1.58 seconds
Started Oct 15 11:29:09 AM UTC 24
Finished Oct 15 11:29:15 AM UTC 24
Peak memory 230104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956021568 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 295.edn_genbits.2956021568
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/295.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/296.edn_genbits.343084489
Short name T941
Test name
Test status
Simulation time 51196837 ps
CPU time 1.02 seconds
Started Oct 15 11:29:09 AM UTC 24
Finished Oct 15 11:29:12 AM UTC 24
Peak memory 229904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343084489 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 296.edn_genbits.343084489
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/296.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/297.edn_genbits.1918320921
Short name T942
Test name
Test status
Simulation time 52755510 ps
CPU time 1.11 seconds
Started Oct 15 11:29:09 AM UTC 24
Finished Oct 15 11:29:12 AM UTC 24
Peak memory 227848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918320921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 297.edn_genbits.1918320921
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/297.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/298.edn_genbits.157768553
Short name T943
Test name
Test status
Simulation time 39911667 ps
CPU time 1.17 seconds
Started Oct 15 11:29:09 AM UTC 24
Finished Oct 15 11:29:12 AM UTC 24
Peak memory 227860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157768553 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 298.edn_genbits.157768553
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/298.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/299.edn_genbits.2694838041
Short name T945
Test name
Test status
Simulation time 68694253 ps
CPU time 1.31 seconds
Started Oct 15 11:29:09 AM UTC 24
Finished Oct 15 11:29:12 AM UTC 24
Peak memory 230104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694838041 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 299.edn_genbits.2694838041
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/299.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/3.edn_alert.3046880805
Short name T54
Test name
Test status
Simulation time 23513089 ps
CPU time 1.7 seconds
Started Oct 15 11:25:03 AM UTC 24
Finished Oct 15 11:25:06 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046880805 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 3.edn_alert.3046880805
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/3.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/3.edn_alert_test.4185148583
Short name T362
Test name
Test status
Simulation time 14388790 ps
CPU time 1.34 seconds
Started Oct 15 11:25:05 AM UTC 24
Finished Oct 15 11:25:08 AM UTC 24
Peak memory 218156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185148583 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.4185148583
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/3.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/3.edn_disable.784862965
Short name T51
Test name
Test status
Simulation time 34829893 ps
CPU time 1.11 seconds
Started Oct 15 11:25:04 AM UTC 24
Finished Oct 15 11:25:06 AM UTC 24
Peak memory 227976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784862965 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.784862965
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/3.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/3.edn_err.511294307
Short name T7
Test name
Test status
Simulation time 25171480 ps
CPU time 1.63 seconds
Started Oct 15 11:25:04 AM UTC 24
Finished Oct 15 11:25:07 AM UTC 24
Peak memory 248284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511294307 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 3.edn_err.511294307
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/3.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/3.edn_intr.4286278181
Short name T73
Test name
Test status
Simulation time 54118300 ps
CPU time 1.26 seconds
Started Oct 15 11:25:03 AM UTC 24
Finished Oct 15 11:25:05 AM UTC 24
Peak memory 227980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286278181 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 3.edn_intr.4286278181
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/3.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/3.edn_regwen.3556298654
Short name T92
Test name
Test status
Simulation time 111038752 ps
CPU time 1.29 seconds
Started Oct 15 11:25:01 AM UTC 24
Finished Oct 15 11:25:03 AM UTC 24
Peak memory 217760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556298654 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 3.edn_regwen.3556298654
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/3.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/3.edn_sec_cm.981578703
Short name T63
Test name
Test status
Simulation time 1026061937 ps
CPU time 12.1 seconds
Started Oct 15 11:25:04 AM UTC 24
Finished Oct 15 11:25:17 AM UTC 24
Peak memory 263788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981578703 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.981578703
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/3.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/3.edn_smoke.1957532911
Short name T93
Test name
Test status
Simulation time 36172608 ps
CPU time 1.41 seconds
Started Oct 15 11:25:01 AM UTC 24
Finished Oct 15 11:25:03 AM UTC 24
Peak memory 227852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957532911 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 3.edn_smoke.1957532911
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/3.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/3.edn_stress_all_with_rand_reset.2677513770
Short name T559
Test name
Test status
Simulation time 4932913568 ps
CPU time 127.4 seconds
Started Oct 15 11:25:02 AM UTC 24
Finished Oct 15 11:27:12 AM UTC 24
Peak memory 231308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2677513770 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_
with_rand_reset.2677513770
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/3.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/30.edn_alert.3069950628
Short name T81
Test name
Test status
Simulation time 42776807 ps
CPU time 1.77 seconds
Started Oct 15 11:26:25 AM UTC 24
Finished Oct 15 11:26:28 AM UTC 24
Peak memory 231984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069950628 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 30.edn_alert.3069950628
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/30.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/30.edn_alert_test.2794871813
Short name T454
Test name
Test status
Simulation time 37755035 ps
CPU time 1.13 seconds
Started Oct 15 11:26:26 AM UTC 24
Finished Oct 15 11:26:28 AM UTC 24
Peak memory 228512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794871813 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.2794871813
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/30.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/30.edn_disable.2377606297
Short name T189
Test name
Test status
Simulation time 11805808 ps
CPU time 0.99 seconds
Started Oct 15 11:26:26 AM UTC 24
Finished Oct 15 11:26:28 AM UTC 24
Peak memory 228036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377606297 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.2377606297
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/30.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/30.edn_disable_auto_req_mode.3017891410
Short name T455
Test name
Test status
Simulation time 145053983 ps
CPU time 1.28 seconds
Started Oct 15 11:26:26 AM UTC 24
Finished Oct 15 11:26:28 AM UTC 24
Peak memory 231944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017891410 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable_auto_req_mode.3017891410
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/30.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/30.edn_err.1968096839
Short name T141
Test name
Test status
Simulation time 20179219 ps
CPU time 1.23 seconds
Started Oct 15 11:26:25 AM UTC 24
Finished Oct 15 11:26:27 AM UTC 24
Peak memory 231960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968096839 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 30.edn_err.1968096839
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/30.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/30.edn_genbits.4143119290
Short name T99
Test name
Test status
Simulation time 55477643 ps
CPU time 1.7 seconds
Started Oct 15 11:26:22 AM UTC 24
Finished Oct 15 11:26:25 AM UTC 24
Peak memory 229896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143119290 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_genbits.4143119290
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/30.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/30.edn_intr.1693713022
Short name T32
Test name
Test status
Simulation time 19917688 ps
CPU time 1.47 seconds
Started Oct 15 11:26:25 AM UTC 24
Finished Oct 15 11:26:27 AM UTC 24
Peak memory 230216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693713022 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 30.edn_intr.1693713022
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/30.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/30.edn_smoke.1799219080
Short name T451
Test name
Test status
Simulation time 16461635 ps
CPU time 1.48 seconds
Started Oct 15 11:26:22 AM UTC 24
Finished Oct 15 11:26:25 AM UTC 24
Peak memory 217620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799219080 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 30.edn_smoke.1799219080
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/30.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/30.edn_stress_all.2067597956
Short name T453
Test name
Test status
Simulation time 213673116 ps
CPU time 2.83 seconds
Started Oct 15 11:26:24 AM UTC 24
Finished Oct 15 11:26:27 AM UTC 24
Peak memory 231280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067597956 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.2067597956
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/30.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/30.edn_stress_all_with_rand_reset.3780039180
Short name T553
Test name
Test status
Simulation time 1624017985 ps
CPU time 44.39 seconds
Started Oct 15 11:26:24 AM UTC 24
Finished Oct 15 11:27:09 AM UTC 24
Peak memory 231304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3780039180 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all
_with_rand_reset.3780039180
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/30.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/31.edn_alert.3660253339
Short name T317
Test name
Test status
Simulation time 51800523 ps
CPU time 1.7 seconds
Started Oct 15 11:26:28 AM UTC 24
Finished Oct 15 11:26:31 AM UTC 24
Peak memory 227980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660253339 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 31.edn_alert.3660253339
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/31.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/31.edn_alert_test.804000041
Short name T458
Test name
Test status
Simulation time 17218232 ps
CPU time 1.43 seconds
Started Oct 15 11:26:29 AM UTC 24
Finished Oct 15 11:26:31 AM UTC 24
Peak memory 217852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804000041 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.804000041
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/31.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/31.edn_disable.3231724693
Short name T457
Test name
Test status
Simulation time 17862121 ps
CPU time 1.24 seconds
Started Oct 15 11:26:28 AM UTC 24
Finished Oct 15 11:26:31 AM UTC 24
Peak memory 227916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231724693 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.3231724693
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/31.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/31.edn_disable_auto_req_mode.2859410726
Short name T459
Test name
Test status
Simulation time 36064872 ps
CPU time 1.52 seconds
Started Oct 15 11:26:28 AM UTC 24
Finished Oct 15 11:26:31 AM UTC 24
Peak memory 231956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859410726 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable_auto_req_mode.2859410726
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/31.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/31.edn_err.2086033580
Short name T206
Test name
Test status
Simulation time 25407571 ps
CPU time 1.17 seconds
Started Oct 15 11:26:28 AM UTC 24
Finished Oct 15 11:26:31 AM UTC 24
Peak memory 229912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086033580 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 31.edn_err.2086033580
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/31.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/31.edn_genbits.1975447139
Short name T100
Test name
Test status
Simulation time 149864921 ps
CPU time 1.63 seconds
Started Oct 15 11:26:26 AM UTC 24
Finished Oct 15 11:26:29 AM UTC 24
Peak memory 229892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975447139 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_genbits.1975447139
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/31.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/31.edn_intr.3073410876
Short name T460
Test name
Test status
Simulation time 21942921 ps
CPU time 1.64 seconds
Started Oct 15 11:26:28 AM UTC 24
Finished Oct 15 11:26:31 AM UTC 24
Peak memory 228108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073410876 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 31.edn_intr.3073410876
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/31.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/31.edn_smoke.2732529167
Short name T456
Test name
Test status
Simulation time 75569502 ps
CPU time 1.18 seconds
Started Oct 15 11:26:26 AM UTC 24
Finished Oct 15 11:26:28 AM UTC 24
Peak memory 227864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732529167 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 31.edn_smoke.2732529167
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/31.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/31.edn_stress_all.922384611
Short name T337
Test name
Test status
Simulation time 449563685 ps
CPU time 4.05 seconds
Started Oct 15 11:26:26 AM UTC 24
Finished Oct 15 11:26:31 AM UTC 24
Peak memory 229404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922384611 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.922384611
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/31.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/32.edn_alert.2215651566
Short name T186
Test name
Test status
Simulation time 52914955 ps
CPU time 1.65 seconds
Started Oct 15 11:26:30 AM UTC 24
Finished Oct 15 11:26:33 AM UTC 24
Peak memory 232080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215651566 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 32.edn_alert.2215651566
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/32.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/32.edn_alert_test.4081891888
Short name T466
Test name
Test status
Simulation time 31753127 ps
CPU time 1.67 seconds
Started Oct 15 11:26:32 AM UTC 24
Finished Oct 15 11:26:35 AM UTC 24
Peak memory 217852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081891888 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.4081891888
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/32.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/32.edn_disable.788647551
Short name T463
Test name
Test status
Simulation time 15151800 ps
CPU time 1.44 seconds
Started Oct 15 11:26:32 AM UTC 24
Finished Oct 15 11:26:35 AM UTC 24
Peak memory 227976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788647551 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.788647551
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/32.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/32.edn_disable_auto_req_mode.1106760327
Short name T465
Test name
Test status
Simulation time 24137056 ps
CPU time 1.61 seconds
Started Oct 15 11:26:32 AM UTC 24
Finished Oct 15 11:26:35 AM UTC 24
Peak memory 227852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106760327 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable_auto_req_mode.1106760327
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/32.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/32.edn_err.3695158251
Short name T315
Test name
Test status
Simulation time 19103835 ps
CPU time 1.22 seconds
Started Oct 15 11:26:31 AM UTC 24
Finished Oct 15 11:26:33 AM UTC 24
Peak memory 229912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695158251 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 32.edn_err.3695158251
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/32.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/32.edn_genbits.2836176967
Short name T325
Test name
Test status
Simulation time 76936691 ps
CPU time 2.37 seconds
Started Oct 15 11:26:30 AM UTC 24
Finished Oct 15 11:26:33 AM UTC 24
Peak memory 231084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836176967 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_genbits.2836176967
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/32.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/32.edn_intr.1515818859
Short name T462
Test name
Test status
Simulation time 48256310 ps
CPU time 1.13 seconds
Started Oct 15 11:26:30 AM UTC 24
Finished Oct 15 11:26:32 AM UTC 24
Peak memory 238312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515818859 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 32.edn_intr.1515818859
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/32.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/32.edn_smoke.214841571
Short name T461
Test name
Test status
Simulation time 18137020 ps
CPU time 1.48 seconds
Started Oct 15 11:26:29 AM UTC 24
Finished Oct 15 11:26:31 AM UTC 24
Peak memory 227860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214841571 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 32.edn_smoke.214841571
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/32.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/33.edn_alert.3143414553
Short name T468
Test name
Test status
Simulation time 55546041 ps
CPU time 1.79 seconds
Started Oct 15 11:26:33 AM UTC 24
Finished Oct 15 11:26:36 AM UTC 24
Peak memory 227984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143414553 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 33.edn_alert.3143414553
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/33.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/33.edn_alert_test.1395384800
Short name T472
Test name
Test status
Simulation time 12952284 ps
CPU time 1.28 seconds
Started Oct 15 11:26:36 AM UTC 24
Finished Oct 15 11:26:38 AM UTC 24
Peak memory 217768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395384800 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.1395384800
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/33.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/33.edn_disable_auto_req_mode.893879067
Short name T471
Test name
Test status
Simulation time 352244592 ps
CPU time 1.15 seconds
Started Oct 15 11:26:36 AM UTC 24
Finished Oct 15 11:26:38 AM UTC 24
Peak memory 227844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893879067 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable_auto_req_mode.893879067
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/33.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/33.edn_err.3006714872
Short name T469
Test name
Test status
Simulation time 36717239 ps
CPU time 1.26 seconds
Started Oct 15 11:26:34 AM UTC 24
Finished Oct 15 11:26:37 AM UTC 24
Peak memory 230272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006714872 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 33.edn_err.3006714872
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/33.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/33.edn_genbits.912224453
Short name T101
Test name
Test status
Simulation time 120948386 ps
CPU time 2.88 seconds
Started Oct 15 11:26:32 AM UTC 24
Finished Oct 15 11:26:36 AM UTC 24
Peak memory 233080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912224453 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.edn_genbits.912224453
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/33.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/33.edn_intr.1218061860
Short name T467
Test name
Test status
Simulation time 20994025 ps
CPU time 1.51 seconds
Started Oct 15 11:26:33 AM UTC 24
Finished Oct 15 11:26:36 AM UTC 24
Peak memory 230096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218061860 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 33.edn_intr.1218061860
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/33.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/33.edn_smoke.2068734293
Short name T464
Test name
Test status
Simulation time 38221347 ps
CPU time 1.38 seconds
Started Oct 15 11:26:32 AM UTC 24
Finished Oct 15 11:26:35 AM UTC 24
Peak memory 227852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068734293 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 33.edn_smoke.2068734293
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/33.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/33.edn_stress_all.1005966827
Short name T260
Test name
Test status
Simulation time 442779894 ps
CPU time 4.59 seconds
Started Oct 15 11:26:32 AM UTC 24
Finished Oct 15 11:26:38 AM UTC 24
Peak memory 229360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005966827 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.1005966827
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/33.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/33.edn_stress_all_with_rand_reset.881785403
Short name T642
Test name
Test status
Simulation time 3054531880 ps
CPU time 66.93 seconds
Started Oct 15 11:26:32 AM UTC 24
Finished Oct 15 11:27:41 AM UTC 24
Peak memory 231360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=881785403 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_
with_rand_reset.881785403
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/33.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/34.edn_alert.3606262793
Short name T476
Test name
Test status
Simulation time 23092813 ps
CPU time 1.52 seconds
Started Oct 15 11:26:37 AM UTC 24
Finished Oct 15 11:26:40 AM UTC 24
Peak memory 230032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606262793 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 34.edn_alert.3606262793
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/34.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/34.edn_alert_test.449583041
Short name T478
Test name
Test status
Simulation time 15000687 ps
CPU time 1.37 seconds
Started Oct 15 11:26:38 AM UTC 24
Finished Oct 15 11:26:41 AM UTC 24
Peak memory 217852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449583041 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.449583041
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/34.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/34.edn_disable.1709189681
Short name T190
Test name
Test status
Simulation time 10477914 ps
CPU time 1.27 seconds
Started Oct 15 11:26:37 AM UTC 24
Finished Oct 15 11:26:39 AM UTC 24
Peak memory 228036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709189681 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.1709189681
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/34.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/34.edn_disable_auto_req_mode.2645217066
Short name T227
Test name
Test status
Simulation time 36941493 ps
CPU time 1.25 seconds
Started Oct 15 11:26:38 AM UTC 24
Finished Oct 15 11:26:40 AM UTC 24
Peak memory 227860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645217066 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable_auto_req_mode.2645217066
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/34.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/34.edn_err.2005800358
Short name T475
Test name
Test status
Simulation time 52233126 ps
CPU time 1.41 seconds
Started Oct 15 11:26:37 AM UTC 24
Finished Oct 15 11:26:39 AM UTC 24
Peak memory 231960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005800358 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 34.edn_err.2005800358
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/34.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/34.edn_intr.3114106082
Short name T474
Test name
Test status
Simulation time 35140633 ps
CPU time 1.2 seconds
Started Oct 15 11:26:37 AM UTC 24
Finished Oct 15 11:26:39 AM UTC 24
Peak memory 238312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114106082 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 34.edn_intr.3114106082
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/34.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/34.edn_smoke.2253407165
Short name T470
Test name
Test status
Simulation time 48008792 ps
CPU time 1.02 seconds
Started Oct 15 11:26:36 AM UTC 24
Finished Oct 15 11:26:38 AM UTC 24
Peak memory 217760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253407165 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 34.edn_smoke.2253407165
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/34.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/34.edn_stress_all.1870506864
Short name T473
Test name
Test status
Simulation time 39556146 ps
CPU time 1.97 seconds
Started Oct 15 11:26:36 AM UTC 24
Finished Oct 15 11:26:39 AM UTC 24
Peak memory 227848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870506864 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.1870506864
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/34.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/35.edn_alert.3240716610
Short name T482
Test name
Test status
Simulation time 27734685 ps
CPU time 1.52 seconds
Started Oct 15 11:26:40 AM UTC 24
Finished Oct 15 11:26:42 AM UTC 24
Peak memory 232068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240716610 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 35.edn_alert.3240716610
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/35.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/35.edn_alert_test.1834168777
Short name T483
Test name
Test status
Simulation time 53330488 ps
CPU time 1.2 seconds
Started Oct 15 11:26:41 AM UTC 24
Finished Oct 15 11:26:43 AM UTC 24
Peak memory 217608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834168777 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.1834168777
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/35.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/35.edn_disable.1298459525
Short name T479
Test name
Test status
Simulation time 46337940 ps
CPU time 1 seconds
Started Oct 15 11:26:40 AM UTC 24
Finished Oct 15 11:26:42 AM UTC 24
Peak memory 228036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298459525 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.1298459525
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/35.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/35.edn_disable_auto_req_mode.2320376342
Short name T143
Test name
Test status
Simulation time 33590949 ps
CPU time 1.83 seconds
Started Oct 15 11:26:41 AM UTC 24
Finished Oct 15 11:26:44 AM UTC 24
Peak memory 227848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320376342 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable_auto_req_mode.2320376342
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/35.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/35.edn_err.320214566
Short name T481
Test name
Test status
Simulation time 22024413 ps
CPU time 1.27 seconds
Started Oct 15 11:26:40 AM UTC 24
Finished Oct 15 11:26:42 AM UTC 24
Peak memory 229908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320214566 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 35.edn_err.320214566
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/35.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/35.edn_genbits.4064301811
Short name T360
Test name
Test status
Simulation time 44765915 ps
CPU time 1.91 seconds
Started Oct 15 11:26:38 AM UTC 24
Finished Oct 15 11:26:41 AM UTC 24
Peak memory 232152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064301811 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_genbits.4064301811
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/35.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/35.edn_smoke.1445051292
Short name T477
Test name
Test status
Simulation time 19059855 ps
CPU time 1.25 seconds
Started Oct 15 11:26:38 AM UTC 24
Finished Oct 15 11:26:40 AM UTC 24
Peak memory 227852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445051292 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 35.edn_smoke.1445051292
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/35.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/35.edn_stress_all.1198124683
Short name T480
Test name
Test status
Simulation time 212413175 ps
CPU time 2.33 seconds
Started Oct 15 11:26:38 AM UTC 24
Finished Oct 15 11:26:42 AM UTC 24
Peak memory 229036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198124683 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.1198124683
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/35.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/35.edn_stress_all_with_rand_reset.3914947309
Short name T749
Test name
Test status
Simulation time 27762993027 ps
CPU time 88.3 seconds
Started Oct 15 11:26:39 AM UTC 24
Finished Oct 15 11:28:10 AM UTC 24
Peak memory 231408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3914947309 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all
_with_rand_reset.3914947309
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/35.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/36.edn_alert.1105841100
Short name T486
Test name
Test status
Simulation time 24537766 ps
CPU time 1.7 seconds
Started Oct 15 11:26:42 AM UTC 24
Finished Oct 15 11:26:45 AM UTC 24
Peak memory 232080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105841100 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 36.edn_alert.1105841100
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/36.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/36.edn_alert_test.1614461595
Short name T487
Test name
Test status
Simulation time 11485947 ps
CPU time 1.12 seconds
Started Oct 15 11:26:43 AM UTC 24
Finished Oct 15 11:26:45 AM UTC 24
Peak memory 218376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614461595 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.1614461595
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/36.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/36.edn_disable.3912211671
Short name T197
Test name
Test status
Simulation time 64420519 ps
CPU time 1.22 seconds
Started Oct 15 11:26:43 AM UTC 24
Finished Oct 15 11:26:45 AM UTC 24
Peak memory 227916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912211671 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.3912211671
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/36.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/36.edn_disable_auto_req_mode.4168664758
Short name T488
Test name
Test status
Simulation time 89110332 ps
CPU time 1.51 seconds
Started Oct 15 11:26:43 AM UTC 24
Finished Oct 15 11:26:46 AM UTC 24
Peak memory 227848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168664758 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable_auto_req_mode.4168664758
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/36.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/36.edn_err.2840938271
Short name T222
Test name
Test status
Simulation time 31114133 ps
CPU time 1.74 seconds
Started Oct 15 11:26:42 AM UTC 24
Finished Oct 15 11:26:45 AM UTC 24
Peak memory 231960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840938271 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 36.edn_err.2840938271
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/36.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/36.edn_genbits.1025724498
Short name T354
Test name
Test status
Simulation time 89848063 ps
CPU time 1.5 seconds
Started Oct 15 11:26:41 AM UTC 24
Finished Oct 15 11:26:43 AM UTC 24
Peak memory 230044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025724498 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_genbits.1025724498
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/36.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/36.edn_intr.351669450
Short name T485
Test name
Test status
Simulation time 29351267 ps
CPU time 1.17 seconds
Started Oct 15 11:26:42 AM UTC 24
Finished Oct 15 11:26:44 AM UTC 24
Peak memory 230388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351669450 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 36.edn_intr.351669450
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/36.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/36.edn_smoke.1632721389
Short name T484
Test name
Test status
Simulation time 17134990 ps
CPU time 1.49 seconds
Started Oct 15 11:26:41 AM UTC 24
Finished Oct 15 11:26:43 AM UTC 24
Peak memory 227864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632721389 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 36.edn_smoke.1632721389
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/36.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/36.edn_stress_all.3457419889
Short name T261
Test name
Test status
Simulation time 101012359 ps
CPU time 2.9 seconds
Started Oct 15 11:26:41 AM UTC 24
Finished Oct 15 11:26:45 AM UTC 24
Peak memory 231088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457419889 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.3457419889
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/36.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/37.edn_alert_test.2013385862
Short name T493
Test name
Test status
Simulation time 23281639 ps
CPU time 1.38 seconds
Started Oct 15 11:26:46 AM UTC 24
Finished Oct 15 11:26:48 AM UTC 24
Peak memory 217856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013385862 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.2013385862
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/37.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/37.edn_disable.3142859520
Short name T228
Test name
Test status
Simulation time 28433492 ps
CPU time 1.21 seconds
Started Oct 15 11:26:46 AM UTC 24
Finished Oct 15 11:26:48 AM UTC 24
Peak memory 228036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142859520 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.3142859520
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/37.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/37.edn_disable_auto_req_mode.650459896
Short name T494
Test name
Test status
Simulation time 27953605 ps
CPU time 1.54 seconds
Started Oct 15 11:26:46 AM UTC 24
Finished Oct 15 11:26:48 AM UTC 24
Peak memory 227848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650459896 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable_auto_req_mode.650459896
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/37.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/37.edn_err.3709542519
Short name T492
Test name
Test status
Simulation time 23767149 ps
CPU time 1.55 seconds
Started Oct 15 11:26:45 AM UTC 24
Finished Oct 15 11:26:47 AM UTC 24
Peak memory 238248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709542519 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 37.edn_err.3709542519
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/37.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/37.edn_genbits.3620079363
Short name T490
Test name
Test status
Simulation time 139371931 ps
CPU time 1.52 seconds
Started Oct 15 11:26:43 AM UTC 24
Finished Oct 15 11:26:46 AM UTC 24
Peak memory 229904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620079363 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_genbits.3620079363
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/37.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/37.edn_intr.2679080953
Short name T491
Test name
Test status
Simulation time 34695558 ps
CPU time 1.31 seconds
Started Oct 15 11:26:45 AM UTC 24
Finished Oct 15 11:26:47 AM UTC 24
Peak memory 228108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679080953 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 37.edn_intr.2679080953
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/37.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/37.edn_smoke.3087182060
Short name T489
Test name
Test status
Simulation time 20087460 ps
CPU time 1.46 seconds
Started Oct 15 11:26:43 AM UTC 24
Finished Oct 15 11:26:46 AM UTC 24
Peak memory 227852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087182060 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 37.edn_smoke.3087182060
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/37.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/37.edn_stress_all.1808848587
Short name T499
Test name
Test status
Simulation time 2360240080 ps
CPU time 5.09 seconds
Started Oct 15 11:26:45 AM UTC 24
Finished Oct 15 11:26:51 AM UTC 24
Peak memory 229224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808848587 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.1808848587
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/37.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/38.edn_alert.704938859
Short name T144
Test name
Test status
Simulation time 53616948 ps
CPU time 1.54 seconds
Started Oct 15 11:26:47 AM UTC 24
Finished Oct 15 11:26:50 AM UTC 24
Peak memory 232076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704938859 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 38.edn_alert.704938859
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/38.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/38.edn_alert_test.135051215
Short name T502
Test name
Test status
Simulation time 27915854 ps
CPU time 1.26 seconds
Started Oct 15 11:26:48 AM UTC 24
Finished Oct 15 11:26:51 AM UTC 24
Peak memory 228576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135051215 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.135051215
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/38.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/38.edn_disable.3055808841
Short name T498
Test name
Test status
Simulation time 45554016 ps
CPU time 1.3 seconds
Started Oct 15 11:26:47 AM UTC 24
Finished Oct 15 11:26:50 AM UTC 24
Peak memory 227976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055808841 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.3055808841
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/38.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/38.edn_disable_auto_req_mode.2743744939
Short name T501
Test name
Test status
Simulation time 50906610 ps
CPU time 1.28 seconds
Started Oct 15 11:26:48 AM UTC 24
Finished Oct 15 11:26:51 AM UTC 24
Peak memory 227856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743744939 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable_auto_req_mode.2743744939
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/38.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/38.edn_err.2067918055
Short name T146
Test name
Test status
Simulation time 39516040 ps
CPU time 1.27 seconds
Started Oct 15 11:26:47 AM UTC 24
Finished Oct 15 11:26:50 AM UTC 24
Peak memory 248232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067918055 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 38.edn_err.2067918055
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/38.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/38.edn_genbits.2028874168
Short name T496
Test name
Test status
Simulation time 57382010 ps
CPU time 1.77 seconds
Started Oct 15 11:26:46 AM UTC 24
Finished Oct 15 11:26:49 AM UTC 24
Peak memory 230164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028874168 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_genbits.2028874168
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/38.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/38.edn_intr.544830395
Short name T497
Test name
Test status
Simulation time 34664016 ps
CPU time 1.2 seconds
Started Oct 15 11:26:47 AM UTC 24
Finished Oct 15 11:26:49 AM UTC 24
Peak memory 227920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544830395 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 38.edn_intr.544830395
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/38.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/38.edn_smoke.1696863412
Short name T495
Test name
Test status
Simulation time 18477174 ps
CPU time 1.42 seconds
Started Oct 15 11:26:46 AM UTC 24
Finished Oct 15 11:26:48 AM UTC 24
Peak memory 227852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696863412 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 38.edn_smoke.1696863412
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/38.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/38.edn_stress_all.2208845171
Short name T505
Test name
Test status
Simulation time 376078031 ps
CPU time 5.05 seconds
Started Oct 15 11:26:46 AM UTC 24
Finished Oct 15 11:26:52 AM UTC 24
Peak memory 231352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208845171 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.2208845171
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/38.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/38.edn_stress_all_with_rand_reset.1003068942
Short name T581
Test name
Test status
Simulation time 4785813030 ps
CPU time 30.99 seconds
Started Oct 15 11:26:46 AM UTC 24
Finished Oct 15 11:27:18 AM UTC 24
Peak memory 231328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1003068942 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all
_with_rand_reset.1003068942
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/38.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/39.edn_alert.237713717
Short name T311
Test name
Test status
Simulation time 80950392 ps
CPU time 1.81 seconds
Started Oct 15 11:26:50 AM UTC 24
Finished Oct 15 11:26:53 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237713717 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 39.edn_alert.237713717
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/39.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/39.edn_alert_test.551406941
Short name T510
Test name
Test status
Simulation time 47224931 ps
CPU time 1.25 seconds
Started Oct 15 11:26:51 AM UTC 24
Finished Oct 15 11:26:53 AM UTC 24
Peak memory 217852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551406941 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.551406941
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/39.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/39.edn_disable.982637073
Short name T504
Test name
Test status
Simulation time 19024199 ps
CPU time 1.12 seconds
Started Oct 15 11:26:50 AM UTC 24
Finished Oct 15 11:26:52 AM UTC 24
Peak memory 227916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982637073 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.982637073
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/39.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/39.edn_disable_auto_req_mode.1802435393
Short name T511
Test name
Test status
Simulation time 141167557 ps
CPU time 1.65 seconds
Started Oct 15 11:26:51 AM UTC 24
Finished Oct 15 11:26:54 AM UTC 24
Peak memory 227844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802435393 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable_auto_req_mode.1802435393
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/39.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/39.edn_err.3396014746
Short name T503
Test name
Test status
Simulation time 20755436 ps
CPU time 1.2 seconds
Started Oct 15 11:26:50 AM UTC 24
Finished Oct 15 11:26:52 AM UTC 24
Peak memory 238624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396014746 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 39.edn_err.3396014746
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/39.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/39.edn_genbits.2580463991
Short name T506
Test name
Test status
Simulation time 70743243 ps
CPU time 2.65 seconds
Started Oct 15 11:26:49 AM UTC 24
Finished Oct 15 11:26:52 AM UTC 24
Peak memory 231076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580463991 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_genbits.2580463991
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/39.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/39.edn_intr.21776153
Short name T507
Test name
Test status
Simulation time 55878051 ps
CPU time 1.47 seconds
Started Oct 15 11:26:50 AM UTC 24
Finished Oct 15 11:26:52 AM UTC 24
Peak memory 238304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21776153 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_in
tr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 39.edn_intr.21776153
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/39.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/39.edn_smoke.1919126978
Short name T500
Test name
Test status
Simulation time 18611931 ps
CPU time 1.18 seconds
Started Oct 15 11:26:49 AM UTC 24
Finished Oct 15 11:26:51 AM UTC 24
Peak memory 227848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919126978 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 39.edn_smoke.1919126978
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/39.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/39.edn_stress_all.3415081255
Short name T513
Test name
Test status
Simulation time 442539754 ps
CPU time 5.84 seconds
Started Oct 15 11:26:49 AM UTC 24
Finished Oct 15 11:26:56 AM UTC 24
Peak memory 229052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415081255 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.3415081255
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/39.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/39.edn_stress_all_with_rand_reset.1581722424
Short name T668
Test name
Test status
Simulation time 7594739948 ps
CPU time 56.23 seconds
Started Oct 15 11:26:50 AM UTC 24
Finished Oct 15 11:27:48 AM UTC 24
Peak memory 231668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1581722424 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all
_with_rand_reset.1581722424
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/39.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/4.edn_alert.686636358
Short name T56
Test name
Test status
Simulation time 22952621 ps
CPU time 1.78 seconds
Started Oct 15 11:25:08 AM UTC 24
Finished Oct 15 11:25:11 AM UTC 24
Peak memory 231656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686636358 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 4.edn_alert.686636358
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/4.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/4.edn_alert_test.4089529992
Short name T363
Test name
Test status
Simulation time 220877916 ps
CPU time 1.47 seconds
Started Oct 15 11:25:10 AM UTC 24
Finished Oct 15 11:25:12 AM UTC 24
Peak memory 228520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089529992 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.4089529992
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/4.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/4.edn_disable.4099641886
Short name T55
Test name
Test status
Simulation time 11627447 ps
CPU time 1.31 seconds
Started Oct 15 11:25:09 AM UTC 24
Finished Oct 15 11:25:11 AM UTC 24
Peak memory 228104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099641886 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.4099641886
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/4.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/4.edn_disable_auto_req_mode.1748374827
Short name T20
Test name
Test status
Simulation time 39673995 ps
CPU time 1.55 seconds
Started Oct 15 11:25:10 AM UTC 24
Finished Oct 15 11:25:12 AM UTC 24
Peak memory 231952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748374827 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable_auto_req_mode.1748374827
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/4.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/4.edn_err.3218076163
Short name T62
Test name
Test status
Simulation time 39546896 ps
CPU time 1.45 seconds
Started Oct 15 11:25:08 AM UTC 24
Finished Oct 15 11:25:10 AM UTC 24
Peak memory 238428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218076163 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 4.edn_err.3218076163
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/4.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/4.edn_genbits.2147255802
Short name T21
Test name
Test status
Simulation time 79901295 ps
CPU time 1.77 seconds
Started Oct 15 11:25:06 AM UTC 24
Finished Oct 15 11:25:09 AM UTC 24
Peak memory 229892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147255802 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_genbits.2147255802
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/4.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/4.edn_intr.2347917088
Short name T215
Test name
Test status
Simulation time 23220953 ps
CPU time 1.63 seconds
Started Oct 15 11:25:08 AM UTC 24
Finished Oct 15 11:25:10 AM UTC 24
Peak memory 227460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347917088 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 4.edn_intr.2347917088
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/4.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/4.edn_regwen.60579915
Short name T126
Test name
Test status
Simulation time 37504333 ps
CPU time 1.29 seconds
Started Oct 15 11:25:06 AM UTC 24
Finished Oct 15 11:25:09 AM UTC 24
Peak memory 217616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60579915 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 4.edn_regwen.60579915
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/4.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/4.edn_sec_cm.1455312982
Short name T64
Test name
Test status
Simulation time 444972681 ps
CPU time 7.24 seconds
Started Oct 15 11:25:10 AM UTC 24
Finished Oct 15 11:25:18 AM UTC 24
Peak memory 261692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455312982 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.1455312982
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/4.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/4.edn_smoke.2028266287
Short name T361
Test name
Test status
Simulation time 14044627 ps
CPU time 1.16 seconds
Started Oct 15 11:25:06 AM UTC 24
Finished Oct 15 11:25:09 AM UTC 24
Peak memory 227860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028266287 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 4.edn_smoke.2028266287
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/4.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/4.edn_stress_all.3463509756
Short name T127
Test name
Test status
Simulation time 151497717 ps
CPU time 3.71 seconds
Started Oct 15 11:25:07 AM UTC 24
Finished Oct 15 11:25:11 AM UTC 24
Peak memory 229088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463509756 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.3463509756
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/4.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/40.edn_alert.1015451153
Short name T145
Test name
Test status
Simulation time 139315662 ps
CPU time 1.3 seconds
Started Oct 15 11:26:52 AM UTC 24
Finished Oct 15 11:26:55 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015451153 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 40.edn_alert.1015451153
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/40.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/40.edn_alert_test.2893082866
Short name T517
Test name
Test status
Simulation time 13919358 ps
CPU time 1.34 seconds
Started Oct 15 11:26:54 AM UTC 24
Finished Oct 15 11:26:56 AM UTC 24
Peak memory 227928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893082866 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.2893082866
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/40.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/40.edn_disable.1563813686
Short name T508
Test name
Test status
Simulation time 80343432 ps
CPU time 1.01 seconds
Started Oct 15 11:26:53 AM UTC 24
Finished Oct 15 11:26:55 AM UTC 24
Peak memory 227916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563813686 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.1563813686
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/40.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/40.edn_disable_auto_req_mode.575536651
Short name T515
Test name
Test status
Simulation time 23763439 ps
CPU time 1.31 seconds
Started Oct 15 11:26:54 AM UTC 24
Finished Oct 15 11:26:56 AM UTC 24
Peak memory 230148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575536651 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable_auto_req_mode.575536651
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/40.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/40.edn_err.907079889
Short name T516
Test name
Test status
Simulation time 35630441 ps
CPU time 1.49 seconds
Started Oct 15 11:26:53 AM UTC 24
Finished Oct 15 11:26:56 AM UTC 24
Peak memory 229908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907079889 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 40.edn_err.907079889
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/40.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/40.edn_genbits.1077436943
Short name T519
Test name
Test status
Simulation time 237019910 ps
CPU time 4.94 seconds
Started Oct 15 11:26:51 AM UTC 24
Finished Oct 15 11:26:57 AM UTC 24
Peak memory 231332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077436943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_genbits.1077436943
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/40.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/40.edn_intr.3386336900
Short name T512
Test name
Test status
Simulation time 23911936 ps
CPU time 1.27 seconds
Started Oct 15 11:26:52 AM UTC 24
Finished Oct 15 11:26:55 AM UTC 24
Peak memory 230156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386336900 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 40.edn_intr.3386336900
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/40.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/40.edn_smoke.1114687422
Short name T509
Test name
Test status
Simulation time 23573279 ps
CPU time 1.01 seconds
Started Oct 15 11:26:51 AM UTC 24
Finished Oct 15 11:26:53 AM UTC 24
Peak memory 227852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114687422 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 40.edn_smoke.1114687422
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/40.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/40.edn_stress_all.973682643
Short name T524
Test name
Test status
Simulation time 205339429 ps
CPU time 6.12 seconds
Started Oct 15 11:26:52 AM UTC 24
Finished Oct 15 11:26:59 AM UTC 24
Peak memory 228792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973682643 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.973682643
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/40.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/40.edn_stress_all_with_rand_reset.2744570245
Short name T753
Test name
Test status
Simulation time 3128846938 ps
CPU time 78.12 seconds
Started Oct 15 11:26:52 AM UTC 24
Finished Oct 15 11:28:12 AM UTC 24
Peak memory 233096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2744570245 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all
_with_rand_reset.2744570245
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/40.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/41.edn_alert_test.1057893454
Short name T523
Test name
Test status
Simulation time 27795805 ps
CPU time 1.15 seconds
Started Oct 15 11:26:57 AM UTC 24
Finished Oct 15 11:26:59 AM UTC 24
Peak memory 217852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057893454 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.1057893454
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/41.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/41.edn_disable.3222899324
Short name T229
Test name
Test status
Simulation time 31939987 ps
CPU time 1.28 seconds
Started Oct 15 11:26:56 AM UTC 24
Finished Oct 15 11:26:58 AM UTC 24
Peak memory 227976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222899324 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.3222899324
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/41.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/41.edn_disable_auto_req_mode.2296191290
Short name T522
Test name
Test status
Simulation time 70703813 ps
CPU time 1.9 seconds
Started Oct 15 11:26:56 AM UTC 24
Finished Oct 15 11:26:59 AM UTC 24
Peak memory 227856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296191290 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable_auto_req_mode.2296191290
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/41.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/41.edn_err.347756942
Short name T521
Test name
Test status
Simulation time 41711469 ps
CPU time 1.7 seconds
Started Oct 15 11:26:56 AM UTC 24
Finished Oct 15 11:26:59 AM UTC 24
Peak memory 227860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347756942 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 41.edn_err.347756942
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/41.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/41.edn_genbits.991571840
Short name T518
Test name
Test status
Simulation time 39813086 ps
CPU time 1.86 seconds
Started Oct 15 11:26:54 AM UTC 24
Finished Oct 15 11:26:57 AM UTC 24
Peak memory 232208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991571840 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.edn_genbits.991571840
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/41.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/41.edn_intr.3862259450
Short name T520
Test name
Test status
Simulation time 26494591 ps
CPU time 1.6 seconds
Started Oct 15 11:26:55 AM UTC 24
Finished Oct 15 11:26:57 AM UTC 24
Peak memory 238312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862259450 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 41.edn_intr.3862259450
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/41.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/41.edn_smoke.1611361068
Short name T514
Test name
Test status
Simulation time 44654026 ps
CPU time 1.16 seconds
Started Oct 15 11:26:54 AM UTC 24
Finished Oct 15 11:26:56 AM UTC 24
Peak memory 227188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611361068 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 41.edn_smoke.1611361068
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/41.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/41.edn_stress_all.1381879909
Short name T525
Test name
Test status
Simulation time 363722371 ps
CPU time 4.75 seconds
Started Oct 15 11:26:54 AM UTC 24
Finished Oct 15 11:27:00 AM UTC 24
Peak memory 229416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381879909 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.1381879909
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/41.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/41.edn_stress_all_with_rand_reset.920418113
Short name T624
Test name
Test status
Simulation time 6454258695 ps
CPU time 40.26 seconds
Started Oct 15 11:26:55 AM UTC 24
Finished Oct 15 11:27:36 AM UTC 24
Peak memory 233348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=920418113 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_
with_rand_reset.920418113
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/41.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/42.edn_alert.2405257989
Short name T529
Test name
Test status
Simulation time 54928633 ps
CPU time 1.47 seconds
Started Oct 15 11:26:58 AM UTC 24
Finished Oct 15 11:27:01 AM UTC 24
Peak memory 231728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405257989 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 42.edn_alert.2405257989
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/42.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/42.edn_alert_test.510385714
Short name T532
Test name
Test status
Simulation time 22225553 ps
CPU time 1.07 seconds
Started Oct 15 11:27:00 AM UTC 24
Finished Oct 15 11:27:02 AM UTC 24
Peak memory 217892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510385714 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.510385714
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/42.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/42.edn_disable.464873367
Short name T198
Test name
Test status
Simulation time 50314158 ps
CPU time 1.29 seconds
Started Oct 15 11:27:00 AM UTC 24
Finished Oct 15 11:27:02 AM UTC 24
Peak memory 227916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464873367 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.464873367
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/42.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/42.edn_err.1341876366
Short name T531
Test name
Test status
Simulation time 24242729 ps
CPU time 1.76 seconds
Started Oct 15 11:26:59 AM UTC 24
Finished Oct 15 11:27:01 AM UTC 24
Peak memory 238444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341876366 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 42.edn_err.1341876366
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/42.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/42.edn_genbits.33342486
Short name T527
Test name
Test status
Simulation time 138280672 ps
CPU time 2.32 seconds
Started Oct 15 11:26:57 AM UTC 24
Finished Oct 15 11:27:01 AM UTC 24
Peak memory 231200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33342486 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 42.edn_genbits.33342486
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/42.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/42.edn_intr.190847139
Short name T528
Test name
Test status
Simulation time 24996691 ps
CPU time 1.42 seconds
Started Oct 15 11:26:58 AM UTC 24
Finished Oct 15 11:27:01 AM UTC 24
Peak memory 238304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190847139 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 42.edn_intr.190847139
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/42.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/42.edn_smoke.2324430925
Short name T526
Test name
Test status
Simulation time 17219003 ps
CPU time 1.19 seconds
Started Oct 15 11:26:57 AM UTC 24
Finished Oct 15 11:27:00 AM UTC 24
Peak memory 227852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324430925 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 42.edn_smoke.2324430925
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/42.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/42.edn_stress_all.399990723
Short name T533
Test name
Test status
Simulation time 111142234 ps
CPU time 3.23 seconds
Started Oct 15 11:26:57 AM UTC 24
Finished Oct 15 11:27:02 AM UTC 24
Peak memory 229152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399990723 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.399990723
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/42.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/42.edn_stress_all_with_rand_reset.2614099456
Short name T944
Test name
Test status
Simulation time 9833860306 ps
CPU time 132.26 seconds
Started Oct 15 11:26:57 AM UTC 24
Finished Oct 15 11:29:12 AM UTC 24
Peak memory 235400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2614099456 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all
_with_rand_reset.2614099456
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/42.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/43.edn_alert.3877151240
Short name T536
Test name
Test status
Simulation time 51389882 ps
CPU time 1.7 seconds
Started Oct 15 11:27:01 AM UTC 24
Finished Oct 15 11:27:04 AM UTC 24
Peak memory 227984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877151240 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 43.edn_alert.3877151240
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/43.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/43.edn_alert_test.1124695412
Short name T540
Test name
Test status
Simulation time 63372361 ps
CPU time 1.29 seconds
Started Oct 15 11:27:02 AM UTC 24
Finished Oct 15 11:27:05 AM UTC 24
Peak memory 228484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124695412 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.1124695412
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/43.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/43.edn_disable.1918849529
Short name T539
Test name
Test status
Simulation time 13670276 ps
CPU time 1.37 seconds
Started Oct 15 11:27:02 AM UTC 24
Finished Oct 15 11:27:04 AM UTC 24
Peak memory 227976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918849529 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.1918849529
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/43.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/43.edn_disable_auto_req_mode.1731710565
Short name T541
Test name
Test status
Simulation time 45533710 ps
CPU time 1.6 seconds
Started Oct 15 11:27:02 AM UTC 24
Finished Oct 15 11:27:05 AM UTC 24
Peak memory 228036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731710565 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable_auto_req_mode.1731710565
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/43.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/43.edn_err.1072481304
Short name T537
Test name
Test status
Simulation time 37304337 ps
CPU time 1.27 seconds
Started Oct 15 11:27:02 AM UTC 24
Finished Oct 15 11:27:04 AM UTC 24
Peak memory 229912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072481304 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 43.edn_err.1072481304
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/43.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/43.edn_genbits.1031521755
Short name T535
Test name
Test status
Simulation time 101662585 ps
CPU time 1.69 seconds
Started Oct 15 11:27:00 AM UTC 24
Finished Oct 15 11:27:03 AM UTC 24
Peak memory 227844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031521755 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_genbits.1031521755
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/43.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/43.edn_intr.2854425382
Short name T113
Test name
Test status
Simulation time 28807218 ps
CPU time 1.3 seconds
Started Oct 15 11:27:01 AM UTC 24
Finished Oct 15 11:27:03 AM UTC 24
Peak memory 229976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854425382 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 43.edn_intr.2854425382
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/43.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/43.edn_smoke.3297313495
Short name T534
Test name
Test status
Simulation time 50617888 ps
CPU time 1.35 seconds
Started Oct 15 11:27:00 AM UTC 24
Finished Oct 15 11:27:02 AM UTC 24
Peak memory 227852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297313495 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 43.edn_smoke.3297313495
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/43.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/43.edn_stress_all.1280666933
Short name T546
Test name
Test status
Simulation time 883664404 ps
CPU time 6.03 seconds
Started Oct 15 11:27:00 AM UTC 24
Finished Oct 15 11:27:07 AM UTC 24
Peak memory 229056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280666933 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.1280666933
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/43.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/43.edn_stress_all_with_rand_reset.1139045401
Short name T252
Test name
Test status
Simulation time 12113197248 ps
CPU time 65.65 seconds
Started Oct 15 11:27:01 AM UTC 24
Finished Oct 15 11:28:08 AM UTC 24
Peak memory 231308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1139045401 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all
_with_rand_reset.1139045401
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/43.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/44.edn_alert.575522256
Short name T163
Test name
Test status
Simulation time 158576886 ps
CPU time 1.65 seconds
Started Oct 15 11:27:04 AM UTC 24
Finished Oct 15 11:27:06 AM UTC 24
Peak memory 232076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575522256 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 44.edn_alert.575522256
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/44.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/44.edn_alert_test.842066910
Short name T548
Test name
Test status
Simulation time 28002085 ps
CPU time 1.35 seconds
Started Oct 15 11:27:06 AM UTC 24
Finished Oct 15 11:27:08 AM UTC 24
Peak memory 228552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842066910 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.842066910
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/44.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/44.edn_disable.889982117
Short name T545
Test name
Test status
Simulation time 18508033 ps
CPU time 1.27 seconds
Started Oct 15 11:27:05 AM UTC 24
Finished Oct 15 11:27:07 AM UTC 24
Peak memory 227916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889982117 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.889982117
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/44.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/44.edn_disable_auto_req_mode.41902241
Short name T550
Test name
Test status
Simulation time 91509834 ps
CPU time 1.71 seconds
Started Oct 15 11:27:06 AM UTC 24
Finished Oct 15 11:27:08 AM UTC 24
Peak memory 228056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41902241 -assert nopostproc +UVM_TESTNAME=edn_disab
le_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable_auto_req_mode.41902241
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/44.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/44.edn_err.2508347837
Short name T547
Test name
Test status
Simulation time 22781535 ps
CPU time 1.57 seconds
Started Oct 15 11:27:05 AM UTC 24
Finished Oct 15 11:27:07 AM UTC 24
Peak memory 238624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508347837 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 44.edn_err.2508347837
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/44.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/44.edn_genbits.3606217912
Short name T544
Test name
Test status
Simulation time 51981443 ps
CPU time 2.23 seconds
Started Oct 15 11:27:03 AM UTC 24
Finished Oct 15 11:27:07 AM UTC 24
Peak memory 231092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606217912 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_genbits.3606217912
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/44.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/44.edn_intr.1157986606
Short name T542
Test name
Test status
Simulation time 20944320 ps
CPU time 1.41 seconds
Started Oct 15 11:27:03 AM UTC 24
Finished Oct 15 11:27:06 AM UTC 24
Peak memory 230036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157986606 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 44.edn_intr.1157986606
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/44.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/44.edn_smoke.3974903218
Short name T538
Test name
Test status
Simulation time 24386221 ps
CPU time 1.23 seconds
Started Oct 15 11:27:02 AM UTC 24
Finished Oct 15 11:27:04 AM UTC 24
Peak memory 227848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974903218 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 44.edn_smoke.3974903218
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/44.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/44.edn_stress_all.890249986
Short name T543
Test name
Test status
Simulation time 79503959 ps
CPU time 1.88 seconds
Started Oct 15 11:27:03 AM UTC 24
Finished Oct 15 11:27:06 AM UTC 24
Peak memory 227852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890249986 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.890249986
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/44.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/44.edn_stress_all_with_rand_reset.1377920272
Short name T812
Test name
Test status
Simulation time 13234405591 ps
CPU time 84.85 seconds
Started Oct 15 11:27:03 AM UTC 24
Finished Oct 15 11:28:30 AM UTC 24
Peak memory 231228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1377920272 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all
_with_rand_reset.1377920272
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/44.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/45.edn_alert.99509590
Short name T555
Test name
Test status
Simulation time 81923019 ps
CPU time 1.76 seconds
Started Oct 15 11:27:07 AM UTC 24
Finished Oct 15 11:27:10 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99509590 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a
lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 45.edn_alert.99509590
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/45.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/45.edn_alert_test.2477068012
Short name T556
Test name
Test status
Simulation time 16839446 ps
CPU time 1.4 seconds
Started Oct 15 11:27:08 AM UTC 24
Finished Oct 15 11:27:11 AM UTC 24
Peak memory 228552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477068012 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.2477068012
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/45.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/45.edn_disable.3411940853
Short name T552
Test name
Test status
Simulation time 79923044 ps
CPU time 1.23 seconds
Started Oct 15 11:27:07 AM UTC 24
Finished Oct 15 11:27:09 AM UTC 24
Peak memory 227976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411940853 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.3411940853
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/45.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/45.edn_disable_auto_req_mode.621011269
Short name T558
Test name
Test status
Simulation time 44938698 ps
CPU time 1.75 seconds
Started Oct 15 11:27:08 AM UTC 24
Finished Oct 15 11:27:11 AM UTC 24
Peak memory 227860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621011269 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable_auto_req_mode.621011269
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/45.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/45.edn_err.1527715912
Short name T194
Test name
Test status
Simulation time 24246136 ps
CPU time 1.52 seconds
Started Oct 15 11:27:07 AM UTC 24
Finished Oct 15 11:27:10 AM UTC 24
Peak memory 238504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527715912 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 45.edn_err.1527715912
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/45.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/45.edn_genbits.672745030
Short name T551
Test name
Test status
Simulation time 36844834 ps
CPU time 2.3 seconds
Started Oct 15 11:27:06 AM UTC 24
Finished Oct 15 11:27:09 AM UTC 24
Peak memory 231104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=672745030 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.edn_genbits.672745030
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/45.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/45.edn_intr.3682169533
Short name T554
Test name
Test status
Simulation time 20912776 ps
CPU time 1.56 seconds
Started Oct 15 11:27:07 AM UTC 24
Finished Oct 15 11:27:10 AM UTC 24
Peak memory 227928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682169533 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 45.edn_intr.3682169533
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/45.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/45.edn_smoke.1802697279
Short name T549
Test name
Test status
Simulation time 16820469 ps
CPU time 1.47 seconds
Started Oct 15 11:27:06 AM UTC 24
Finished Oct 15 11:27:08 AM UTC 24
Peak memory 227852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802697279 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 45.edn_smoke.1802697279
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/45.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/45.edn_stress_all.1233344783
Short name T561
Test name
Test status
Simulation time 323222258 ps
CPU time 6.03 seconds
Started Oct 15 11:27:06 AM UTC 24
Finished Oct 15 11:27:13 AM UTC 24
Peak memory 231140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233344783 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.1233344783
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/45.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/45.edn_stress_all_with_rand_reset.166320270
Short name T734
Test name
Test status
Simulation time 8428744585 ps
CPU time 55.86 seconds
Started Oct 15 11:27:06 AM UTC 24
Finished Oct 15 11:28:03 AM UTC 24
Peak memory 231384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=166320270 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_
with_rand_reset.166320270
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/45.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/46.edn_alert.2753780175
Short name T563
Test name
Test status
Simulation time 296311590 ps
CPU time 1.44 seconds
Started Oct 15 11:27:11 AM UTC 24
Finished Oct 15 11:27:13 AM UTC 24
Peak memory 230032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753780175 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 46.edn_alert.2753780175
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/46.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/46.edn_alert_test.3594904369
Short name T566
Test name
Test status
Simulation time 31054295 ps
CPU time 1.37 seconds
Started Oct 15 11:27:11 AM UTC 24
Finished Oct 15 11:27:13 AM UTC 24
Peak memory 228516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594904369 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.3594904369
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/46.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/46.edn_disable.2426470589
Short name T562
Test name
Test status
Simulation time 33012817 ps
CPU time 1.19 seconds
Started Oct 15 11:27:11 AM UTC 24
Finished Oct 15 11:27:13 AM UTC 24
Peak memory 227824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426470589 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.2426470589
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/46.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/46.edn_disable_auto_req_mode.1106548634
Short name T565
Test name
Test status
Simulation time 99931920 ps
CPU time 1.46 seconds
Started Oct 15 11:27:11 AM UTC 24
Finished Oct 15 11:27:13 AM UTC 24
Peak memory 227856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106548634 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable_auto_req_mode.1106548634
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/46.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/46.edn_err.2868806160
Short name T142
Test name
Test status
Simulation time 100069127 ps
CPU time 1.39 seconds
Started Oct 15 11:27:11 AM UTC 24
Finished Oct 15 11:27:13 AM UTC 24
Peak memory 231960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868806160 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 46.edn_err.2868806160
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/46.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/46.edn_genbits.863445516
Short name T345
Test name
Test status
Simulation time 82927690 ps
CPU time 1.71 seconds
Started Oct 15 11:27:08 AM UTC 24
Finished Oct 15 11:27:11 AM UTC 24
Peak memory 231940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863445516 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.edn_genbits.863445516
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/46.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/46.edn_intr.2394920337
Short name T560
Test name
Test status
Simulation time 45321813 ps
CPU time 1.32 seconds
Started Oct 15 11:27:10 AM UTC 24
Finished Oct 15 11:27:12 AM UTC 24
Peak memory 228108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394920337 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 46.edn_intr.2394920337
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/46.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/46.edn_smoke.1430353835
Short name T557
Test name
Test status
Simulation time 17354447 ps
CPU time 1.45 seconds
Started Oct 15 11:27:08 AM UTC 24
Finished Oct 15 11:27:11 AM UTC 24
Peak memory 227852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430353835 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 46.edn_smoke.1430353835
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/46.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/46.edn_stress_all.3573026115
Short name T567
Test name
Test status
Simulation time 517248713 ps
CPU time 3.58 seconds
Started Oct 15 11:27:09 AM UTC 24
Finished Oct 15 11:27:14 AM UTC 24
Peak memory 233256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573026115 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.3573026115
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/46.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/46.edn_stress_all_with_rand_reset.338072390
Short name T800
Test name
Test status
Simulation time 5519002167 ps
CPU time 74.64 seconds
Started Oct 15 11:27:10 AM UTC 24
Finished Oct 15 11:28:26 AM UTC 24
Peak memory 231300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=338072390 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_
with_rand_reset.338072390
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/46.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/47.edn_alert.2048077197
Short name T571
Test name
Test status
Simulation time 45032858 ps
CPU time 1.73 seconds
Started Oct 15 11:27:12 AM UTC 24
Finished Oct 15 11:27:15 AM UTC 24
Peak memory 230032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048077197 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 47.edn_alert.2048077197
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/47.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/47.edn_alert_test.4165394221
Short name T575
Test name
Test status
Simulation time 21089377 ps
CPU time 1.24 seconds
Started Oct 15 11:27:14 AM UTC 24
Finished Oct 15 11:27:17 AM UTC 24
Peak memory 228612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165394221 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.4165394221
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/47.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/47.edn_disable.3254964825
Short name T572
Test name
Test status
Simulation time 17381758 ps
CPU time 1.13 seconds
Started Oct 15 11:27:13 AM UTC 24
Finished Oct 15 11:27:15 AM UTC 24
Peak memory 228096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254964825 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.3254964825
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/47.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/47.edn_disable_auto_req_mode.1436010821
Short name T574
Test name
Test status
Simulation time 33746349 ps
CPU time 1.8 seconds
Started Oct 15 11:27:13 AM UTC 24
Finished Oct 15 11:27:16 AM UTC 24
Peak memory 229896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436010821 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable_auto_req_mode.1436010821
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/47.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/47.edn_err.2979029135
Short name T573
Test name
Test status
Simulation time 19805889 ps
CPU time 1.45 seconds
Started Oct 15 11:27:13 AM UTC 24
Finished Oct 15 11:27:16 AM UTC 24
Peak memory 229912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979029135 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 47.edn_err.2979029135
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/47.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/47.edn_genbits.637068854
Short name T570
Test name
Test status
Simulation time 105840028 ps
CPU time 1.82 seconds
Started Oct 15 11:27:12 AM UTC 24
Finished Oct 15 11:27:15 AM UTC 24
Peak memory 229896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637068854 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.edn_genbits.637068854
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/47.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/47.edn_intr.920802679
Short name T569
Test name
Test status
Simulation time 21423329 ps
CPU time 1.6 seconds
Started Oct 15 11:27:12 AM UTC 24
Finished Oct 15 11:27:15 AM UTC 24
Peak memory 228160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920802679 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 47.edn_intr.920802679
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/47.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/47.edn_smoke.198209393
Short name T564
Test name
Test status
Simulation time 58361552 ps
CPU time 1.39 seconds
Started Oct 15 11:27:11 AM UTC 24
Finished Oct 15 11:27:13 AM UTC 24
Peak memory 227848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198209393 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 47.edn_smoke.198209393
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/47.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/47.edn_stress_all.334254869
Short name T324
Test name
Test status
Simulation time 225124476 ps
CPU time 3.4 seconds
Started Oct 15 11:27:12 AM UTC 24
Finished Oct 15 11:27:17 AM UTC 24
Peak memory 233208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334254869 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.334254869
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/47.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/48.edn_alert.1794040505
Short name T582
Test name
Test status
Simulation time 107085185 ps
CPU time 1.87 seconds
Started Oct 15 11:27:16 AM UTC 24
Finished Oct 15 11:27:19 AM UTC 24
Peak memory 231844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794040505 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 48.edn_alert.1794040505
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/48.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/48.edn_alert_test.583545716
Short name T580
Test name
Test status
Simulation time 45386239 ps
CPU time 1.27 seconds
Started Oct 15 11:27:16 AM UTC 24
Finished Oct 15 11:27:18 AM UTC 24
Peak memory 228636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583545716 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.583545716
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/48.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/48.edn_disable.1748543620
Short name T578
Test name
Test status
Simulation time 28065002 ps
CPU time 1.22 seconds
Started Oct 15 11:27:16 AM UTC 24
Finished Oct 15 11:27:18 AM UTC 24
Peak memory 227976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748543620 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.1748543620
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/48.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/48.edn_disable_auto_req_mode.766748578
Short name T583
Test name
Test status
Simulation time 40762429 ps
CPU time 1.9 seconds
Started Oct 15 11:27:16 AM UTC 24
Finished Oct 15 11:27:19 AM UTC 24
Peak memory 230088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766748578 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable_auto_req_mode.766748578
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/48.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/48.edn_err.693183865
Short name T140
Test name
Test status
Simulation time 20581254 ps
CPU time 1.58 seconds
Started Oct 15 11:27:16 AM UTC 24
Finished Oct 15 11:27:18 AM UTC 24
Peak memory 231956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693183865 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 48.edn_err.693183865
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/48.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/48.edn_genbits.2629695291
Short name T579
Test name
Test status
Simulation time 166494058 ps
CPU time 2.49 seconds
Started Oct 15 11:27:15 AM UTC 24
Finished Oct 15 11:27:18 AM UTC 24
Peak memory 231096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629695291 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_genbits.2629695291
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/48.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/48.edn_intr.1529972207
Short name T577
Test name
Test status
Simulation time 21157600 ps
CPU time 1.71 seconds
Started Oct 15 11:27:15 AM UTC 24
Finished Oct 15 11:27:17 AM UTC 24
Peak memory 238312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529972207 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 48.edn_intr.1529972207
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/48.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/48.edn_smoke.725666224
Short name T576
Test name
Test status
Simulation time 18529615 ps
CPU time 1.33 seconds
Started Oct 15 11:27:15 AM UTC 24
Finished Oct 15 11:27:17 AM UTC 24
Peak memory 227860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725666224 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 48.edn_smoke.725666224
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/48.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/48.edn_stress_all.2418255305
Short name T338
Test name
Test status
Simulation time 531232559 ps
CPU time 3.26 seconds
Started Oct 15 11:27:15 AM UTC 24
Finished Oct 15 11:27:19 AM UTC 24
Peak memory 229360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418255305 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.2418255305
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/48.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/49.edn_alert.1632621606
Short name T588
Test name
Test status
Simulation time 21849834 ps
CPU time 1.64 seconds
Started Oct 15 11:27:18 AM UTC 24
Finished Oct 15 11:27:21 AM UTC 24
Peak memory 230032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632621606 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 49.edn_alert.1632621606
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/49.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/49.edn_alert_test.3320025452
Short name T530
Test name
Test status
Simulation time 27324739 ps
CPU time 1.54 seconds
Started Oct 15 11:27:20 AM UTC 24
Finished Oct 15 11:27:22 AM UTC 24
Peak memory 217852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320025452 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.3320025452
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/49.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/49.edn_disable.3817956002
Short name T586
Test name
Test status
Simulation time 13375379 ps
CPU time 1.07 seconds
Started Oct 15 11:27:19 AM UTC 24
Finished Oct 15 11:27:21 AM UTC 24
Peak memory 228036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817956002 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.3817956002
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/49.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/49.edn_disable_auto_req_mode.2706454295
Short name T149
Test name
Test status
Simulation time 32912953 ps
CPU time 1.53 seconds
Started Oct 15 11:27:19 AM UTC 24
Finished Oct 15 11:27:21 AM UTC 24
Peak memory 227856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706454295 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable_auto_req_mode.2706454295
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/49.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/49.edn_err.1958089745
Short name T587
Test name
Test status
Simulation time 34906174 ps
CPU time 1.41 seconds
Started Oct 15 11:27:18 AM UTC 24
Finished Oct 15 11:27:21 AM UTC 24
Peak memory 231960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958089745 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 49.edn_err.1958089745
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/49.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/49.edn_genbits.130795664
Short name T343
Test name
Test status
Simulation time 56519047 ps
CPU time 1.98 seconds
Started Oct 15 11:27:17 AM UTC 24
Finished Oct 15 11:27:20 AM UTC 24
Peak memory 230044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130795664 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.edn_genbits.130795664
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/49.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/49.edn_intr.884855034
Short name T585
Test name
Test status
Simulation time 22364302 ps
CPU time 1.4 seconds
Started Oct 15 11:27:17 AM UTC 24
Finished Oct 15 11:27:20 AM UTC 24
Peak memory 229968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884855034 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 49.edn_intr.884855034
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/49.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/49.edn_smoke.1855057983
Short name T584
Test name
Test status
Simulation time 178258469 ps
CPU time 1.29 seconds
Started Oct 15 11:27:17 AM UTC 24
Finished Oct 15 11:27:19 AM UTC 24
Peak memory 227852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855057983 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 49.edn_smoke.1855057983
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/49.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/49.edn_stress_all.1014518114
Short name T589
Test name
Test status
Simulation time 628248247 ps
CPU time 3.59 seconds
Started Oct 15 11:27:17 AM UTC 24
Finished Oct 15 11:27:22 AM UTC 24
Peak memory 231324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014518114 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.1014518114
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/49.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/49.edn_stress_all_with_rand_reset.3571075424
Short name T721
Test name
Test status
Simulation time 1698589770 ps
CPU time 42.97 seconds
Started Oct 15 11:27:17 AM UTC 24
Finished Oct 15 11:28:02 AM UTC 24
Peak memory 231300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3571075424 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all
_with_rand_reset.3571075424
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/49.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/5.edn_alert.2090243
Short name T132
Test name
Test status
Simulation time 28059299 ps
CPU time 1.84 seconds
Started Oct 15 11:25:12 AM UTC 24
Finished Oct 15 11:25:15 AM UTC 24
Peak memory 232080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090243 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_al
ert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 5.edn_alert.2090243
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/5.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/5.edn_alert_test.2465663621
Short name T365
Test name
Test status
Simulation time 34137728 ps
CPU time 1.19 seconds
Started Oct 15 11:25:15 AM UTC 24
Finished Oct 15 11:25:17 AM UTC 24
Peak memory 216536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465663621 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.2465663621
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/5.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/5.edn_disable.1472093855
Short name T181
Test name
Test status
Simulation time 31270662 ps
CPU time 1.24 seconds
Started Oct 15 11:25:14 AM UTC 24
Finished Oct 15 11:25:16 AM UTC 24
Peak memory 227984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472093855 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.1472093855
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/5.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/5.edn_disable_auto_req_mode.708119101
Short name T89
Test name
Test status
Simulation time 64709085 ps
CPU time 1.8 seconds
Started Oct 15 11:25:14 AM UTC 24
Finished Oct 15 11:25:16 AM UTC 24
Peak memory 229908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708119101 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable_auto_req_mode.708119101
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/5.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/5.edn_err.3938682547
Short name T114
Test name
Test status
Simulation time 29697170 ps
CPU time 1.86 seconds
Started Oct 15 11:25:14 AM UTC 24
Finished Oct 15 11:25:16 AM UTC 24
Peak memory 231960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938682547 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 5.edn_err.3938682547
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/5.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/5.edn_genbits.576444704
Short name T44
Test name
Test status
Simulation time 66103456 ps
CPU time 1.87 seconds
Started Oct 15 11:25:11 AM UTC 24
Finished Oct 15 11:25:14 AM UTC 24
Peak memory 229904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576444704 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.edn_genbits.576444704
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/5.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/5.edn_intr.3724793607
Short name T40
Test name
Test status
Simulation time 45244853 ps
CPU time 1.49 seconds
Started Oct 15 11:25:12 AM UTC 24
Finished Oct 15 11:25:15 AM UTC 24
Peak memory 238304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724793607 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 5.edn_intr.3724793607
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/5.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/5.edn_regwen.2249901806
Short name T316
Test name
Test status
Simulation time 17230177 ps
CPU time 1.52 seconds
Started Oct 15 11:25:11 AM UTC 24
Finished Oct 15 11:25:14 AM UTC 24
Peak memory 217624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249901806 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 5.edn_regwen.2249901806
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/5.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/5.edn_smoke.774467976
Short name T364
Test name
Test status
Simulation time 14655285 ps
CPU time 1.44 seconds
Started Oct 15 11:25:11 AM UTC 24
Finished Oct 15 11:25:14 AM UTC 24
Peak memory 227860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774467976 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 5.edn_smoke.774467976
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/5.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/5.edn_stress_all.2946541313
Short name T129
Test name
Test status
Simulation time 506742546 ps
CPU time 3.35 seconds
Started Oct 15 11:25:11 AM UTC 24
Finished Oct 15 11:25:16 AM UTC 24
Peak memory 231332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946541313 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.2946541313
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/5.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/50.edn_alert.2184825822
Short name T590
Test name
Test status
Simulation time 85545513 ps
CPU time 1.23 seconds
Started Oct 15 11:27:20 AM UTC 24
Finished Oct 15 11:27:22 AM UTC 24
Peak memory 230032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184825822 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 50.edn_alert.2184825822
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/50.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/50.edn_err.4049608306
Short name T592
Test name
Test status
Simulation time 22609418 ps
CPU time 1.76 seconds
Started Oct 15 11:27:20 AM UTC 24
Finished Oct 15 11:27:23 AM UTC 24
Peak memory 248228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049608306 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 50.edn_err.4049608306
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/50.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/50.edn_genbits.3037303774
Short name T593
Test name
Test status
Simulation time 53069004 ps
CPU time 1.87 seconds
Started Oct 15 11:27:20 AM UTC 24
Finished Oct 15 11:27:23 AM UTC 24
Peak memory 227848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037303774 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 50.edn_genbits.3037303774
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/50.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/51.edn_alert.3857589855
Short name T209
Test name
Test status
Simulation time 309827882 ps
CPU time 1.91 seconds
Started Oct 15 11:27:20 AM UTC 24
Finished Oct 15 11:27:23 AM UTC 24
Peak memory 232080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857589855 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 51.edn_alert.3857589855
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/51.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/51.edn_err.2608777107
Short name T591
Test name
Test status
Simulation time 42921702 ps
CPU time 1.52 seconds
Started Oct 15 11:27:20 AM UTC 24
Finished Oct 15 11:27:23 AM UTC 24
Peak memory 231960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608777107 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 51.edn_err.2608777107
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/51.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/51.edn_genbits.3822494469
Short name T594
Test name
Test status
Simulation time 39746393 ps
CPU time 1.62 seconds
Started Oct 15 11:27:20 AM UTC 24
Finished Oct 15 11:27:23 AM UTC 24
Peak memory 230044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822494469 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 51.edn_genbits.3822494469
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/51.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/52.edn_alert.2675214945
Short name T210
Test name
Test status
Simulation time 24328780 ps
CPU time 1.69 seconds
Started Oct 15 11:27:21 AM UTC 24
Finished Oct 15 11:27:24 AM UTC 24
Peak memory 232080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675214945 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 52.edn_alert.2675214945
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/52.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/52.edn_err.3706372050
Short name T195
Test name
Test status
Simulation time 27330556 ps
CPU time 0.94 seconds
Started Oct 15 11:27:21 AM UTC 24
Finished Oct 15 11:27:23 AM UTC 24
Peak memory 229912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706372050 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 52.edn_err.3706372050
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/52.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/52.edn_genbits.3724798174
Short name T597
Test name
Test status
Simulation time 59527795 ps
CPU time 2.22 seconds
Started Oct 15 11:27:21 AM UTC 24
Finished Oct 15 11:27:25 AM UTC 24
Peak memory 231096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724798174 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 52.edn_genbits.3724798174
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/52.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/53.edn_alert.400295769
Short name T598
Test name
Test status
Simulation time 48606007 ps
CPU time 1.35 seconds
Started Oct 15 11:27:22 AM UTC 24
Finished Oct 15 11:27:25 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400295769 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 53.edn_alert.400295769
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/53.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/53.edn_err.2343904936
Short name T596
Test name
Test status
Simulation time 38495790 ps
CPU time 1.25 seconds
Started Oct 15 11:27:22 AM UTC 24
Finished Oct 15 11:27:25 AM UTC 24
Peak memory 229912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343904936 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 53.edn_err.2343904936
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/53.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/53.edn_genbits.17819075
Short name T595
Test name
Test status
Simulation time 40976875 ps
CPU time 1.22 seconds
Started Oct 15 11:27:21 AM UTC 24
Finished Oct 15 11:27:24 AM UTC 24
Peak memory 227844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17819075 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 53.edn_genbits.17819075
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/53.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/54.edn_alert.333184489
Short name T599
Test name
Test status
Simulation time 98674930 ps
CPU time 1.48 seconds
Started Oct 15 11:27:23 AM UTC 24
Finished Oct 15 11:27:26 AM UTC 24
Peak memory 227980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333184489 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 54.edn_alert.333184489
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/54.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/54.edn_err.2267769780
Short name T603
Test name
Test status
Simulation time 28209925 ps
CPU time 1.88 seconds
Started Oct 15 11:27:24 AM UTC 24
Finished Oct 15 11:27:26 AM UTC 24
Peak memory 244140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267769780 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 54.edn_err.2267769780
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/54.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/55.edn_alert.232325688
Short name T600
Test name
Test status
Simulation time 31551250 ps
CPU time 1.51 seconds
Started Oct 15 11:27:24 AM UTC 24
Finished Oct 15 11:27:26 AM UTC 24
Peak memory 232076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232325688 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 55.edn_alert.232325688
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/55.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/55.edn_genbits.2671153125
Short name T601
Test name
Test status
Simulation time 29503480 ps
CPU time 1.71 seconds
Started Oct 15 11:27:24 AM UTC 24
Finished Oct 15 11:27:26 AM UTC 24
Peak memory 227848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671153125 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 55.edn_genbits.2671153125
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/55.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/56.edn_alert.2305224176
Short name T602
Test name
Test status
Simulation time 32526949 ps
CPU time 1.53 seconds
Started Oct 15 11:27:24 AM UTC 24
Finished Oct 15 11:27:26 AM UTC 24
Peak memory 227984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305224176 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 56.edn_alert.2305224176
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/56.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/56.edn_err.4140454436
Short name T207
Test name
Test status
Simulation time 23002615 ps
CPU time 1.36 seconds
Started Oct 15 11:27:24 AM UTC 24
Finished Oct 15 11:27:26 AM UTC 24
Peak memory 229912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140454436 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 56.edn_err.4140454436
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/56.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/56.edn_genbits.830705345
Short name T604
Test name
Test status
Simulation time 42860135 ps
CPU time 2.31 seconds
Started Oct 15 11:27:24 AM UTC 24
Finished Oct 15 11:27:27 AM UTC 24
Peak memory 231184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830705345 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 56.edn_genbits.830705345
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/56.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/57.edn_alert.1711423490
Short name T192
Test name
Test status
Simulation time 41249190 ps
CPU time 1.58 seconds
Started Oct 15 11:27:25 AM UTC 24
Finished Oct 15 11:27:28 AM UTC 24
Peak memory 230032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711423490 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 57.edn_alert.1711423490
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/57.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/57.edn_err.1946818101
Short name T606
Test name
Test status
Simulation time 18138708 ps
CPU time 1.35 seconds
Started Oct 15 11:27:25 AM UTC 24
Finished Oct 15 11:27:28 AM UTC 24
Peak memory 229840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946818101 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 57.edn_err.1946818101
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/57.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/57.edn_genbits.558393015
Short name T607
Test name
Test status
Simulation time 44080590 ps
CPU time 1.82 seconds
Started Oct 15 11:27:25 AM UTC 24
Finished Oct 15 11:27:28 AM UTC 24
Peak memory 230200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558393015 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 57.edn_genbits.558393015
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/57.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/58.edn_alert.1947025687
Short name T609
Test name
Test status
Simulation time 40063167 ps
CPU time 1.53 seconds
Started Oct 15 11:27:26 AM UTC 24
Finished Oct 15 11:27:29 AM UTC 24
Peak memory 232076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947025687 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 58.edn_alert.1947025687
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/58.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/58.edn_err.32932086
Short name T608
Test name
Test status
Simulation time 117144046 ps
CPU time 1.14 seconds
Started Oct 15 11:27:26 AM UTC 24
Finished Oct 15 11:27:29 AM UTC 24
Peak memory 231952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32932086 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 58.edn_err.32932086
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/58.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/58.edn_genbits.1327511994
Short name T13
Test name
Test status
Simulation time 35331604 ps
CPU time 1.85 seconds
Started Oct 15 11:27:25 AM UTC 24
Finished Oct 15 11:27:29 AM UTC 24
Peak memory 231888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327511994 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 58.edn_genbits.1327511994
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/58.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/59.edn_alert.2397850941
Short name T610
Test name
Test status
Simulation time 41554672 ps
CPU time 1.65 seconds
Started Oct 15 11:27:26 AM UTC 24
Finished Oct 15 11:27:29 AM UTC 24
Peak memory 227984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397850941 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 59.edn_alert.2397850941
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/59.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/59.edn_err.2388329291
Short name T612
Test name
Test status
Simulation time 44289771 ps
CPU time 1.26 seconds
Started Oct 15 11:27:27 AM UTC 24
Finished Oct 15 11:27:30 AM UTC 24
Peak memory 244104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388329291 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 59.edn_err.2388329291
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/59.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/59.edn_genbits.1453786545
Short name T611
Test name
Test status
Simulation time 57112821 ps
CPU time 1.87 seconds
Started Oct 15 11:27:26 AM UTC 24
Finished Oct 15 11:27:30 AM UTC 24
Peak memory 230044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453786545 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 59.edn_genbits.1453786545
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/59.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/6.edn_alert_test.3718187157
Short name T366
Test name
Test status
Simulation time 17416992 ps
CPU time 1.4 seconds
Started Oct 15 11:25:17 AM UTC 24
Finished Oct 15 11:25:20 AM UTC 24
Peak memory 228616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718187157 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.3718187157
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/6.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/6.edn_disable.2254547698
Short name T45
Test name
Test status
Simulation time 13346076 ps
CPU time 1.35 seconds
Started Oct 15 11:25:17 AM UTC 24
Finished Oct 15 11:25:20 AM UTC 24
Peak memory 228044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254547698 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.2254547698
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/6.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/6.edn_intr.1630409477
Short name T30
Test name
Test status
Simulation time 21826490 ps
CPU time 1.4 seconds
Started Oct 15 11:25:16 AM UTC 24
Finished Oct 15 11:25:18 AM UTC 24
Peak memory 229968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630409477 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 6.edn_intr.1630409477
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/6.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/6.edn_regwen.2227119864
Short name T318
Test name
Test status
Simulation time 30445180 ps
CPU time 1.5 seconds
Started Oct 15 11:25:15 AM UTC 24
Finished Oct 15 11:25:17 AM UTC 24
Peak memory 217624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227119864 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 6.edn_regwen.2227119864
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/6.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/6.edn_smoke.4263070736
Short name T256
Test name
Test status
Simulation time 25046466 ps
CPU time 1.26 seconds
Started Oct 15 11:25:15 AM UTC 24
Finished Oct 15 11:25:17 AM UTC 24
Peak memory 217696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263070736 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 6.edn_smoke.4263070736
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/6.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/6.edn_stress_all.2146857921
Short name T216
Test name
Test status
Simulation time 110922777 ps
CPU time 3.8 seconds
Started Oct 15 11:25:16 AM UTC 24
Finished Oct 15 11:25:21 AM UTC 24
Peak memory 229080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146857921 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.2146857921
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/6.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/6.edn_stress_all_with_rand_reset.2667964154
Short name T240
Test name
Test status
Simulation time 23334301711 ps
CPU time 89.47 seconds
Started Oct 15 11:25:16 AM UTC 24
Finished Oct 15 11:26:47 AM UTC 24
Peak memory 229476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2667964154 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_
with_rand_reset.2667964154
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/6.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/60.edn_alert.2166533175
Short name T613
Test name
Test status
Simulation time 70649693 ps
CPU time 1.24 seconds
Started Oct 15 11:27:27 AM UTC 24
Finished Oct 15 11:27:30 AM UTC 24
Peak memory 230032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166533175 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 60.edn_alert.2166533175
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/60.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/60.edn_err.856108757
Short name T208
Test name
Test status
Simulation time 21883112 ps
CPU time 1.6 seconds
Started Oct 15 11:27:28 AM UTC 24
Finished Oct 15 11:27:30 AM UTC 24
Peak memory 229908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856108757 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 60.edn_err.856108757
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/60.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/60.edn_genbits.2604781280
Short name T340
Test name
Test status
Simulation time 97660747 ps
CPU time 2.03 seconds
Started Oct 15 11:27:27 AM UTC 24
Finished Oct 15 11:27:31 AM UTC 24
Peak memory 231284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604781280 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 60.edn_genbits.2604781280
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/60.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/61.edn_alert.2725502534
Short name T614
Test name
Test status
Simulation time 33888757 ps
CPU time 1.6 seconds
Started Oct 15 11:27:28 AM UTC 24
Finished Oct 15 11:27:30 AM UTC 24
Peak memory 232080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725502534 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 61.edn_alert.2725502534
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/61.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/61.edn_err.4168642079
Short name T179
Test name
Test status
Simulation time 22663673 ps
CPU time 1.18 seconds
Started Oct 15 11:27:28 AM UTC 24
Finished Oct 15 11:27:30 AM UTC 24
Peak memory 229912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168642079 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 61.edn_err.4168642079
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/61.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/61.edn_genbits.2753344722
Short name T615
Test name
Test status
Simulation time 53025711 ps
CPU time 1.72 seconds
Started Oct 15 11:27:28 AM UTC 24
Finished Oct 15 11:27:30 AM UTC 24
Peak memory 229904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753344722 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 61.edn_genbits.2753344722
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/61.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/62.edn_alert.4270265095
Short name T617
Test name
Test status
Simulation time 36890969 ps
CPU time 1.38 seconds
Started Oct 15 11:27:29 AM UTC 24
Finished Oct 15 11:27:32 AM UTC 24
Peak memory 232080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270265095 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 62.edn_alert.4270265095
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/62.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/62.edn_err.1613369231
Short name T616
Test name
Test status
Simulation time 23515349 ps
CPU time 1.28 seconds
Started Oct 15 11:27:29 AM UTC 24
Finished Oct 15 11:27:31 AM UTC 24
Peak memory 229912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613369231 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 62.edn_err.1613369231
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/62.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/62.edn_genbits.2262719201
Short name T359
Test name
Test status
Simulation time 41644633 ps
CPU time 2.03 seconds
Started Oct 15 11:27:29 AM UTC 24
Finished Oct 15 11:27:32 AM UTC 24
Peak memory 233452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262719201 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 62.edn_genbits.2262719201
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/62.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/63.edn_alert.3474253619
Short name T619
Test name
Test status
Simulation time 37786760 ps
CPU time 1.06 seconds
Started Oct 15 11:27:30 AM UTC 24
Finished Oct 15 11:27:32 AM UTC 24
Peak memory 232076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474253619 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 63.edn_alert.3474253619
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/63.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/63.edn_err.3735377262
Short name T157
Test name
Test status
Simulation time 45463828 ps
CPU time 0.95 seconds
Started Oct 15 11:27:30 AM UTC 24
Finished Oct 15 11:27:32 AM UTC 24
Peak memory 231960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735377262 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 63.edn_err.3735377262
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/63.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/63.edn_genbits.3027334488
Short name T618
Test name
Test status
Simulation time 82683464 ps
CPU time 1.35 seconds
Started Oct 15 11:27:29 AM UTC 24
Finished Oct 15 11:27:32 AM UTC 24
Peak memory 227804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027334488 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 63.edn_genbits.3027334488
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/63.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/64.edn_alert.1275462771
Short name T234
Test name
Test status
Simulation time 77420699 ps
CPU time 1.45 seconds
Started Oct 15 11:27:30 AM UTC 24
Finished Oct 15 11:27:33 AM UTC 24
Peak memory 230020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275462771 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 64.edn_alert.1275462771
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/64.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/64.edn_err.1624000957
Short name T621
Test name
Test status
Simulation time 24467054 ps
CPU time 1.32 seconds
Started Oct 15 11:27:30 AM UTC 24
Finished Oct 15 11:27:33 AM UTC 24
Peak memory 229912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624000957 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 64.edn_err.1624000957
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/64.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/64.edn_genbits.2436288848
Short name T620
Test name
Test status
Simulation time 45905788 ps
CPU time 1.41 seconds
Started Oct 15 11:27:30 AM UTC 24
Finished Oct 15 11:27:33 AM UTC 24
Peak memory 229892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436288848 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 64.edn_genbits.2436288848
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/64.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/65.edn_alert.2749323936
Short name T265
Test name
Test status
Simulation time 260869726 ps
CPU time 2.16 seconds
Started Oct 15 11:27:31 AM UTC 24
Finished Oct 15 11:27:35 AM UTC 24
Peak memory 231584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749323936 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 65.edn_alert.2749323936
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/65.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/65.edn_err.1383648196
Short name T622
Test name
Test status
Simulation time 21068269 ps
CPU time 1.31 seconds
Started Oct 15 11:27:31 AM UTC 24
Finished Oct 15 11:27:34 AM UTC 24
Peak memory 229912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383648196 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 65.edn_err.1383648196
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/65.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/65.edn_genbits.1405188379
Short name T269
Test name
Test status
Simulation time 307063388 ps
CPU time 4.22 seconds
Started Oct 15 11:27:30 AM UTC 24
Finished Oct 15 11:27:36 AM UTC 24
Peak memory 233128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405188379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 65.edn_genbits.1405188379
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/65.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/66.edn_alert.489430045
Short name T623
Test name
Test status
Simulation time 23369273 ps
CPU time 1.69 seconds
Started Oct 15 11:27:31 AM UTC 24
Finished Oct 15 11:27:35 AM UTC 24
Peak memory 231960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489430045 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 66.edn_alert.489430045
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/66.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/66.edn_err.1176184893
Short name T164
Test name
Test status
Simulation time 54141526 ps
CPU time 1.14 seconds
Started Oct 15 11:27:31 AM UTC 24
Finished Oct 15 11:27:34 AM UTC 24
Peak memory 231960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176184893 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 66.edn_err.1176184893
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/66.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/66.edn_genbits.741315696
Short name T264
Test name
Test status
Simulation time 34172711 ps
CPU time 1.83 seconds
Started Oct 15 11:27:31 AM UTC 24
Finished Oct 15 11:27:35 AM UTC 24
Peak memory 230140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741315696 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 66.edn_genbits.741315696
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/66.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/67.edn_alert.1365232168
Short name T138
Test name
Test status
Simulation time 92832250 ps
CPU time 1.7 seconds
Started Oct 15 11:27:32 AM UTC 24
Finished Oct 15 11:27:35 AM UTC 24
Peak memory 230032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365232168 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 67.edn_alert.1365232168
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/67.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/67.edn_err.1417645036
Short name T268
Test name
Test status
Simulation time 66820366 ps
CPU time 1.62 seconds
Started Oct 15 11:27:33 AM UTC 24
Finished Oct 15 11:27:35 AM UTC 24
Peak memory 244084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417645036 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 67.edn_err.1417645036
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/67.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/67.edn_genbits.2925970301
Short name T266
Test name
Test status
Simulation time 62591309 ps
CPU time 2.31 seconds
Started Oct 15 11:27:31 AM UTC 24
Finished Oct 15 11:27:35 AM UTC 24
Peak memory 230928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925970301 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 67.edn_genbits.2925970301
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/67.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/68.edn_alert.3861206861
Short name T150
Test name
Test status
Simulation time 28334772 ps
CPU time 1.85 seconds
Started Oct 15 11:27:33 AM UTC 24
Finished Oct 15 11:27:36 AM UTC 24
Peak memory 230032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861206861 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 68.edn_alert.3861206861
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/68.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/68.edn_err.171026276
Short name T267
Test name
Test status
Simulation time 18298914 ps
CPU time 1.39 seconds
Started Oct 15 11:27:33 AM UTC 24
Finished Oct 15 11:27:35 AM UTC 24
Peak memory 238440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171026276 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 68.edn_err.171026276
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/68.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/68.edn_genbits.3014233999
Short name T628
Test name
Test status
Simulation time 101025832 ps
CPU time 3.4 seconds
Started Oct 15 11:27:33 AM UTC 24
Finished Oct 15 11:27:37 AM UTC 24
Peak memory 233100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014233999 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 68.edn_genbits.3014233999
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/68.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/69.edn_alert.2522073794
Short name T625
Test name
Test status
Simulation time 25823106 ps
CPU time 1.46 seconds
Started Oct 15 11:27:34 AM UTC 24
Finished Oct 15 11:27:37 AM UTC 24
Peak memory 232080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522073794 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 69.edn_alert.2522073794
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/69.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/69.edn_err.2312005738
Short name T627
Test name
Test status
Simulation time 27706390 ps
CPU time 1.86 seconds
Started Oct 15 11:27:34 AM UTC 24
Finished Oct 15 11:27:37 AM UTC 24
Peak memory 244144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312005738 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 69.edn_err.2312005738
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/69.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/69.edn_genbits.247581330
Short name T270
Test name
Test status
Simulation time 86100065 ps
CPU time 2.05 seconds
Started Oct 15 11:27:33 AM UTC 24
Finished Oct 15 11:27:36 AM UTC 24
Peak memory 231096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247581330 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 69.edn_genbits.247581330
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/69.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/7.edn_alert.2669340400
Short name T58
Test name
Test status
Simulation time 109498969 ps
CPU time 1.76 seconds
Started Oct 15 11:25:20 AM UTC 24
Finished Oct 15 11:25:23 AM UTC 24
Peak memory 232076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669340400 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 7.edn_alert.2669340400
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/7.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/7.edn_disable.1564258565
Short name T52
Test name
Test status
Simulation time 23203720 ps
CPU time 1.31 seconds
Started Oct 15 11:25:21 AM UTC 24
Finished Oct 15 11:25:23 AM UTC 24
Peak memory 227984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564258565 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.1564258565
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/7.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/7.edn_disable_auto_req_mode.485221781
Short name T291
Test name
Test status
Simulation time 47199759 ps
CPU time 1.52 seconds
Started Oct 15 11:25:21 AM UTC 24
Finished Oct 15 11:25:24 AM UTC 24
Peak memory 227860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485221781 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable_auto_req_mode.485221781
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/7.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/7.edn_err.1377771970
Short name T8
Test name
Test status
Simulation time 31958803 ps
CPU time 1.53 seconds
Started Oct 15 11:25:21 AM UTC 24
Finished Oct 15 11:25:24 AM UTC 24
Peak memory 231960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377771970 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 7.edn_err.1377771970
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/7.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/7.edn_genbits.443461666
Short name T305
Test name
Test status
Simulation time 45982317 ps
CPU time 2.11 seconds
Started Oct 15 11:25:19 AM UTC 24
Finished Oct 15 11:25:22 AM UTC 24
Peak memory 233524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443461666 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.edn_genbits.443461666
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/7.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/7.edn_intr.645574129
Short name T102
Test name
Test status
Simulation time 22230397 ps
CPU time 1.55 seconds
Started Oct 15 11:25:20 AM UTC 24
Finished Oct 15 11:25:23 AM UTC 24
Peak memory 227924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645574129 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 7.edn_intr.645574129
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/7.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/7.edn_regwen.2286559364
Short name T257
Test name
Test status
Simulation time 18534368 ps
CPU time 1.54 seconds
Started Oct 15 11:25:19 AM UTC 24
Finished Oct 15 11:25:21 AM UTC 24
Peak memory 217744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286559364 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 7.edn_regwen.2286559364
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/7.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/7.edn_smoke.56186501
Short name T367
Test name
Test status
Simulation time 81258793 ps
CPU time 1.11 seconds
Started Oct 15 11:25:18 AM UTC 24
Finished Oct 15 11:25:21 AM UTC 24
Peak memory 227864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56186501 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 7.edn_smoke.56186501
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/7.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/7.edn_stress_all_with_rand_reset.271303984
Short name T217
Test name
Test status
Simulation time 5848532072 ps
CPU time 75.8 seconds
Started Oct 15 11:25:19 AM UTC 24
Finished Oct 15 11:26:36 AM UTC 24
Peak memory 233276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=271303984 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_w
ith_rand_reset.271303984
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/7.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/70.edn_alert.3829091963
Short name T271
Test name
Test status
Simulation time 25262183 ps
CPU time 1.32 seconds
Started Oct 15 11:27:34 AM UTC 24
Finished Oct 15 11:27:36 AM UTC 24
Peak memory 227984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829091963 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 70.edn_alert.3829091963
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/70.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/70.edn_err.2306060147
Short name T147
Test name
Test status
Simulation time 55847103 ps
CPU time 1.3 seconds
Started Oct 15 11:27:35 AM UTC 24
Finished Oct 15 11:27:38 AM UTC 24
Peak memory 231940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306060147 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 70.edn_err.2306060147
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/70.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/70.edn_genbits.3015605435
Short name T626
Test name
Test status
Simulation time 27431664 ps
CPU time 1.84 seconds
Started Oct 15 11:27:34 AM UTC 24
Finished Oct 15 11:27:37 AM UTC 24
Peak memory 227860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015605435 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 70.edn_genbits.3015605435
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/70.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/71.edn_alert.185353529
Short name T211
Test name
Test status
Simulation time 88925518 ps
CPU time 1.54 seconds
Started Oct 15 11:27:35 AM UTC 24
Finished Oct 15 11:27:38 AM UTC 24
Peak memory 232048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185353529 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 71.edn_alert.185353529
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/71.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/71.edn_err.418527555
Short name T629
Test name
Test status
Simulation time 21828642 ps
CPU time 1.16 seconds
Started Oct 15 11:27:35 AM UTC 24
Finished Oct 15 11:27:38 AM UTC 24
Peak memory 229908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418527555 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 71.edn_err.418527555
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/71.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/71.edn_genbits.1772374861
Short name T633
Test name
Test status
Simulation time 218692495 ps
CPU time 2.65 seconds
Started Oct 15 11:27:35 AM UTC 24
Finished Oct 15 11:27:39 AM UTC 24
Peak memory 233148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772374861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 71.edn_genbits.1772374861
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/71.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/72.edn_alert.4209440469
Short name T184
Test name
Test status
Simulation time 33520255 ps
CPU time 1.68 seconds
Started Oct 15 11:27:36 AM UTC 24
Finished Oct 15 11:27:39 AM UTC 24
Peak memory 232080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209440469 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 72.edn_alert.4209440469
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/72.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/72.edn_err.984877653
Short name T634
Test name
Test status
Simulation time 29788438 ps
CPU time 1.66 seconds
Started Oct 15 11:27:36 AM UTC 24
Finished Oct 15 11:27:39 AM UTC 24
Peak memory 231956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984877653 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 72.edn_err.984877653
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/72.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/72.edn_genbits.2739207300
Short name T630
Test name
Test status
Simulation time 77687941 ps
CPU time 1.59 seconds
Started Oct 15 11:27:35 AM UTC 24
Finished Oct 15 11:27:38 AM UTC 24
Peak memory 229908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739207300 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 72.edn_genbits.2739207300
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/72.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/73.edn_alert.3706782368
Short name T151
Test name
Test status
Simulation time 31788208 ps
CPU time 1.47 seconds
Started Oct 15 11:27:37 AM UTC 24
Finished Oct 15 11:27:39 AM UTC 24
Peak memory 232076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706782368 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 73.edn_alert.3706782368
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/73.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/73.edn_err.478890019
Short name T632
Test name
Test status
Simulation time 29206492 ps
CPU time 1.14 seconds
Started Oct 15 11:27:37 AM UTC 24
Finished Oct 15 11:27:39 AM UTC 24
Peak memory 227860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478890019 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 73.edn_err.478890019
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/73.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/73.edn_genbits.450173668
Short name T631
Test name
Test status
Simulation time 50425420 ps
CPU time 1.34 seconds
Started Oct 15 11:27:37 AM UTC 24
Finished Oct 15 11:27:39 AM UTC 24
Peak memory 232248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450173668 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 73.edn_genbits.450173668
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/73.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/74.edn_alert.4212990033
Short name T636
Test name
Test status
Simulation time 90121434 ps
CPU time 1.61 seconds
Started Oct 15 11:27:37 AM UTC 24
Finished Oct 15 11:27:40 AM UTC 24
Peak memory 230032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212990033 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 74.edn_alert.4212990033
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/74.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/74.edn_err.3821737574
Short name T187
Test name
Test status
Simulation time 18585302 ps
CPU time 1.48 seconds
Started Oct 15 11:27:37 AM UTC 24
Finished Oct 15 11:27:40 AM UTC 24
Peak memory 238444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821737574 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 74.edn_err.3821737574
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/74.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/74.edn_genbits.2004756487
Short name T635
Test name
Test status
Simulation time 91365856 ps
CPU time 1.6 seconds
Started Oct 15 11:27:37 AM UTC 24
Finished Oct 15 11:27:39 AM UTC 24
Peak memory 229892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004756487 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 74.edn_genbits.2004756487
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/74.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/75.edn_alert.385197382
Short name T639
Test name
Test status
Simulation time 45006614 ps
CPU time 1.53 seconds
Started Oct 15 11:27:38 AM UTC 24
Finished Oct 15 11:27:40 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385197382 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 75.edn_alert.385197382
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/75.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/75.edn_err.2299552361
Short name T175
Test name
Test status
Simulation time 19062027 ps
CPU time 1.15 seconds
Started Oct 15 11:27:38 AM UTC 24
Finished Oct 15 11:27:40 AM UTC 24
Peak memory 238484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299552361 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 75.edn_err.2299552361
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/75.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/75.edn_genbits.1702069559
Short name T637
Test name
Test status
Simulation time 20800085 ps
CPU time 1.16 seconds
Started Oct 15 11:27:38 AM UTC 24
Finished Oct 15 11:27:40 AM UTC 24
Peak memory 227848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702069559 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 75.edn_genbits.1702069559
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/75.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/76.edn_alert.472295239
Short name T641
Test name
Test status
Simulation time 291077603 ps
CPU time 1.64 seconds
Started Oct 15 11:27:38 AM UTC 24
Finished Oct 15 11:27:41 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472295239 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 76.edn_alert.472295239
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/76.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/76.edn_err.1552457317
Short name T638
Test name
Test status
Simulation time 25372211 ps
CPU time 1.34 seconds
Started Oct 15 11:27:38 AM UTC 24
Finished Oct 15 11:27:40 AM UTC 24
Peak memory 229912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552457317 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 76.edn_err.1552457317
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/76.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/76.edn_genbits.3456150652
Short name T327
Test name
Test status
Simulation time 46039426 ps
CPU time 1.97 seconds
Started Oct 15 11:27:38 AM UTC 24
Finished Oct 15 11:27:41 AM UTC 24
Peak memory 230044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456150652 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 76.edn_genbits.3456150652
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/76.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/77.edn_alert.2722626992
Short name T640
Test name
Test status
Simulation time 30486272 ps
CPU time 1.3 seconds
Started Oct 15 11:27:38 AM UTC 24
Finished Oct 15 11:27:41 AM UTC 24
Peak memory 230032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722626992 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 77.edn_alert.2722626992
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/77.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/77.edn_err.3101906292
Short name T643
Test name
Test status
Simulation time 19879571 ps
CPU time 1.42 seconds
Started Oct 15 11:27:39 AM UTC 24
Finished Oct 15 11:27:42 AM UTC 24
Peak memory 230272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101906292 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 77.edn_err.3101906292
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/77.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/77.edn_genbits.3882649501
Short name T647
Test name
Test status
Simulation time 82078109 ps
CPU time 3.4 seconds
Started Oct 15 11:27:38 AM UTC 24
Finished Oct 15 11:27:43 AM UTC 24
Peak memory 233464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882649501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 77.edn_genbits.3882649501
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/77.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/78.edn_alert.251695595
Short name T644
Test name
Test status
Simulation time 24519141 ps
CPU time 1.4 seconds
Started Oct 15 11:27:39 AM UTC 24
Finished Oct 15 11:27:42 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251695595 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 78.edn_alert.251695595
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/78.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/78.edn_err.1841469002
Short name T645
Test name
Test status
Simulation time 19764309 ps
CPU time 1.48 seconds
Started Oct 15 11:27:39 AM UTC 24
Finished Oct 15 11:27:42 AM UTC 24
Peak memory 229912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841469002 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 78.edn_err.1841469002
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/78.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/78.edn_genbits.3069411837
Short name T336
Test name
Test status
Simulation time 29603992 ps
CPU time 1.27 seconds
Started Oct 15 11:27:39 AM UTC 24
Finished Oct 15 11:27:42 AM UTC 24
Peak memory 229896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069411837 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 78.edn_genbits.3069411837
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/78.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/79.edn_alert.4266363270
Short name T651
Test name
Test status
Simulation time 25745472 ps
CPU time 1.63 seconds
Started Oct 15 11:27:41 AM UTC 24
Finished Oct 15 11:27:44 AM UTC 24
Peak memory 232080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266363270 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 79.edn_alert.4266363270
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/79.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/79.edn_err.1166802756
Short name T648
Test name
Test status
Simulation time 58965914 ps
CPU time 1.21 seconds
Started Oct 15 11:27:41 AM UTC 24
Finished Oct 15 11:27:43 AM UTC 24
Peak memory 238428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166802756 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 79.edn_err.1166802756
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/79.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/79.edn_genbits.805467646
Short name T654
Test name
Test status
Simulation time 46569453 ps
CPU time 2.21 seconds
Started Oct 15 11:27:41 AM UTC 24
Finished Oct 15 11:27:44 AM UTC 24
Peak memory 231360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805467646 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 79.edn_genbits.805467646
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/79.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/8.edn_alert_test.948046546
Short name T369
Test name
Test status
Simulation time 42411725 ps
CPU time 1.3 seconds
Started Oct 15 11:25:25 AM UTC 24
Finished Oct 15 11:25:27 AM UTC 24
Peak memory 228668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948046546 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.948046546
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/8.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/8.edn_disable.3733409204
Short name T176
Test name
Test status
Simulation time 45593126 ps
CPU time 1.31 seconds
Started Oct 15 11:25:25 AM UTC 24
Finished Oct 15 11:25:27 AM UTC 24
Peak memory 228284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733409204 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.3733409204
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/8.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/8.edn_err.3184804013
Short name T65
Test name
Test status
Simulation time 33167715 ps
CPU time 1.05 seconds
Started Oct 15 11:25:25 AM UTC 24
Finished Oct 15 11:25:27 AM UTC 24
Peak memory 238248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184804013 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 8.edn_err.3184804013
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/8.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/8.edn_genbits.3139877909
Short name T47
Test name
Test status
Simulation time 38673528 ps
CPU time 2.29 seconds
Started Oct 15 11:25:22 AM UTC 24
Finished Oct 15 11:25:26 AM UTC 24
Peak memory 231092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139877909 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_genbits.3139877909
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/8.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/8.edn_intr.3645230811
Short name T33
Test name
Test status
Simulation time 23341153 ps
CPU time 1.18 seconds
Started Oct 15 11:25:23 AM UTC 24
Finished Oct 15 11:25:26 AM UTC 24
Peak memory 229968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645230811 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 8.edn_intr.3645230811
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/8.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/8.edn_regwen.2291228154
Short name T319
Test name
Test status
Simulation time 19509797 ps
CPU time 1.52 seconds
Started Oct 15 11:25:21 AM UTC 24
Finished Oct 15 11:25:24 AM UTC 24
Peak memory 217744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291228154 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 8.edn_regwen.2291228154
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/8.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/8.edn_smoke.2865373118
Short name T368
Test name
Test status
Simulation time 34308474 ps
CPU time 1.41 seconds
Started Oct 15 11:25:21 AM UTC 24
Finished Oct 15 11:25:24 AM UTC 24
Peak memory 227860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865373118 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 8.edn_smoke.2865373118
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/8.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/8.edn_stress_all.4008030049
Short name T125
Test name
Test status
Simulation time 223820123 ps
CPU time 1.84 seconds
Started Oct 15 11:25:22 AM UTC 24
Finished Oct 15 11:25:25 AM UTC 24
Peak memory 227856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008030049 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.4008030049
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/8.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/80.edn_alert.1188096446
Short name T650
Test name
Test status
Simulation time 28846595 ps
CPU time 1.37 seconds
Started Oct 15 11:27:41 AM UTC 24
Finished Oct 15 11:27:43 AM UTC 24
Peak memory 232080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188096446 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 80.edn_alert.1188096446
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/80.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/80.edn_err.859615079
Short name T158
Test name
Test status
Simulation time 31462670 ps
CPU time 1.5 seconds
Started Oct 15 11:27:41 AM UTC 24
Finished Oct 15 11:27:44 AM UTC 24
Peak memory 231896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859615079 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 80.edn_err.859615079
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/80.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/80.edn_genbits.4263626528
Short name T332
Test name
Test status
Simulation time 35125322 ps
CPU time 1.6 seconds
Started Oct 15 11:27:41 AM UTC 24
Finished Oct 15 11:27:44 AM UTC 24
Peak memory 230104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263626528 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 80.edn_genbits.4263626528
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/80.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/81.edn_alert.351734421
Short name T653
Test name
Test status
Simulation time 51427475 ps
CPU time 1.45 seconds
Started Oct 15 11:27:41 AM UTC 24
Finished Oct 15 11:27:44 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351734421 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 81.edn_alert.351734421
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/81.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/81.edn_err.3698723676
Short name T652
Test name
Test status
Simulation time 64285710 ps
CPU time 1.22 seconds
Started Oct 15 11:27:41 AM UTC 24
Finished Oct 15 11:27:44 AM UTC 24
Peak memory 231816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698723676 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 81.edn_err.3698723676
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/81.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/81.edn_genbits.3535387881
Short name T649
Test name
Test status
Simulation time 79072948 ps
CPU time 1.24 seconds
Started Oct 15 11:27:41 AM UTC 24
Finished Oct 15 11:27:43 AM UTC 24
Peak memory 229892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535387881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 81.edn_genbits.3535387881
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/81.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/82.edn_alert.2467598331
Short name T655
Test name
Test status
Simulation time 44420597 ps
CPU time 1.26 seconds
Started Oct 15 11:27:42 AM UTC 24
Finished Oct 15 11:27:45 AM UTC 24
Peak memory 232080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467598331 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 82.edn_alert.2467598331
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/82.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/82.edn_err.778953148
Short name T657
Test name
Test status
Simulation time 79917128 ps
CPU time 1.46 seconds
Started Oct 15 11:27:42 AM UTC 24
Finished Oct 15 11:27:45 AM UTC 24
Peak memory 231956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778953148 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 82.edn_err.778953148
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/82.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/82.edn_genbits.220400378
Short name T646
Test name
Test status
Simulation time 59715244 ps
CPU time 1.77 seconds
Started Oct 15 11:27:41 AM UTC 24
Finished Oct 15 11:27:44 AM UTC 24
Peak memory 230140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220400378 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 82.edn_genbits.220400378
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/82.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/83.edn_alert.3010371178
Short name T656
Test name
Test status
Simulation time 28904680 ps
CPU time 1.39 seconds
Started Oct 15 11:27:42 AM UTC 24
Finished Oct 15 11:27:45 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010371178 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 83.edn_alert.3010371178
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/83.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/83.edn_err.1723283054
Short name T658
Test name
Test status
Simulation time 20573801 ps
CPU time 1.4 seconds
Started Oct 15 11:27:42 AM UTC 24
Finished Oct 15 11:27:45 AM UTC 24
Peak memory 229912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723283054 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 83.edn_err.1723283054
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/83.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/83.edn_genbits.4076749466
Short name T898
Test name
Test status
Simulation time 2932268861 ps
CPU time 69.99 seconds
Started Oct 15 11:27:42 AM UTC 24
Finished Oct 15 11:28:54 AM UTC 24
Peak memory 231256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076749466 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 83.edn_genbits.4076749466
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/83.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/84.edn_alert.508280457
Short name T659
Test name
Test status
Simulation time 23936618 ps
CPU time 1.49 seconds
Started Oct 15 11:27:42 AM UTC 24
Finished Oct 15 11:27:45 AM UTC 24
Peak memory 232076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508280457 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 84.edn_alert.508280457
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/84.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/84.edn_err.2570263916
Short name T230
Test name
Test status
Simulation time 34273464 ps
CPU time 1.1 seconds
Started Oct 15 11:27:43 AM UTC 24
Finished Oct 15 11:27:46 AM UTC 24
Peak memory 248176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570263916 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 84.edn_err.2570263916
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/84.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/84.edn_genbits.55415908
Short name T660
Test name
Test status
Simulation time 28210103 ps
CPU time 1.44 seconds
Started Oct 15 11:27:42 AM UTC 24
Finished Oct 15 11:27:45 AM UTC 24
Peak memory 232156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55415908 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 84.edn_genbits.55415908
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/84.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/85.edn_alert.3755995961
Short name T199
Test name
Test status
Simulation time 91514481 ps
CPU time 0.98 seconds
Started Oct 15 11:27:43 AM UTC 24
Finished Oct 15 11:27:46 AM UTC 24
Peak memory 230032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755995961 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 85.edn_alert.3755995961
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/85.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/85.edn_err.190346743
Short name T661
Test name
Test status
Simulation time 35845371 ps
CPU time 1.27 seconds
Started Oct 15 11:27:43 AM UTC 24
Finished Oct 15 11:27:46 AM UTC 24
Peak memory 231956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190346743 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 85.edn_err.190346743
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/85.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/85.edn_genbits.1705309867
Short name T662
Test name
Test status
Simulation time 64100386 ps
CPU time 1.62 seconds
Started Oct 15 11:27:43 AM UTC 24
Finished Oct 15 11:27:47 AM UTC 24
Peak memory 227920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705309867 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 85.edn_genbits.1705309867
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/85.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/86.edn_alert.2203542635
Short name T155
Test name
Test status
Simulation time 28582991 ps
CPU time 1.64 seconds
Started Oct 15 11:27:45 AM UTC 24
Finished Oct 15 11:27:48 AM UTC 24
Peak memory 230032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203542635 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 86.edn_alert.2203542635
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/86.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/86.edn_err.2995951420
Short name T664
Test name
Test status
Simulation time 57617411 ps
CPU time 1.2 seconds
Started Oct 15 11:27:45 AM UTC 24
Finished Oct 15 11:27:47 AM UTC 24
Peak memory 231960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995951420 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 86.edn_err.2995951420
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/86.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/86.edn_genbits.1225790317
Short name T663
Test name
Test status
Simulation time 79310771 ps
CPU time 1.26 seconds
Started Oct 15 11:27:44 AM UTC 24
Finished Oct 15 11:27:47 AM UTC 24
Peak memory 232152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225790317 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 86.edn_genbits.1225790317
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/86.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/87.edn_alert.454333779
Short name T666
Test name
Test status
Simulation time 72484608 ps
CPU time 1.26 seconds
Started Oct 15 11:27:45 AM UTC 24
Finished Oct 15 11:27:47 AM UTC 24
Peak memory 231960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454333779 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 87.edn_alert.454333779
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/87.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/87.edn_err.2098411066
Short name T665
Test name
Test status
Simulation time 41666917 ps
CPU time 1.27 seconds
Started Oct 15 11:27:45 AM UTC 24
Finished Oct 15 11:27:47 AM UTC 24
Peak memory 238248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098411066 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 87.edn_err.2098411066
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/87.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/87.edn_genbits.3752556899
Short name T674
Test name
Test status
Simulation time 148230723 ps
CPU time 2.92 seconds
Started Oct 15 11:27:45 AM UTC 24
Finished Oct 15 11:27:49 AM UTC 24
Peak memory 233144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752556899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 87.edn_genbits.3752556899
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/87.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/88.edn_alert.2414761320
Short name T200
Test name
Test status
Simulation time 72110281 ps
CPU time 1.48 seconds
Started Oct 15 11:27:45 AM UTC 24
Finished Oct 15 11:27:48 AM UTC 24
Peak memory 230032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414761320 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 88.edn_alert.2414761320
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/88.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/88.edn_err.3840372219
Short name T667
Test name
Test status
Simulation time 22335821 ps
CPU time 1.22 seconds
Started Oct 15 11:27:45 AM UTC 24
Finished Oct 15 11:27:47 AM UTC 24
Peak memory 230272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840372219 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 88.edn_err.3840372219
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/88.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/88.edn_genbits.2150147900
Short name T333
Test name
Test status
Simulation time 64864389 ps
CPU time 1.58 seconds
Started Oct 15 11:27:45 AM UTC 24
Finished Oct 15 11:27:48 AM UTC 24
Peak memory 229780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150147900 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 88.edn_genbits.2150147900
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/88.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/89.edn_alert.2620393940
Short name T669
Test name
Test status
Simulation time 31033197 ps
CPU time 1.57 seconds
Started Oct 15 11:27:45 AM UTC 24
Finished Oct 15 11:27:48 AM UTC 24
Peak memory 227964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620393940 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 89.edn_alert.2620393940
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/89.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/89.edn_err.1776999145
Short name T672
Test name
Test status
Simulation time 30629429 ps
CPU time 1.62 seconds
Started Oct 15 11:27:46 AM UTC 24
Finished Oct 15 11:27:49 AM UTC 24
Peak memory 231960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776999145 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 89.edn_err.1776999145
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/89.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/89.edn_genbits.1400678129
Short name T701
Test name
Test status
Simulation time 1132637591 ps
CPU time 9.28 seconds
Started Oct 15 11:27:45 AM UTC 24
Finished Oct 15 11:27:56 AM UTC 24
Peak memory 233136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400678129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 89.edn_genbits.1400678129
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/89.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/9.edn_alert.3488139766
Short name T135
Test name
Test status
Simulation time 62286097 ps
CPU time 1.61 seconds
Started Oct 15 11:25:27 AM UTC 24
Finished Oct 15 11:25:30 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488139766 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 9.edn_alert.3488139766
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/9.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/9.edn_alert_test.189188239
Short name T371
Test name
Test status
Simulation time 16916610 ps
CPU time 1.41 seconds
Started Oct 15 11:25:28 AM UTC 24
Finished Oct 15 11:25:31 AM UTC 24
Peak memory 217848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189188239 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.189188239
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/9.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/9.edn_err.4201330845
Short name T174
Test name
Test status
Simulation time 30111562 ps
CPU time 1.81 seconds
Started Oct 15 11:25:27 AM UTC 24
Finished Oct 15 11:25:30 AM UTC 24
Peak memory 231536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201330845 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 9.edn_err.4201330845
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/9.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/9.edn_genbits.684990507
Short name T41
Test name
Test status
Simulation time 59633879 ps
CPU time 1.78 seconds
Started Oct 15 11:25:25 AM UTC 24
Finished Oct 15 11:25:28 AM UTC 24
Peak memory 231956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684990507 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.edn_genbits.684990507
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/9.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/9.edn_intr.667908517
Short name T66
Test name
Test status
Simulation time 36570803 ps
CPU time 1.16 seconds
Started Oct 15 11:25:27 AM UTC 24
Finished Oct 15 11:25:29 AM UTC 24
Peak memory 238684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667908517 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 9.edn_intr.667908517
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/9.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/9.edn_regwen.1047403668
Short name T321
Test name
Test status
Simulation time 116671176 ps
CPU time 1.34 seconds
Started Oct 15 11:25:25 AM UTC 24
Finished Oct 15 11:25:27 AM UTC 24
Peak memory 217744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047403668 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 9.edn_regwen.1047403668
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/9.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/9.edn_smoke.1495405803
Short name T323
Test name
Test status
Simulation time 24006646 ps
CPU time 1.39 seconds
Started Oct 15 11:25:25 AM UTC 24
Finished Oct 15 11:25:27 AM UTC 24
Peak memory 217620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495405803 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 9.edn_smoke.1495405803
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/9.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/9.edn_stress_all.1080651116
Short name T122
Test name
Test status
Simulation time 219637128 ps
CPU time 4.81 seconds
Started Oct 15 11:25:26 AM UTC 24
Finished Oct 15 11:25:32 AM UTC 24
Peak memory 231140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080651116 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.1080651116
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/9.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/90.edn_alert.1900213094
Short name T671
Test name
Test status
Simulation time 49135346 ps
CPU time 1.33 seconds
Started Oct 15 11:27:46 AM UTC 24
Finished Oct 15 11:27:49 AM UTC 24
Peak memory 232076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900213094 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 90.edn_alert.1900213094
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/90.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/90.edn_err.537696632
Short name T670
Test name
Test status
Simulation time 33201419 ps
CPU time 0.85 seconds
Started Oct 15 11:27:46 AM UTC 24
Finished Oct 15 11:27:48 AM UTC 24
Peak memory 229908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537696632 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 90.edn_err.537696632
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/90.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/90.edn_genbits.4070825097
Short name T673
Test name
Test status
Simulation time 53896773 ps
CPU time 1.72 seconds
Started Oct 15 11:27:46 AM UTC 24
Finished Oct 15 11:27:49 AM UTC 24
Peak memory 232152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070825097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 90.edn_genbits.4070825097
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/90.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/91.edn_alert.3463064371
Short name T675
Test name
Test status
Simulation time 31235880 ps
CPU time 1.48 seconds
Started Oct 15 11:27:46 AM UTC 24
Finished Oct 15 11:27:49 AM UTC 24
Peak memory 227984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463064371 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 91.edn_alert.3463064371
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/91.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/91.edn_err.583000162
Short name T678
Test name
Test status
Simulation time 26420153 ps
CPU time 1.32 seconds
Started Oct 15 11:27:47 AM UTC 24
Finished Oct 15 11:27:50 AM UTC 24
Peak memory 231956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583000162 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 91.edn_err.583000162
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/91.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/91.edn_genbits.1312063097
Short name T342
Test name
Test status
Simulation time 60785319 ps
CPU time 1.31 seconds
Started Oct 15 11:27:46 AM UTC 24
Finished Oct 15 11:27:49 AM UTC 24
Peak memory 229908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312063097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 91.edn_genbits.1312063097
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/91.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/92.edn_alert.119309051
Short name T677
Test name
Test status
Simulation time 26266713 ps
CPU time 1.28 seconds
Started Oct 15 11:27:47 AM UTC 24
Finished Oct 15 11:27:50 AM UTC 24
Peak memory 230028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119309051 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 92.edn_alert.119309051
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/92.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/92.edn_err.4222060811
Short name T676
Test name
Test status
Simulation time 30600142 ps
CPU time 1.15 seconds
Started Oct 15 11:27:47 AM UTC 24
Finished Oct 15 11:27:50 AM UTC 24
Peak memory 231940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222060811 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 92.edn_err.4222060811
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/92.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/93.edn_alert.2930018504
Short name T679
Test name
Test status
Simulation time 89494865 ps
CPU time 1.41 seconds
Started Oct 15 11:27:49 AM UTC 24
Finished Oct 15 11:27:51 AM UTC 24
Peak memory 230032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930018504 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 93.edn_alert.2930018504
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/93.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/93.edn_err.1403906460
Short name T180
Test name
Test status
Simulation time 19714184 ps
CPU time 1.34 seconds
Started Oct 15 11:27:49 AM UTC 24
Finished Oct 15 11:27:51 AM UTC 24
Peak memory 238248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403906460 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 93.edn_err.1403906460
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/93.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/93.edn_genbits.3201419915
Short name T683
Test name
Test status
Simulation time 66691664 ps
CPU time 1.82 seconds
Started Oct 15 11:27:48 AM UTC 24
Finished Oct 15 11:27:51 AM UTC 24
Peak memory 230044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201419915 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 93.edn_genbits.3201419915
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/93.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/94.edn_alert.310425098
Short name T682
Test name
Test status
Simulation time 24565605 ps
CPU time 1.63 seconds
Started Oct 15 11:27:49 AM UTC 24
Finished Oct 15 11:27:51 AM UTC 24
Peak memory 232076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310425098 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 94.edn_alert.310425098
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/94.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/94.edn_err.4034558240
Short name T681
Test name
Test status
Simulation time 28836590 ps
CPU time 1.33 seconds
Started Oct 15 11:27:49 AM UTC 24
Finished Oct 15 11:27:51 AM UTC 24
Peak memory 244136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034558240 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 94.edn_err.4034558240
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/94.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/94.edn_genbits.1900880709
Short name T680
Test name
Test status
Simulation time 80231786 ps
CPU time 1.47 seconds
Started Oct 15 11:27:49 AM UTC 24
Finished Oct 15 11:27:51 AM UTC 24
Peak memory 227848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900880709 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 94.edn_genbits.1900880709
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/94.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/95.edn_alert.13596736
Short name T203
Test name
Test status
Simulation time 31282844 ps
CPU time 1.29 seconds
Started Oct 15 11:27:49 AM UTC 24
Finished Oct 15 11:27:51 AM UTC 24
Peak memory 232076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13596736 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a
lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 95.edn_alert.13596736
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/95.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/95.edn_err.4278846041
Short name T214
Test name
Test status
Simulation time 23250135 ps
CPU time 1.25 seconds
Started Oct 15 11:27:49 AM UTC 24
Finished Oct 15 11:27:51 AM UTC 24
Peak memory 231868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278846041 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 95.edn_err.4278846041
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/95.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/95.edn_genbits.4215549142
Short name T684
Test name
Test status
Simulation time 122565629 ps
CPU time 1.88 seconds
Started Oct 15 11:27:49 AM UTC 24
Finished Oct 15 11:27:52 AM UTC 24
Peak memory 230044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215549142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 95.edn_genbits.4215549142
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/95.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/96.edn_alert.2328286768
Short name T686
Test name
Test status
Simulation time 68467525 ps
CPU time 1.52 seconds
Started Oct 15 11:27:50 AM UTC 24
Finished Oct 15 11:27:53 AM UTC 24
Peak memory 229996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328286768 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 96.edn_alert.2328286768
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/96.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/96.edn_err.3659390065
Short name T154
Test name
Test status
Simulation time 50471891 ps
CPU time 1.16 seconds
Started Oct 15 11:27:50 AM UTC 24
Finished Oct 15 11:27:52 AM UTC 24
Peak memory 231940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659390065 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 96.edn_err.3659390065
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/96.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/96.edn_genbits.1732905052
Short name T691
Test name
Test status
Simulation time 178707493 ps
CPU time 3.08 seconds
Started Oct 15 11:27:49 AM UTC 24
Finished Oct 15 11:27:53 AM UTC 24
Peak memory 233236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732905052 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 96.edn_genbits.1732905052
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/96.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/97.edn_alert.3323842470
Short name T685
Test name
Test status
Simulation time 50509109 ps
CPU time 1.41 seconds
Started Oct 15 11:27:50 AM UTC 24
Finished Oct 15 11:27:52 AM UTC 24
Peak memory 230032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323842470 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 97.edn_alert.3323842470
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/97.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/97.edn_err.3549256148
Short name T687
Test name
Test status
Simulation time 23840964 ps
CPU time 1.55 seconds
Started Oct 15 11:27:50 AM UTC 24
Finished Oct 15 11:27:53 AM UTC 24
Peak memory 229912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549256148 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 97.edn_err.3549256148
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/97.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/97.edn_genbits.3519358291
Short name T351
Test name
Test status
Simulation time 833330603 ps
CPU time 6.93 seconds
Started Oct 15 11:27:50 AM UTC 24
Finished Oct 15 11:27:58 AM UTC 24
Peak memory 231084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519358291 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 97.edn_genbits.3519358291
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/97.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/98.edn_alert.3724192831
Short name T688
Test name
Test status
Simulation time 25476137 ps
CPU time 1.55 seconds
Started Oct 15 11:27:50 AM UTC 24
Finished Oct 15 11:27:53 AM UTC 24
Peak memory 232080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724192831 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 98.edn_alert.3724192831
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/98.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/98.edn_err.2289460372
Short name T165
Test name
Test status
Simulation time 25970223 ps
CPU time 1.26 seconds
Started Oct 15 11:27:50 AM UTC 24
Finished Oct 15 11:27:53 AM UTC 24
Peak memory 231956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289460372 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 98.edn_err.2289460372
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/98.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/98.edn_genbits.1783244610
Short name T689
Test name
Test status
Simulation time 37483592 ps
CPU time 1.7 seconds
Started Oct 15 11:27:50 AM UTC 24
Finished Oct 15 11:27:53 AM UTC 24
Peak memory 229908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783244610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 98.edn_genbits.1783244610
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/98.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/99.edn_alert.390898179
Short name T690
Test name
Test status
Simulation time 77186723 ps
CPU time 1.61 seconds
Started Oct 15 11:27:50 AM UTC 24
Finished Oct 15 11:27:53 AM UTC 24
Peak memory 232076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390898179 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 99.edn_alert.390898179
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/99.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/99.edn_err.3421283582
Short name T692
Test name
Test status
Simulation time 64971789 ps
CPU time 1.23 seconds
Started Oct 15 11:27:51 AM UTC 24
Finished Oct 15 11:27:54 AM UTC 24
Peak memory 227864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421283582 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 99.edn_err.3421283582
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/99.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/default/99.edn_genbits.3254287971
Short name T346
Test name
Test status
Simulation time 37414422 ps
CPU time 1.59 seconds
Started Oct 15 11:27:50 AM UTC 24
Finished Oct 15 11:27:53 AM UTC 24
Peak memory 231956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254287971 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 99.edn_genbits.3254287971
Directory /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/99.edn_genbits/latest
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