Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.61 98.25 93.91 97.02 91.86 96.37 99.77 92.06


Total test records in report: 1130
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
T293 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_rw.1811798909 Feb 09 01:56:09 PM UTC 25 Feb 09 01:56:11 PM UTC 25 38171126 ps
T1016 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/4.edn_tl_errors.2876159826 Feb 09 01:56:08 PM UTC 25 Feb 09 01:56:11 PM UTC 25 47056394 ps
T1017 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_hw_reset.2505591250 Feb 09 01:56:09 PM UTC 25 Feb 09 01:56:11 PM UTC 25 75695970 ps
T318 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/4.edn_tl_intg_err.27745332 Feb 09 01:56:09 PM UTC 25 Feb 09 01:56:12 PM UTC 25 176982030 ps
T281 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_aliasing.334614533 Feb 09 01:56:10 PM UTC 25 Feb 09 01:56:13 PM UTC 25 22918097 ps
T1018 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/3.edn_tl_errors.460304918 Feb 09 01:56:05 PM UTC 25 Feb 09 01:56:13 PM UTC 25 517976091 ps
T294 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/4.edn_same_csr_outstanding.3393200980 Feb 09 01:56:11 PM UTC 25 Feb 09 01:56:14 PM UTC 25 56799374 ps
T1019 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.892684605 Feb 09 01:56:11 PM UTC 25 Feb 09 01:56:14 PM UTC 25 111096070 ps
T282 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/5.edn_csr_rw.1531794469 Feb 09 01:56:13 PM UTC 25 Feb 09 01:56:15 PM UTC 25 27444108 ps
T1020 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/5.edn_intr_test.3588732318 Feb 09 01:56:13 PM UTC 25 Feb 09 01:56:15 PM UTC 25 30005330 ps
T1021 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/6.edn_intr_test.615171877 Feb 09 01:56:13 PM UTC 25 Feb 09 01:56:15 PM UTC 25 14670236 ps
T295 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/5.edn_same_csr_outstanding.214517448 Feb 09 01:56:13 PM UTC 25 Feb 09 01:56:15 PM UTC 25 50948344 ps
T1022 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_bit_bash.757367121 Feb 09 01:56:08 PM UTC 25 Feb 09 01:56:15 PM UTC 25 348553465 ps
T1023 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_intg_err.3132617168 Feb 09 01:56:13 PM UTC 25 Feb 09 01:56:16 PM UTC 25 44797481 ps
T1024 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1040048256 Feb 09 01:56:13 PM UTC 25 Feb 09 01:56:16 PM UTC 25 48251131 ps
T1025 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/6.edn_csr_rw.3794258849 Feb 09 01:56:14 PM UTC 25 Feb 09 01:56:16 PM UTC 25 34502094 ps
T296 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/6.edn_same_csr_outstanding.3526150688 Feb 09 01:56:14 PM UTC 25 Feb 09 01:56:16 PM UTC 25 26872113 ps
T317 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/5.edn_tl_intg_err.1372680139 Feb 09 01:56:12 PM UTC 25 Feb 09 01:56:17 PM UTC 25 71468754 ps
T1026 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_errors.2489957206 Feb 09 01:56:13 PM UTC 25 Feb 09 01:56:17 PM UTC 25 39952951 ps
T1027 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1305716418 Feb 09 01:56:20 PM UTC 25 Feb 09 01:56:22 PM UTC 25 31224259 ps
T1028 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/5.edn_tl_errors.1367212801 Feb 09 01:56:11 PM UTC 25 Feb 09 01:56:18 PM UTC 25 118606467 ps
T1029 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_errors.684528219 Feb 09 01:56:15 PM UTC 25 Feb 09 01:56:18 PM UTC 25 23430607 ps
T1030 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2423029249 Feb 09 01:56:15 PM UTC 25 Feb 09 01:56:18 PM UTC 25 50303202 ps
T1031 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_rw.3743040019 Feb 09 01:56:16 PM UTC 25 Feb 09 01:56:18 PM UTC 25 12945975 ps
T1032 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/7.edn_intr_test.1515648190 Feb 09 01:56:16 PM UTC 25 Feb 09 01:56:18 PM UTC 25 23707676 ps
T1033 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3242117102 Feb 09 01:56:16 PM UTC 25 Feb 09 01:56:19 PM UTC 25 20294407 ps
T1034 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_intg_err.3437040200 Feb 09 01:56:16 PM UTC 25 Feb 09 01:56:19 PM UTC 25 219483141 ps
T286 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_bit_bash.3782985807 Feb 09 01:56:09 PM UTC 25 Feb 09 01:56:19 PM UTC 25 611631385 ps
T1035 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/7.edn_same_csr_outstanding.2215685774 Feb 09 01:56:16 PM UTC 25 Feb 09 01:56:19 PM UTC 25 63608029 ps
T1036 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/8.edn_intr_test.1623506295 Feb 09 01:56:17 PM UTC 25 Feb 09 01:56:19 PM UTC 25 83966321 ps
T283 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_rw.1185936968 Feb 09 01:56:17 PM UTC 25 Feb 09 01:56:20 PM UTC 25 25393409 ps
T1037 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/8.edn_same_csr_outstanding.63854798 Feb 09 01:56:18 PM UTC 25 Feb 09 01:56:21 PM UTC 25 26561771 ps
T1038 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1614726554 Feb 09 01:56:18 PM UTC 25 Feb 09 01:56:21 PM UTC 25 35883610 ps
T1039 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_intg_err.1942028306 Feb 09 01:56:17 PM UTC 25 Feb 09 01:56:22 PM UTC 25 124838966 ps
T1040 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_intg_err.720359574 Feb 09 01:56:18 PM UTC 25 Feb 09 01:56:22 PM UTC 25 71674102 ps
T1041 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/9.edn_intr_test.4191567364 Feb 09 01:56:20 PM UTC 25 Feb 09 01:56:22 PM UTC 25 20050435 ps
T284 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_rw.3637737814 Feb 09 01:56:20 PM UTC 25 Feb 09 01:56:22 PM UTC 25 13730469 ps
T1042 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_errors.267604081 Feb 09 01:56:18 PM UTC 25 Feb 09 01:56:22 PM UTC 25 42311672 ps
T1043 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/9.edn_same_csr_outstanding.4285886888 Feb 09 01:56:20 PM UTC 25 Feb 09 01:56:22 PM UTC 25 56613538 ps
T1044 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_intg_err.3295536803 Feb 09 01:56:20 PM UTC 25 Feb 09 01:56:23 PM UTC 25 176106411 ps
T1045 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/10.edn_intr_test.3907736666 Feb 09 01:56:21 PM UTC 25 Feb 09 01:56:23 PM UTC 25 19894555 ps
T285 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_rw.1743972677 Feb 09 01:56:21 PM UTC 25 Feb 09 01:56:23 PM UTC 25 52187885 ps
T1046 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/10.edn_same_csr_outstanding.1170276136 Feb 09 01:56:21 PM UTC 25 Feb 09 01:56:24 PM UTC 25 53346931 ps
T1047 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_errors.2969369753 Feb 09 01:56:17 PM UTC 25 Feb 09 01:56:24 PM UTC 25 526935755 ps
T1048 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1531300456 Feb 09 01:56:22 PM UTC 25 Feb 09 01:56:25 PM UTC 25 17086319 ps
T1049 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_rw.664437475 Feb 09 01:56:23 PM UTC 25 Feb 09 01:56:25 PM UTC 25 60452812 ps
T1050 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/11.edn_intr_test.2618447709 Feb 09 01:56:23 PM UTC 25 Feb 09 01:56:25 PM UTC 25 16926120 ps
T1051 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/11.edn_same_csr_outstanding.3620016018 Feb 09 01:56:23 PM UTC 25 Feb 09 01:56:26 PM UTC 25 391698204 ps
T1052 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_errors.3164168103 Feb 09 01:56:20 PM UTC 25 Feb 09 01:56:26 PM UTC 25 181625422 ps
T1053 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.316299219 Feb 09 01:56:23 PM UTC 25 Feb 09 01:56:26 PM UTC 25 95574309 ps
T1054 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_intg_err.1342975478 Feb 09 01:56:23 PM UTC 25 Feb 09 01:56:27 PM UTC 25 162005424 ps
T1055 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/12.edn_intr_test.2596320324 Feb 09 01:56:24 PM UTC 25 Feb 09 01:56:27 PM UTC 25 43616422 ps
T289 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_rw.3014419342 Feb 09 01:56:24 PM UTC 25 Feb 09 01:56:27 PM UTC 25 19673322 ps
T1056 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/12.edn_same_csr_outstanding.672917445 Feb 09 01:56:24 PM UTC 25 Feb 09 01:56:27 PM UTC 25 64424031 ps
T1057 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_errors.2490931073 Feb 09 01:56:22 PM UTC 25 Feb 09 01:56:27 PM UTC 25 395850073 ps
T1058 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.2404938939 Feb 09 01:56:24 PM UTC 25 Feb 09 01:56:27 PM UTC 25 81728549 ps
T1059 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_errors.1649303931 Feb 09 01:56:23 PM UTC 25 Feb 09 01:56:28 PM UTC 25 227047687 ps
T1060 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_intg_err.4053054287 Feb 09 01:56:23 PM UTC 25 Feb 09 01:56:28 PM UTC 25 135840683 ps
T1061 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_errors.2427357037 Feb 09 01:56:26 PM UTC 25 Feb 09 01:56:29 PM UTC 25 116660911 ps
T1062 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/13.edn_intr_test.2133463048 Feb 09 01:56:27 PM UTC 25 Feb 09 01:56:29 PM UTC 25 51021686 ps
T1063 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_rw.882225922 Feb 09 01:56:27 PM UTC 25 Feb 09 01:56:29 PM UTC 25 14674996 ps
T1064 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_intg_err.4160335172 Feb 09 01:56:26 PM UTC 25 Feb 09 01:56:29 PM UTC 25 109588625 ps
T1065 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/13.edn_same_csr_outstanding.1837452182 Feb 09 01:56:27 PM UTC 25 Feb 09 01:56:29 PM UTC 25 14316039 ps
T1066 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_rw.1066206106 Feb 09 01:56:28 PM UTC 25 Feb 09 01:56:30 PM UTC 25 13036059 ps
T1067 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1808561051 Feb 09 01:56:27 PM UTC 25 Feb 09 01:56:30 PM UTC 25 362673657 ps
T1068 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_errors.3795356683 Feb 09 01:56:27 PM UTC 25 Feb 09 01:56:30 PM UTC 25 24868815 ps
T1069 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/14.edn_intr_test.2332726565 Feb 09 01:56:28 PM UTC 25 Feb 09 01:56:30 PM UTC 25 14786624 ps
T1070 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/14.edn_same_csr_outstanding.1419075361 Feb 09 01:56:28 PM UTC 25 Feb 09 01:56:31 PM UTC 25 19596716 ps
T1071 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_intg_err.4031180266 Feb 09 01:56:28 PM UTC 25 Feb 09 01:56:31 PM UTC 25 52092134 ps
T1072 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1610303114 Feb 09 01:56:28 PM UTC 25 Feb 09 01:56:32 PM UTC 25 158422531 ps
T1073 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/15.edn_intr_test.105360091 Feb 09 01:56:29 PM UTC 25 Feb 09 01:56:32 PM UTC 25 24357529 ps
T288 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_rw.2533350103 Feb 09 01:56:29 PM UTC 25 Feb 09 01:56:32 PM UTC 25 98824121 ps
T1074 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2875276509 Feb 09 01:56:30 PM UTC 25 Feb 09 01:56:33 PM UTC 25 27434632 ps
T1075 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/15.edn_same_csr_outstanding.899794947 Feb 09 01:56:30 PM UTC 25 Feb 09 01:56:33 PM UTC 25 110090460 ps
T1076 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_errors.3627075305 Feb 09 01:56:28 PM UTC 25 Feb 09 01:56:33 PM UTC 25 256055468 ps
T1077 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_intg_err.596368219 Feb 09 01:56:29 PM UTC 25 Feb 09 01:56:34 PM UTC 25 223336827 ps
T287 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_rw.3318240487 Feb 09 01:56:31 PM UTC 25 Feb 09 01:56:34 PM UTC 25 18326055 ps
T1078 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/16.edn_intr_test.123002286 Feb 09 01:56:31 PM UTC 25 Feb 09 01:56:34 PM UTC 25 11746918 ps
T1079 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/16.edn_same_csr_outstanding.429069311 Feb 09 01:56:32 PM UTC 25 Feb 09 01:56:34 PM UTC 25 62766768 ps
T1080 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_errors.840514055 Feb 09 01:56:30 PM UTC 25 Feb 09 01:56:34 PM UTC 25 112382856 ps
T1081 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_intg_err.3790343744 Feb 09 01:56:30 PM UTC 25 Feb 09 01:56:35 PM UTC 25 258757390 ps
T1082 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.224078503 Feb 09 01:56:32 PM UTC 25 Feb 09 01:56:35 PM UTC 25 109277625 ps
T1083 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/17.edn_intr_test.1557876168 Feb 09 01:56:33 PM UTC 25 Feb 09 01:56:35 PM UTC 25 15021224 ps
T1084 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_rw.3849666988 Feb 09 01:56:33 PM UTC 25 Feb 09 01:56:35 PM UTC 25 25866685 ps
T1085 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/17.edn_same_csr_outstanding.3379482162 Feb 09 01:56:33 PM UTC 25 Feb 09 01:56:36 PM UTC 25 120417517 ps
T1086 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_errors.3754521926 Feb 09 01:56:32 PM UTC 25 Feb 09 01:56:36 PM UTC 25 59410541 ps
T1087 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3487821618 Feb 09 01:56:34 PM UTC 25 Feb 09 01:56:37 PM UTC 25 36289846 ps
T1088 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_intg_err.3270809622 Feb 09 01:56:33 PM UTC 25 Feb 09 01:56:37 PM UTC 25 105037889 ps
T1089 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/18.edn_intr_test.145714090 Feb 09 01:56:35 PM UTC 25 Feb 09 01:56:37 PM UTC 25 14239892 ps
T1090 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_rw.2298231042 Feb 09 01:56:35 PM UTC 25 Feb 09 01:56:37 PM UTC 25 64136702 ps
T1091 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/18.edn_same_csr_outstanding.1744045332 Feb 09 01:56:35 PM UTC 25 Feb 09 01:56:38 PM UTC 25 35164978 ps
T1092 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_errors.1760869025 Feb 09 01:56:34 PM UTC 25 Feb 09 01:56:38 PM UTC 25 204024775 ps
T1093 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_intg_err.4180249086 Feb 09 01:56:34 PM UTC 25 Feb 09 01:56:39 PM UTC 25 89777131 ps
T1094 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1944750261 Feb 09 01:56:35 PM UTC 25 Feb 09 01:56:39 PM UTC 25 65684481 ps
T1095 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_rw.1480928917 Feb 09 01:56:36 PM UTC 25 Feb 09 01:56:39 PM UTC 25 48070361 ps
T1096 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/19.edn_intr_test.961651861 Feb 09 01:56:36 PM UTC 25 Feb 09 01:56:39 PM UTC 25 23507593 ps
T1097 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1030937623 Feb 09 01:56:36 PM UTC 25 Feb 09 01:56:39 PM UTC 25 26069859 ps
T1098 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/19.edn_same_csr_outstanding.906220212 Feb 09 01:56:36 PM UTC 25 Feb 09 01:56:39 PM UTC 25 317432558 ps
T1099 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/21.edn_intr_test.3368589390 Feb 09 01:56:37 PM UTC 25 Feb 09 01:56:40 PM UTC 25 13174131 ps
T1100 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/20.edn_intr_test.3769987071 Feb 09 01:56:37 PM UTC 25 Feb 09 01:56:40 PM UTC 25 28133905 ps
T1101 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_errors.3645338684 Feb 09 01:56:35 PM UTC 25 Feb 09 01:56:40 PM UTC 25 343692416 ps
T1102 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/22.edn_intr_test.556966390 Feb 09 01:56:38 PM UTC 25 Feb 09 01:56:40 PM UTC 25 26258462 ps
T1103 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/23.edn_intr_test.3814796864 Feb 09 01:56:39 PM UTC 25 Feb 09 01:56:41 PM UTC 25 22056655 ps
T1104 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_intg_err.3247464245 Feb 09 01:56:36 PM UTC 25 Feb 09 01:56:41 PM UTC 25 190996420 ps
T1105 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/25.edn_intr_test.3349452103 Feb 09 01:56:39 PM UTC 25 Feb 09 01:56:41 PM UTC 25 37542164 ps
T1106 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/24.edn_intr_test.299134570 Feb 09 01:56:39 PM UTC 25 Feb 09 01:56:41 PM UTC 25 20831041 ps
T1107 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/28.edn_intr_test.1401987775 Feb 09 01:56:40 PM UTC 25 Feb 09 01:56:42 PM UTC 25 40287766 ps
T1108 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/26.edn_intr_test.343858081 Feb 09 01:56:40 PM UTC 25 Feb 09 01:56:42 PM UTC 25 10768322 ps
T1109 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/29.edn_intr_test.1726547264 Feb 09 01:56:40 PM UTC 25 Feb 09 01:56:42 PM UTC 25 16916532 ps
T1110 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/27.edn_intr_test.1656639380 Feb 09 01:56:40 PM UTC 25 Feb 09 01:56:42 PM UTC 25 21574726 ps
T1111 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/31.edn_intr_test.1088439447 Feb 09 01:56:40 PM UTC 25 Feb 09 01:56:42 PM UTC 25 13055414 ps
T1112 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/30.edn_intr_test.1809678607 Feb 09 01:56:40 PM UTC 25 Feb 09 01:56:42 PM UTC 25 15233785 ps
T1113 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/32.edn_intr_test.3015901005 Feb 09 01:56:40 PM UTC 25 Feb 09 01:56:42 PM UTC 25 68747673 ps
T1114 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/34.edn_intr_test.1978177670 Feb 09 01:56:41 PM UTC 25 Feb 09 01:56:43 PM UTC 25 32696298 ps
T1115 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/35.edn_intr_test.395348109 Feb 09 01:56:41 PM UTC 25 Feb 09 01:56:43 PM UTC 25 13691358 ps
T1116 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/33.edn_intr_test.441079051 Feb 09 01:56:41 PM UTC 25 Feb 09 01:56:43 PM UTC 25 24695047 ps
T1117 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/38.edn_intr_test.1928903564 Feb 09 01:56:41 PM UTC 25 Feb 09 01:56:44 PM UTC 25 36199927 ps
T1118 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/37.edn_intr_test.68267504 Feb 09 01:56:41 PM UTC 25 Feb 09 01:56:44 PM UTC 25 18366936 ps
T1119 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/36.edn_intr_test.3966058367 Feb 09 01:56:41 PM UTC 25 Feb 09 01:56:44 PM UTC 25 17506692 ps
T1120 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/39.edn_intr_test.3833661349 Feb 09 01:56:42 PM UTC 25 Feb 09 01:56:45 PM UTC 25 14862912 ps
T1121 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/40.edn_intr_test.764393654 Feb 09 01:56:42 PM UTC 25 Feb 09 01:56:45 PM UTC 25 14486371 ps
T1122 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/44.edn_intr_test.1133402308 Feb 09 01:56:43 PM UTC 25 Feb 09 01:56:46 PM UTC 25 43997575 ps
T1123 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/41.edn_intr_test.390369879 Feb 09 01:56:43 PM UTC 25 Feb 09 01:56:46 PM UTC 25 41496152 ps
T1124 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/43.edn_intr_test.2981519473 Feb 09 01:56:43 PM UTC 25 Feb 09 01:56:46 PM UTC 25 59263139 ps
T1125 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/42.edn_intr_test.4092798148 Feb 09 01:56:43 PM UTC 25 Feb 09 01:56:46 PM UTC 25 40266247 ps
T1126 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/45.edn_intr_test.78626708 Feb 09 01:56:44 PM UTC 25 Feb 09 01:56:46 PM UTC 25 114995898 ps
T1127 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/46.edn_intr_test.3752239739 Feb 09 01:56:44 PM UTC 25 Feb 09 01:56:46 PM UTC 25 15382953 ps
T1128 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/47.edn_intr_test.2450671796 Feb 09 01:56:44 PM UTC 25 Feb 09 01:56:46 PM UTC 25 28462131 ps
T1129 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/48.edn_intr_test.3576734942 Feb 09 01:56:45 PM UTC 25 Feb 09 01:56:47 PM UTC 25 11843495 ps
T1130 /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/49.edn_intr_test.1290742324 Feb 09 01:56:45 PM UTC 25 Feb 09 01:56:47 PM UTC 25 16245364 ps

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/0.edn_disable_auto_req_mode.761749351
Short name T10
Test name
Test status
Simulation time 128685941 ps
CPU time 1.81 seconds
Started Feb 09 01:27:53 PM UTC 25
Finished Feb 09 01:27:56 PM UTC 25
Peak memory 226076 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761749351 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_re
q_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable_auto_req_mode.761749351
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/0.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/0.edn_genbits.2955157580
Short name T3
Test name
Test status
Simulation time 91692391 ps
CPU time 1.86 seconds
Started Feb 09 01:27:40 PM UTC 25
Finished Feb 09 01:27:43 PM UTC 25
Peak memory 228260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955157580 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.edn_genbits.2955157580
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/0.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/2.edn_sec_cm.3377715431
Short name T18
Test name
Test status
Simulation time 380970378 ps
CPU time 4.68 seconds
Started Feb 09 01:28:37 PM UTC 25
Finished Feb 09 01:28:43 PM UTC 25
Peak memory 260460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377715431 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM
_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.3377715431
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/2.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/1.edn_alert.2076671121
Short name T28
Test name
Test status
Simulation time 29645023 ps
CPU time 1.85 seconds
Started Feb 09 01:28:13 PM UTC 25
Finished Feb 09 01:28:16 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076671121 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 1.edn_alert.2076671121
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/1.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/2.edn_stress_all.961047750
Short name T57
Test name
Test status
Simulation time 914644484 ps
CPU time 4.01 seconds
Started Feb 09 01:28:25 PM UTC 25
Finished Feb 09 01:28:31 PM UTC 25
Peak memory 227232 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961047750 -assert nopostproc +UVM_TESTNAME=edn_stress_all_
test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.961047750
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/2.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/1.edn_stress_all_with_rand_reset.981045686
Short name T37
Test name
Test status
Simulation time 29879418012 ps
CPU time 411.67 seconds
Started Feb 09 01:28:07 PM UTC 25
Finished Feb 09 01:35:05 PM UTC 25
Peak memory 234172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=981045686 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.981045686
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/1.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/9.edn_alert.2252961129
Short name T86
Test name
Test status
Simulation time 50695542 ps
CPU time 1.86 seconds
Started Feb 09 01:30:46 PM UTC 25
Finished Feb 09 01:30:49 PM UTC 25
Peak memory 228320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252961129 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 9.edn_alert.2252961129
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/9.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/7.edn_stress_all.4171457072
Short name T119
Test name
Test status
Simulation time 417326635 ps
CPU time 8.7 seconds
Started Feb 09 01:30:07 PM UTC 25
Finished Feb 09 01:30:17 PM UTC 25
Peak memory 231580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171457072 -assert nopostproc +UVM_TESTNAME=edn_stress_all
_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.4171457072
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/7.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/5.edn_genbits.2789326428
Short name T20
Test name
Test status
Simulation time 173475753 ps
CPU time 2.09 seconds
Started Feb 09 01:29:38 PM UTC 25
Finished Feb 09 01:29:42 PM UTC 25
Peak memory 227364 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789326428 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.edn_genbits.2789326428
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/5.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/7.edn_alert.2902394555
Short name T42
Test name
Test status
Simulation time 45220931 ps
CPU time 1.71 seconds
Started Feb 09 01:30:10 PM UTC 25
Finished Feb 09 01:30:13 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902394555 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 7.edn_alert.2902394555
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/7.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/0.edn_regwen.833617746
Short name T2
Test name
Test status
Simulation time 24763674 ps
CPU time 1.39 seconds
Started Feb 09 01:27:39 PM UTC 25
Finished Feb 09 01:27:42 PM UTC 25
Peak memory 215912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833617746 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 0.edn_regwen.833617746
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/0.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/12.edn_alert.2969741561
Short name T125
Test name
Test status
Simulation time 22434510 ps
CPU time 1.66 seconds
Started Feb 09 01:31:23 PM UTC 25
Finished Feb 09 01:31:26 PM UTC 25
Peak memory 228316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969741561 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 12.edn_alert.2969741561
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/12.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/5.edn_disable_auto_req_mode.505576517
Short name T21
Test name
Test status
Simulation time 62042961 ps
CPU time 2.46 seconds
Started Feb 09 01:29:48 PM UTC 25
Finished Feb 09 01:29:52 PM UTC 25
Peak memory 232124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505576517 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_re
q_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable_auto_req_mode.505576517
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/5.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/0.edn_intr.3799671637
Short name T5
Test name
Test status
Simulation time 43583115 ps
CPU time 1.29 seconds
Started Feb 09 01:27:45 PM UTC 25
Finished Feb 09 01:27:48 PM UTC 25
Peak memory 228260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799671637 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 0.edn_intr.3799671637
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/0.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/2.edn_disable.788948164
Short name T45
Test name
Test status
Simulation time 12614945 ps
CPU time 1.37 seconds
Started Feb 09 01:28:34 PM UTC 25
Finished Feb 09 01:28:37 PM UTC 25
Peak memory 230108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788948164 -assert nopostproc +UVM_TESTNAME=edn_disable_test +U
VM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.edn_disable.788948164
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/2.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/1.edn_disable_auto_req_mode.2650717517
Short name T14
Test name
Test status
Simulation time 58894463 ps
CPU time 1.76 seconds
Started Feb 09 01:28:17 PM UTC 25
Finished Feb 09 01:28:20 PM UTC 25
Peak memory 228124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650717517 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_r
eq_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable_auto_req_mode.2650717517
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/1.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/3.edn_tl_intg_err.4288847070
Short name T316
Test name
Test status
Simulation time 174867440 ps
CPU time 2.87 seconds
Started Feb 09 01:56:05 PM UTC 25
Finished Feb 09 01:56:09 PM UTC 25
Peak memory 217788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288847070 -assert nopostproc +UVM_TESTNAME=edn_base_t
est +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.4288847070
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/3.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/9.edn_disable.1921543983
Short name T82
Test name
Test status
Simulation time 38590965 ps
CPU time 1.31 seconds
Started Feb 09 01:30:47 PM UTC 25
Finished Feb 09 01:30:50 PM UTC 25
Peak memory 226012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921543983 -assert nopostproc +UVM_TESTNAME=edn_disable_test +
UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.edn_disable.1921543983
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/9.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_aliasing.89969614
Short name T274
Test name
Test status
Simulation time 383122078 ps
CPU time 2.41 seconds
Started Feb 09 01:55:58 PM UTC 25
Finished Feb 09 01:56:02 PM UTC 25
Peak memory 217728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89969614 -assert nopostproc +UVM_TESTNAME=edn_base_test +
UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.89969614
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/0.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/36.edn_disable.2608551994
Short name T211
Test name
Test status
Simulation time 24280290 ps
CPU time 1.18 seconds
Started Feb 09 01:45:52 PM UTC 25
Finished Feb 09 01:45:55 PM UTC 25
Peak memory 226012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608551994 -assert nopostproc +UVM_TESTNAME=edn_disable_test +
UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.edn_disable.2608551994
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/36.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/22.edn_err.3065529542
Short name T194
Test name
Test status
Simulation time 22488828 ps
CPU time 1.58 seconds
Started Feb 09 01:38:51 PM UTC 25
Finished Feb 09 01:38:53 PM UTC 25
Peak memory 236856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065529542 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 22.edn_err.3065529542
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/22.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/2.edn_alert_test.1425272683
Short name T66
Test name
Test status
Simulation time 24249169 ps
CPU time 1.46 seconds
Started Feb 09 01:28:38 PM UTC 25
Finished Feb 09 01:28:41 PM UTC 25
Peak memory 226692 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425272683 -assert nopostproc +UVM_TESTNAME=edn_base_test +UV
M_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.1425272683
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/2.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/62.edn_alert.3247844487
Short name T301
Test name
Test status
Simulation time 88357050 ps
CPU time 1.65 seconds
Started Feb 09 01:52:57 PM UTC 25
Finished Feb 09 01:53:00 PM UTC 25
Peak memory 228320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247844487 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 62.edn_alert.3247844487
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/62.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/6.edn_alert.1362713263
Short name T47
Test name
Test status
Simulation time 25190413 ps
CPU time 1.66 seconds
Started Feb 09 01:29:58 PM UTC 25
Finished Feb 09 01:30:01 PM UTC 25
Peak memory 228260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362713263 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 6.edn_alert.1362713263
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/6.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/13.edn_stress_all_with_rand_reset.759107806
Short name T340
Test name
Test status
Simulation time 47936300888 ps
CPU time 1195.79 seconds
Started Feb 09 01:31:38 PM UTC 25
Finished Feb 09 01:51:47 PM UTC 25
Peak memory 231844 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=759107806 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.759107806
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/13.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/48.edn_alert.2325791123
Short name T170
Test name
Test status
Simulation time 40183381 ps
CPU time 1.77 seconds
Started Feb 09 01:51:59 PM UTC 25
Finished Feb 09 01:52:02 PM UTC 25
Peak memory 228196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325791123 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 48.edn_alert.2325791123
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/48.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/0.edn_alert.439039609
Short name T9
Test name
Test status
Simulation time 36829101 ps
CPU time 1.63 seconds
Started Feb 09 01:27:48 PM UTC 25
Finished Feb 09 01:27:51 PM UTC 25
Peak memory 228320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439039609 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 0.edn_alert.439039609
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/0.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/28.edn_alert.1110876134
Short name T85
Test name
Test status
Simulation time 404423435 ps
CPU time 2.57 seconds
Started Feb 09 01:42:39 PM UTC 25
Finished Feb 09 01:42:43 PM UTC 25
Peak memory 231792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110876134 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 28.edn_alert.1110876134
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/28.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/24.edn_genbits.1668839324
Short name T333
Test name
Test status
Simulation time 91678629 ps
CPU time 2 seconds
Started Feb 09 01:39:42 PM UTC 25
Finished Feb 09 01:39:45 PM UTC 25
Peak memory 230312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668839324 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.edn_genbits.1668839324
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/24.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/5.edn_alert.4229344434
Short name T118
Test name
Test status
Simulation time 33647949 ps
CPU time 1.73 seconds
Started Feb 09 01:29:44 PM UTC 25
Finished Feb 09 01:29:47 PM UTC 25
Peak memory 232416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229344434 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 5.edn_alert.4229344434
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/5.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/10.edn_disable_auto_req_mode.2122094604
Short name T166
Test name
Test status
Simulation time 33229475 ps
CPU time 1.81 seconds
Started Feb 09 01:31:03 PM UTC 25
Finished Feb 09 01:31:06 PM UTC 25
Peak memory 230168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122094604 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_r
eq_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable_auto_req_mode.2122094604
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/10.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/108.edn_alert.694473060
Short name T706
Test name
Test status
Simulation time 166949174 ps
CPU time 1.75 seconds
Started Feb 09 01:54:00 PM UTC 25
Finished Feb 09 01:54:03 PM UTC 25
Peak memory 230284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694473060 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 108.edn_alert.694473060
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/108.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/145.edn_alert.1000262452
Short name T777
Test name
Test status
Simulation time 91162035 ps
CPU time 1.71 seconds
Started Feb 09 01:54:34 PM UTC 25
Finished Feb 09 01:54:37 PM UTC 25
Peak memory 228320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000262452 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 145.edn_alert.1000262452
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/145.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/150.edn_alert.1194208627
Short name T790
Test name
Test status
Simulation time 38732658 ps
CPU time 1.62 seconds
Started Feb 09 01:54:40 PM UTC 25
Finished Feb 09 01:54:43 PM UTC 25
Peak memory 230352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194208627 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 150.edn_alert.1194208627
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/150.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/91.edn_alert.1662794845
Short name T680
Test name
Test status
Simulation time 202431318 ps
CPU time 1.79 seconds
Started Feb 09 01:53:42 PM UTC 25
Finished Feb 09 01:53:45 PM UTC 25
Peak memory 230304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662794845 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 91.edn_alert.1662794845
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/91.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/4.edn_disable_auto_req_mode.970573087
Short name T46
Test name
Test status
Simulation time 40776045 ps
CPU time 2 seconds
Started Feb 09 01:29:25 PM UTC 25
Finished Feb 09 01:29:29 PM UTC 25
Peak memory 228120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970573087 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_re
q_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable_auto_req_mode.970573087
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/4.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/68.edn_genbits.2280517082
Short name T627
Test name
Test status
Simulation time 39990179 ps
CPU time 2.08 seconds
Started Feb 09 01:53:08 PM UTC 25
Finished Feb 09 01:53:11 PM UTC 25
Peak memory 231544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280517082 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 68.edn_genbits.2280517082
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/68.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/18.edn_disable.1886067825
Short name T229
Test name
Test status
Simulation time 19080066 ps
CPU time 1.31 seconds
Started Feb 09 01:35:15 PM UTC 25
Finished Feb 09 01:35:18 PM UTC 25
Peak memory 226272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886067825 -assert nopostproc +UVM_TESTNAME=edn_disable_test +
UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.edn_disable.1886067825
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/18.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/14.edn_intr.2578488517
Short name T35
Test name
Test status
Simulation time 21920969 ps
CPU time 1.64 seconds
Started Feb 09 01:32:20 PM UTC 25
Finished Feb 09 01:32:23 PM UTC 25
Peak memory 228256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578488517 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 14.edn_intr.2578488517
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/14.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/121.edn_alert.4203118090
Short name T730
Test name
Test status
Simulation time 44412683 ps
CPU time 1.72 seconds
Started Feb 09 01:54:11 PM UTC 25
Finished Feb 09 01:54:14 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203118090 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 121.edn_alert.4203118090
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/121.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/129.edn_alert.147901121
Short name T153
Test name
Test status
Simulation time 52129144 ps
CPU time 1.8 seconds
Started Feb 09 01:54:20 PM UTC 25
Finished Feb 09 01:54:23 PM UTC 25
Peak memory 230364 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147901121 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 129.edn_alert.147901121
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/129.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/13.edn_disable_auto_req_mode.2498645430
Short name T94
Test name
Test status
Simulation time 183128675 ps
CPU time 1.55 seconds
Started Feb 09 01:32:01 PM UTC 25
Finished Feb 09 01:32:04 PM UTC 25
Peak memory 228128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498645430 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_r
eq_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable_auto_req_mode.2498645430
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/13.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/14.edn_disable.2891451026
Short name T96
Test name
Test status
Simulation time 11418094 ps
CPU time 1.29 seconds
Started Feb 09 01:32:31 PM UTC 25
Finished Feb 09 01:32:33 PM UTC 25
Peak memory 226012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891451026 -assert nopostproc +UVM_TESTNAME=edn_disable_test +
UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.edn_disable.2891451026
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/14.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/15.edn_disable_auto_req_mode.541668785
Short name T120
Test name
Test status
Simulation time 40398210 ps
CPU time 1.79 seconds
Started Feb 09 01:33:20 PM UTC 25
Finished Feb 09 01:33:23 PM UTC 25
Peak memory 230472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541668785 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_re
q_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable_auto_req_mode.541668785
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/15.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/19.edn_disable_auto_req_mode.706971057
Short name T223
Test name
Test status
Simulation time 80696793 ps
CPU time 1.6 seconds
Started Feb 09 01:35:35 PM UTC 25
Finished Feb 09 01:35:38 PM UTC 25
Peak memory 228124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706971057 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_re
q_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable_auto_req_mode.706971057
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/19.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/31.edn_alert.3954936024
Short name T178
Test name
Test status
Simulation time 223307401 ps
CPU time 1.91 seconds
Started Feb 09 01:43:36 PM UTC 25
Finished Feb 09 01:43:39 PM UTC 25
Peak memory 228320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954936024 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 31.edn_alert.3954936024
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/31.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/35.edn_disable.4158574589
Short name T210
Test name
Test status
Simulation time 33052101 ps
CPU time 1.28 seconds
Started Feb 09 01:45:29 PM UTC 25
Finished Feb 09 01:45:31 PM UTC 25
Peak memory 230116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158574589 -assert nopostproc +UVM_TESTNAME=edn_disable_test +
UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.edn_disable.4158574589
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/35.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/44.edn_err.29994019
Short name T207
Test name
Test status
Simulation time 29284094 ps
CPU time 1.32 seconds
Started Feb 09 01:50:41 PM UTC 25
Finished Feb 09 01:50:43 PM UTC 25
Peak memory 230304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29994019 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 44.edn_err.29994019
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/44.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/69.edn_err.341345365
Short name T204
Test name
Test status
Simulation time 19504567 ps
CPU time 1.56 seconds
Started Feb 09 01:53:10 PM UTC 25
Finished Feb 09 01:53:13 PM UTC 25
Peak memory 228084 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341345365 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na
me 69.edn_err.341345365
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/69.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/60.edn_genbits.3138177963
Short name T352
Test name
Test status
Simulation time 62320318 ps
CPU time 2.15 seconds
Started Feb 09 01:52:51 PM UTC 25
Finished Feb 09 01:52:54 PM UTC 25
Peak memory 231664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138177963 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 60.edn_genbits.3138177963
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/60.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/35.edn_stress_all.2250498461
Short name T256
Test name
Test status
Simulation time 1413000688 ps
CPU time 7.9 seconds
Started Feb 09 01:45:11 PM UTC 25
Finished Feb 09 01:45:20 PM UTC 25
Peak memory 229416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250498461 -assert nopostproc +UVM_TESTNAME=edn_stress_all
_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.2250498461
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/35.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/11.edn_genbits.1139793390
Short name T78
Test name
Test status
Simulation time 32692032 ps
CPU time 1.84 seconds
Started Feb 09 01:31:07 PM UTC 25
Finished Feb 09 01:31:10 PM UTC 25
Peak memory 226048 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139793390 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.edn_genbits.1139793390
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/11.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/64.edn_alert.1467351107
Short name T320
Test name
Test status
Simulation time 73634579 ps
CPU time 1.75 seconds
Started Feb 09 01:53:02 PM UTC 25
Finished Feb 09 01:53:05 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467351107 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 64.edn_alert.1467351107
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/64.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/10.edn_stress_all_with_rand_reset.2310145831
Short name T38
Test name
Test status
Simulation time 10754431244 ps
CPU time 257.37 seconds
Started Feb 09 01:30:54 PM UTC 25
Finished Feb 09 01:35:15 PM UTC 25
Peak memory 233792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2310145831 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.2310145831
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/10.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/9.edn_genbits.1346774189
Short name T41
Test name
Test status
Simulation time 84482989 ps
CPU time 2.02 seconds
Started Feb 09 01:30:38 PM UTC 25
Finished Feb 09 01:30:42 PM UTC 25
Peak memory 229616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346774189 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.edn_genbits.1346774189
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/9.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/26.edn_intr.1869842528
Short name T105
Test name
Test status
Simulation time 21955541 ps
CPU time 1.55 seconds
Started Feb 09 01:42:08 PM UTC 25
Finished Feb 09 01:42:11 PM UTC 25
Peak memory 228256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869842528 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 26.edn_intr.1869842528
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/26.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/0.edn_same_csr_outstanding.1680023189
Short name T273
Test name
Test status
Simulation time 51893398 ps
CPU time 1.94 seconds
Started Feb 09 01:55:58 PM UTC 25
Finished Feb 09 01:56:01 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680023189 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_outstanding.1680023189
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/0.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/1.edn_genbits.2986945351
Short name T30
Test name
Test status
Simulation time 36600571 ps
CPU time 2.29 seconds
Started Feb 09 01:28:03 PM UTC 25
Finished Feb 09 01:28:07 PM UTC 25
Peak memory 229596 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986945351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.edn_genbits.2986945351
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/1.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/100.edn_genbits.3758118685
Short name T351
Test name
Test status
Simulation time 125996843 ps
CPU time 2.37 seconds
Started Feb 09 01:53:53 PM UTC 25
Finished Feb 09 01:53:57 PM UTC 25
Peak memory 229352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758118685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 100.edn_genbits.3758118685
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/100.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/105.edn_alert.99225164
Short name T703
Test name
Test status
Simulation time 31297665 ps
CPU time 1.81 seconds
Started Feb 09 01:53:58 PM UTC 25
Finished Feb 09 01:54:01 PM UTC 25
Peak memory 230308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99225164 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 105.edn_alert.99225164
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/105.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/111.edn_genbits.3709577709
Short name T336
Test name
Test status
Simulation time 63605704 ps
CPU time 2.1 seconds
Started Feb 09 01:54:02 PM UTC 25
Finished Feb 09 01:54:05 PM UTC 25
Peak memory 229368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709577709 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 111.edn_genbits.3709577709
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/111.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/142.edn_genbits.2328613310
Short name T770
Test name
Test status
Simulation time 55790004 ps
CPU time 1.73 seconds
Started Feb 09 01:54:30 PM UTC 25
Finished Feb 09 01:54:33 PM UTC 25
Peak memory 230348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328613310 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 142.edn_genbits.2328613310
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/142.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/154.edn_genbits.3794632733
Short name T341
Test name
Test status
Simulation time 45170806 ps
CPU time 2.06 seconds
Started Feb 09 01:54:43 PM UTC 25
Finished Feb 09 01:54:46 PM UTC 25
Peak memory 229648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794632733 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 154.edn_genbits.3794632733
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/154.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/171.edn_genbits.105780886
Short name T338
Test name
Test status
Simulation time 256187127 ps
CPU time 5.75 seconds
Started Feb 09 01:54:59 PM UTC 25
Finished Feb 09 01:55:06 PM UTC 25
Peak memory 231396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105780886 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 171.edn_genbits.105780886
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/171.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/190.edn_genbits.2163463742
Short name T348
Test name
Test status
Simulation time 83369093 ps
CPU time 1.71 seconds
Started Feb 09 01:55:12 PM UTC 25
Finished Feb 09 01:55:15 PM UTC 25
Peak memory 230312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163463742 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 190.edn_genbits.2163463742
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/190.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/34.edn_intr.2723263884
Short name T104
Test name
Test status
Simulation time 20791034 ps
CPU time 1.28 seconds
Started Feb 09 01:44:57 PM UTC 25
Finished Feb 09 01:44:59 PM UTC 25
Peak memory 228376 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723263884 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 34.edn_intr.2723263884
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/34.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/143.edn_alert.3513460610
Short name T132
Test name
Test status
Simulation time 123151507 ps
CPU time 1.82 seconds
Started Feb 09 01:54:33 PM UTC 25
Finished Feb 09 01:54:36 PM UTC 25
Peak memory 228320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513460610 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 143.edn_alert.3513460610
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/143.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/0.edn_err.1849713860
Short name T6
Test name
Test status
Simulation time 26041640 ps
CPU time 1.8 seconds
Started Feb 09 01:27:48 PM UTC 25
Finished Feb 09 01:27:51 PM UTC 25
Peak memory 230296 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849713860 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 0.edn_err.1849713860
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/0.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_bit_bash.430180449
Short name T1004
Test name
Test status
Simulation time 187780715 ps
CPU time 4.36 seconds
Started Feb 09 01:55:58 PM UTC 25
Finished Feb 09 01:56:04 PM UTC 25
Peak memory 217512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430180449 -assert nopostproc +UVM_TESTNAME=edn_base_test
+UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.430180449
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/0.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_hw_reset.3857078192
Short name T998
Test name
Test status
Simulation time 93255438 ps
CPU time 1.31 seconds
Started Feb 09 01:55:57 PM UTC 25
Finished Feb 09 01:56:00 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857078192 -assert nopostproc +UVM_TESTNAME=edn_base_test
+UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.3857078192
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/0.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3882822762
Short name T1000
Test name
Test status
Simulation time 86522390 ps
CPU time 1.65 seconds
Started Feb 09 01:55:59 PM UTC 25
Finished Feb 09 01:56:02 PM UTC 25
Peak memory 226032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882822762
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.3882822762
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_rw.1035092107
Short name T999
Test name
Test status
Simulation time 40191958 ps
CPU time 1.28 seconds
Started Feb 09 01:55:57 PM UTC 25
Finished Feb 09 01:56:00 PM UTC 25
Peak memory 215724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035092107 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_
TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.1035092107
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/0.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/0.edn_intr_test.398925662
Short name T997
Test name
Test status
Simulation time 13817555 ps
CPU time 1.28 seconds
Started Feb 09 01:55:57 PM UTC 25
Finished Feb 09 01:55:59 PM UTC 25
Peak memory 215732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398925662 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST
_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.398925662
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/0.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/0.edn_tl_errors.1782689634
Short name T996
Test name
Test status
Simulation time 26016287 ps
CPU time 2.35 seconds
Started Feb 09 01:55:56 PM UTC 25
Finished Feb 09 01:55:59 PM UTC 25
Peak memory 228100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782689634 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.1782689634
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/0.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/0.edn_tl_intg_err.3299015903
Short name T303
Test name
Test status
Simulation time 120142638 ps
CPU time 2.97 seconds
Started Feb 09 01:55:57 PM UTC 25
Finished Feb 09 01:56:01 PM UTC 25
Peak memory 217764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299015903 -assert nopostproc +UVM_TESTNAME=edn_base_t
est +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.3299015903
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/0.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_aliasing.123720449
Short name T1005
Test name
Test status
Simulation time 73613909 ps
CPU time 2.19 seconds
Started Feb 09 01:56:00 PM UTC 25
Finished Feb 09 01:56:04 PM UTC 25
Peak memory 217540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123720449 -assert nopostproc +UVM_TESTNAME=edn_base_test
+UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.123720449
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/1.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_bit_bash.3189267574
Short name T1009
Test name
Test status
Simulation time 110590459 ps
CPU time 4.54 seconds
Started Feb 09 01:56:00 PM UTC 25
Finished Feb 09 01:56:06 PM UTC 25
Peak memory 217520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189267574 -assert nopostproc +UVM_TESTNAME=edn_base_test
+UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.3189267574
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/1.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_hw_reset.3910438725
Short name T275
Test name
Test status
Simulation time 17572408 ps
CPU time 1.4 seconds
Started Feb 09 01:56:00 PM UTC 25
Finished Feb 09 01:56:03 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910438725 -assert nopostproc +UVM_TESTNAME=edn_base_test
+UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.3910438725
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/1.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3686657973
Short name T1006
Test name
Test status
Simulation time 33841129 ps
CPU time 1.92 seconds
Started Feb 09 01:56:02 PM UTC 25
Finished Feb 09 01:56:05 PM UTC 25
Peak memory 226032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686657973
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.3686657973
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_rw.1644743575
Short name T1002
Test name
Test status
Simulation time 57764776 ps
CPU time 1.39 seconds
Started Feb 09 01:56:00 PM UTC 25
Finished Feb 09 01:56:03 PM UTC 25
Peak memory 215724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644743575 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_
TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.1644743575
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/1.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/1.edn_intr_test.2748931908
Short name T1001
Test name
Test status
Simulation time 26575077 ps
CPU time 1.33 seconds
Started Feb 09 01:56:00 PM UTC 25
Finished Feb 09 01:56:03 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748931908 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.2748931908
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/1.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/1.edn_same_csr_outstanding.1512960862
Short name T276
Test name
Test status
Simulation time 59120204 ps
CPU time 1.16 seconds
Started Feb 09 01:56:01 PM UTC 25
Finished Feb 09 01:56:04 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512960862 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_outstanding.1512960862
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/1.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/1.edn_tl_errors.3074987780
Short name T1003
Test name
Test status
Simulation time 60340319 ps
CPU time 2.69 seconds
Started Feb 09 01:55:59 PM UTC 25
Finished Feb 09 01:56:03 PM UTC 25
Peak memory 227948 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074987780 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.3074987780
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/1.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/1.edn_tl_intg_err.1657211579
Short name T304
Test name
Test status
Simulation time 242160186 ps
CPU time 2.27 seconds
Started Feb 09 01:55:59 PM UTC 25
Finished Feb 09 01:56:03 PM UTC 25
Peak memory 217740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657211579 -assert nopostproc +UVM_TESTNAME=edn_base_t
est +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.1657211579
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/1.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1531300456
Short name T1048
Test name
Test status
Simulation time 17086319 ps
CPU time 1.55 seconds
Started Feb 09 01:56:22 PM UTC 25
Finished Feb 09 01:56:25 PM UTC 25
Peak memory 226032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531300456
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.1531300456
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_rw.1743972677
Short name T285
Test name
Test status
Simulation time 52187885 ps
CPU time 1.36 seconds
Started Feb 09 01:56:21 PM UTC 25
Finished Feb 09 01:56:23 PM UTC 25
Peak memory 215792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743972677 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_
TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.1743972677
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/10.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/10.edn_intr_test.3907736666
Short name T1045
Test name
Test status
Simulation time 19894555 ps
CPU time 1.26 seconds
Started Feb 09 01:56:21 PM UTC 25
Finished Feb 09 01:56:23 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907736666 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.3907736666
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/10.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/10.edn_same_csr_outstanding.1170276136
Short name T1046
Test name
Test status
Simulation time 53346931 ps
CPU time 1.65 seconds
Started Feb 09 01:56:21 PM UTC 25
Finished Feb 09 01:56:24 PM UTC 25
Peak memory 215728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170276136 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_outstanding.1170276136
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/10.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_errors.3164168103
Short name T1052
Test name
Test status
Simulation time 181625422 ps
CPU time 4.99 seconds
Started Feb 09 01:56:20 PM UTC 25
Finished Feb 09 01:56:26 PM UTC 25
Peak memory 227884 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164168103 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.3164168103
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/10.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_intg_err.3295536803
Short name T1044
Test name
Test status
Simulation time 176106411 ps
CPU time 2.05 seconds
Started Feb 09 01:56:20 PM UTC 25
Finished Feb 09 01:56:23 PM UTC 25
Peak memory 217836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295536803 -assert nopostproc +UVM_TESTNAME=edn_base_t
est +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.3295536803
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/10.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.316299219
Short name T1053
Test name
Test status
Simulation time 95574309 ps
CPU time 1.71 seconds
Started Feb 09 01:56:23 PM UTC 25
Finished Feb 09 01:56:26 PM UTC 25
Peak memory 226028 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316299219
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.316299219
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_rw.664437475
Short name T1049
Test name
Test status
Simulation time 60452812 ps
CPU time 1.28 seconds
Started Feb 09 01:56:23 PM UTC 25
Finished Feb 09 01:56:25 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664437475 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_T
EST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.664437475
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/11.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/11.edn_intr_test.2618447709
Short name T1050
Test name
Test status
Simulation time 16926120 ps
CPU time 1.25 seconds
Started Feb 09 01:56:23 PM UTC 25
Finished Feb 09 01:56:25 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618447709 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.2618447709
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/11.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/11.edn_same_csr_outstanding.3620016018
Short name T1051
Test name
Test status
Simulation time 391698204 ps
CPU time 1.61 seconds
Started Feb 09 01:56:23 PM UTC 25
Finished Feb 09 01:56:26 PM UTC 25
Peak memory 215728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620016018 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_outstanding.3620016018
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/11.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_errors.2490931073
Short name T1057
Test name
Test status
Simulation time 395850073 ps
CPU time 4.22 seconds
Started Feb 09 01:56:22 PM UTC 25
Finished Feb 09 01:56:27 PM UTC 25
Peak memory 227944 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490931073 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.2490931073
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/11.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_intg_err.4053054287
Short name T1060
Test name
Test status
Simulation time 135840683 ps
CPU time 4 seconds
Started Feb 09 01:56:23 PM UTC 25
Finished Feb 09 01:56:28 PM UTC 25
Peak memory 217628 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053054287 -assert nopostproc +UVM_TESTNAME=edn_base_t
est +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.4053054287
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/11.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.2404938939
Short name T1058
Test name
Test status
Simulation time 81728549 ps
CPU time 1.86 seconds
Started Feb 09 01:56:24 PM UTC 25
Finished Feb 09 01:56:27 PM UTC 25
Peak memory 226032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404938939
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.2404938939
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_rw.3014419342
Short name T289
Test name
Test status
Simulation time 19673322 ps
CPU time 1.42 seconds
Started Feb 09 01:56:24 PM UTC 25
Finished Feb 09 01:56:27 PM UTC 25
Peak memory 215620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014419342 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_
TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.3014419342
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/12.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/12.edn_intr_test.2596320324
Short name T1055
Test name
Test status
Simulation time 43616422 ps
CPU time 1.32 seconds
Started Feb 09 01:56:24 PM UTC 25
Finished Feb 09 01:56:27 PM UTC 25
Peak memory 215552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596320324 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.2596320324
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/12.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/12.edn_same_csr_outstanding.672917445
Short name T1056
Test name
Test status
Simulation time 64424031 ps
CPU time 1.67 seconds
Started Feb 09 01:56:24 PM UTC 25
Finished Feb 09 01:56:27 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=672917445 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_outstanding.672917445
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/12.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_errors.1649303931
Short name T1059
Test name
Test status
Simulation time 227047687 ps
CPU time 3.54 seconds
Started Feb 09 01:56:23 PM UTC 25
Finished Feb 09 01:56:28 PM UTC 25
Peak memory 227940 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649303931 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.1649303931
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/12.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_intg_err.1342975478
Short name T1054
Test name
Test status
Simulation time 162005424 ps
CPU time 2.39 seconds
Started Feb 09 01:56:23 PM UTC 25
Finished Feb 09 01:56:27 PM UTC 25
Peak memory 217928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342975478 -assert nopostproc +UVM_TESTNAME=edn_base_t
est +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.1342975478
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/12.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1808561051
Short name T1067
Test name
Test status
Simulation time 362673657 ps
CPU time 2.2 seconds
Started Feb 09 01:56:27 PM UTC 25
Finished Feb 09 01:56:30 PM UTC 25
Peak memory 228040 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808561051
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.1808561051
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_rw.882225922
Short name T1063
Test name
Test status
Simulation time 14674996 ps
CPU time 1.22 seconds
Started Feb 09 01:56:27 PM UTC 25
Finished Feb 09 01:56:29 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882225922 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_T
EST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.882225922
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/13.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/13.edn_intr_test.2133463048
Short name T1062
Test name
Test status
Simulation time 51021686 ps
CPU time 1.19 seconds
Started Feb 09 01:56:27 PM UTC 25
Finished Feb 09 01:56:29 PM UTC 25
Peak memory 214380 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133463048 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.2133463048
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/13.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/13.edn_same_csr_outstanding.1837452182
Short name T1065
Test name
Test status
Simulation time 14316039 ps
CPU time 1.51 seconds
Started Feb 09 01:56:27 PM UTC 25
Finished Feb 09 01:56:29 PM UTC 25
Peak memory 214484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837452182 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_outstanding.1837452182
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/13.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_errors.2427357037
Short name T1061
Test name
Test status
Simulation time 116660911 ps
CPU time 1.93 seconds
Started Feb 09 01:56:26 PM UTC 25
Finished Feb 09 01:56:29 PM UTC 25
Peak memory 225824 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427357037 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.2427357037
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/13.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_intg_err.4160335172
Short name T1064
Test name
Test status
Simulation time 109588625 ps
CPU time 2.42 seconds
Started Feb 09 01:56:26 PM UTC 25
Finished Feb 09 01:56:29 PM UTC 25
Peak memory 227544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160335172 -assert nopostproc +UVM_TESTNAME=edn_base_t
est +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.4160335172
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/13.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1610303114
Short name T1072
Test name
Test status
Simulation time 158422531 ps
CPU time 2.06 seconds
Started Feb 09 01:56:28 PM UTC 25
Finished Feb 09 01:56:32 PM UTC 25
Peak memory 227952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610303114
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.1610303114
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_rw.1066206106
Short name T1066
Test name
Test status
Simulation time 13036059 ps
CPU time 1.1 seconds
Started Feb 09 01:56:28 PM UTC 25
Finished Feb 09 01:56:30 PM UTC 25
Peak memory 215792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066206106 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_
TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.1066206106
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/14.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/14.edn_intr_test.2332726565
Short name T1069
Test name
Test status
Simulation time 14786624 ps
CPU time 1.37 seconds
Started Feb 09 01:56:28 PM UTC 25
Finished Feb 09 01:56:30 PM UTC 25
Peak memory 214764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332726565 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.2332726565
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/14.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/14.edn_same_csr_outstanding.1419075361
Short name T1070
Test name
Test status
Simulation time 19596716 ps
CPU time 1.71 seconds
Started Feb 09 01:56:28 PM UTC 25
Finished Feb 09 01:56:31 PM UTC 25
Peak memory 215728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419075361 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_outstanding.1419075361
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/14.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_errors.3795356683
Short name T1068
Test name
Test status
Simulation time 24868815 ps
CPU time 2.36 seconds
Started Feb 09 01:56:27 PM UTC 25
Finished Feb 09 01:56:30 PM UTC 25
Peak memory 227940 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795356683 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.3795356683
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/14.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_intg_err.4031180266
Short name T1071
Test name
Test status
Simulation time 52092134 ps
CPU time 2.28 seconds
Started Feb 09 01:56:28 PM UTC 25
Finished Feb 09 01:56:31 PM UTC 25
Peak memory 217216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031180266 -assert nopostproc +UVM_TESTNAME=edn_base_t
est +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.4031180266
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/14.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2875276509
Short name T1074
Test name
Test status
Simulation time 27434632 ps
CPU time 1.57 seconds
Started Feb 09 01:56:30 PM UTC 25
Finished Feb 09 01:56:33 PM UTC 25
Peak memory 226032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875276509
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.2875276509
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_rw.2533350103
Short name T288
Test name
Test status
Simulation time 98824121 ps
CPU time 1.14 seconds
Started Feb 09 01:56:29 PM UTC 25
Finished Feb 09 01:56:32 PM UTC 25
Peak memory 215792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533350103 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_
TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.2533350103
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/15.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/15.edn_intr_test.105360091
Short name T1073
Test name
Test status
Simulation time 24357529 ps
CPU time 1.14 seconds
Started Feb 09 01:56:29 PM UTC 25
Finished Feb 09 01:56:32 PM UTC 25
Peak memory 215784 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105360091 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST
_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.105360091
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/15.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/15.edn_same_csr_outstanding.899794947
Short name T1075
Test name
Test status
Simulation time 110090460 ps
CPU time 1.92 seconds
Started Feb 09 01:56:30 PM UTC 25
Finished Feb 09 01:56:33 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899794947 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_outstanding.899794947
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/15.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_errors.3627075305
Short name T1076
Test name
Test status
Simulation time 256055468 ps
CPU time 3.78 seconds
Started Feb 09 01:56:28 PM UTC 25
Finished Feb 09 01:56:33 PM UTC 25
Peak memory 227940 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627075305 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.3627075305
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/15.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_intg_err.596368219
Short name T1077
Test name
Test status
Simulation time 223336827 ps
CPU time 3.14 seconds
Started Feb 09 01:56:29 PM UTC 25
Finished Feb 09 01:56:34 PM UTC 25
Peak memory 227944 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596368219 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.596368219
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/15.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.224078503
Short name T1082
Test name
Test status
Simulation time 109277625 ps
CPU time 2.03 seconds
Started Feb 09 01:56:32 PM UTC 25
Finished Feb 09 01:56:35 PM UTC 25
Peak memory 228232 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224078503
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.224078503
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_rw.3318240487
Short name T287
Test name
Test status
Simulation time 18326055 ps
CPU time 1.25 seconds
Started Feb 09 01:56:31 PM UTC 25
Finished Feb 09 01:56:34 PM UTC 25
Peak memory 215768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318240487 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_
TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.3318240487
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/16.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/16.edn_intr_test.123002286
Short name T1078
Test name
Test status
Simulation time 11746918 ps
CPU time 1.3 seconds
Started Feb 09 01:56:31 PM UTC 25
Finished Feb 09 01:56:34 PM UTC 25
Peak memory 215780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123002286 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST
_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.123002286
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/16.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/16.edn_same_csr_outstanding.429069311
Short name T1079
Test name
Test status
Simulation time 62766768 ps
CPU time 1.55 seconds
Started Feb 09 01:56:32 PM UTC 25
Finished Feb 09 01:56:34 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429069311 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_outstanding.429069311
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/16.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_errors.840514055
Short name T1080
Test name
Test status
Simulation time 112382856 ps
CPU time 2.76 seconds
Started Feb 09 01:56:30 PM UTC 25
Finished Feb 09 01:56:34 PM UTC 25
Peak memory 228032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840514055 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST
_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.840514055
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/16.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_intg_err.3790343744
Short name T1081
Test name
Test status
Simulation time 258757390 ps
CPU time 3.18 seconds
Started Feb 09 01:56:30 PM UTC 25
Finished Feb 09 01:56:35 PM UTC 25
Peak memory 217648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790343744 -assert nopostproc +UVM_TESTNAME=edn_base_t
est +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.3790343744
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/16.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3487821618
Short name T1087
Test name
Test status
Simulation time 36289846 ps
CPU time 1.66 seconds
Started Feb 09 01:56:34 PM UTC 25
Finished Feb 09 01:56:37 PM UTC 25
Peak memory 226032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487821618
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.3487821618
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_rw.3849666988
Short name T1084
Test name
Test status
Simulation time 25866685 ps
CPU time 1.34 seconds
Started Feb 09 01:56:33 PM UTC 25
Finished Feb 09 01:56:35 PM UTC 25
Peak memory 215792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849666988 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_
TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.3849666988
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/17.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/17.edn_intr_test.1557876168
Short name T1083
Test name
Test status
Simulation time 15021224 ps
CPU time 1.36 seconds
Started Feb 09 01:56:33 PM UTC 25
Finished Feb 09 01:56:35 PM UTC 25
Peak memory 215052 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557876168 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.1557876168
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/17.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/17.edn_same_csr_outstanding.3379482162
Short name T1085
Test name
Test status
Simulation time 120417517 ps
CPU time 1.57 seconds
Started Feb 09 01:56:33 PM UTC 25
Finished Feb 09 01:56:36 PM UTC 25
Peak memory 215728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379482162 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_outstanding.3379482162
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/17.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_errors.3754521926
Short name T1086
Test name
Test status
Simulation time 59410541 ps
CPU time 3.61 seconds
Started Feb 09 01:56:32 PM UTC 25
Finished Feb 09 01:56:36 PM UTC 25
Peak memory 228036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754521926 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.3754521926
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/17.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_intg_err.3270809622
Short name T1088
Test name
Test status
Simulation time 105037889 ps
CPU time 3.22 seconds
Started Feb 09 01:56:33 PM UTC 25
Finished Feb 09 01:56:37 PM UTC 25
Peak memory 227680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270809622 -assert nopostproc +UVM_TESTNAME=edn_base_t
est +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.3270809622
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/17.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1944750261
Short name T1094
Test name
Test status
Simulation time 65684481 ps
CPU time 2.26 seconds
Started Feb 09 01:56:35 PM UTC 25
Finished Feb 09 01:56:39 PM UTC 25
Peak memory 227976 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944750261
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.1944750261
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_rw.2298231042
Short name T1090
Test name
Test status
Simulation time 64136702 ps
CPU time 1.23 seconds
Started Feb 09 01:56:35 PM UTC 25
Finished Feb 09 01:56:37 PM UTC 25
Peak memory 215792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298231042 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_
TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.2298231042
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/18.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/18.edn_intr_test.145714090
Short name T1089
Test name
Test status
Simulation time 14239892 ps
CPU time 1.32 seconds
Started Feb 09 01:56:35 PM UTC 25
Finished Feb 09 01:56:37 PM UTC 25
Peak memory 215784 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145714090 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST
_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.145714090
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/18.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/18.edn_same_csr_outstanding.1744045332
Short name T1091
Test name
Test status
Simulation time 35164978 ps
CPU time 1.69 seconds
Started Feb 09 01:56:35 PM UTC 25
Finished Feb 09 01:56:38 PM UTC 25
Peak memory 215728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744045332 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_outstanding.1744045332
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/18.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_errors.1760869025
Short name T1092
Test name
Test status
Simulation time 204024775 ps
CPU time 3.33 seconds
Started Feb 09 01:56:34 PM UTC 25
Finished Feb 09 01:56:38 PM UTC 25
Peak memory 227948 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760869025 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.1760869025
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/18.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_intg_err.4180249086
Short name T1093
Test name
Test status
Simulation time 89777131 ps
CPU time 3.39 seconds
Started Feb 09 01:56:34 PM UTC 25
Finished Feb 09 01:56:39 PM UTC 25
Peak memory 217644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180249086 -assert nopostproc +UVM_TESTNAME=edn_base_t
est +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.4180249086
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/18.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1030937623
Short name T1097
Test name
Test status
Simulation time 26069859 ps
CPU time 1.77 seconds
Started Feb 09 01:56:36 PM UTC 25
Finished Feb 09 01:56:39 PM UTC 25
Peak memory 215792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030937623
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.1030937623
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_rw.1480928917
Short name T1095
Test name
Test status
Simulation time 48070361 ps
CPU time 1.27 seconds
Started Feb 09 01:56:36 PM UTC 25
Finished Feb 09 01:56:39 PM UTC 25
Peak memory 215792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1480928917 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_
TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.1480928917
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/19.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/19.edn_intr_test.961651861
Short name T1096
Test name
Test status
Simulation time 23507593 ps
CPU time 1.35 seconds
Started Feb 09 01:56:36 PM UTC 25
Finished Feb 09 01:56:39 PM UTC 25
Peak memory 215784 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961651861 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST
_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.961651861
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/19.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/19.edn_same_csr_outstanding.906220212
Short name T1098
Test name
Test status
Simulation time 317432558 ps
CPU time 1.87 seconds
Started Feb 09 01:56:36 PM UTC 25
Finished Feb 09 01:56:39 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906220212 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_outstanding.906220212
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/19.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_errors.3645338684
Short name T1101
Test name
Test status
Simulation time 343692416 ps
CPU time 3.52 seconds
Started Feb 09 01:56:35 PM UTC 25
Finished Feb 09 01:56:40 PM UTC 25
Peak memory 228036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645338684 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.3645338684
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/19.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_intg_err.3247464245
Short name T1104
Test name
Test status
Simulation time 190996420 ps
CPU time 3.35 seconds
Started Feb 09 01:56:36 PM UTC 25
Finished Feb 09 01:56:41 PM UTC 25
Peak memory 217644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247464245 -assert nopostproc +UVM_TESTNAME=edn_base_t
est +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.3247464245
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/19.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_aliasing.2872385542
Short name T279
Test name
Test status
Simulation time 86436376 ps
CPU time 1.66 seconds
Started Feb 09 01:56:04 PM UTC 25
Finished Feb 09 01:56:07 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872385542 -assert nopostproc +UVM_TESTNAME=edn_base_test
+UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.2872385542
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/2.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_bit_bash.2945728276
Short name T1014
Test name
Test status
Simulation time 243990902 ps
CPU time 6.01 seconds
Started Feb 09 01:56:04 PM UTC 25
Finished Feb 09 01:56:11 PM UTC 25
Peak memory 217516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945728276 -assert nopostproc +UVM_TESTNAME=edn_base_test
+UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.2945728276
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/2.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_hw_reset.696666029
Short name T278
Test name
Test status
Simulation time 35883620 ps
CPU time 1.48 seconds
Started Feb 09 01:56:04 PM UTC 25
Finished Feb 09 01:56:06 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696666029 -assert nopostproc +UVM_TESTNAME=edn_base_test
+UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.696666029
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/2.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.642859897
Short name T1011
Test name
Test status
Simulation time 38591194 ps
CPU time 2.17 seconds
Started Feb 09 01:56:05 PM UTC 25
Finished Feb 09 01:56:08 PM UTC 25
Peak memory 227996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642859897
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.642859897
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_rw.272007058
Short name T277
Test name
Test status
Simulation time 170678380 ps
CPU time 1.11 seconds
Started Feb 09 01:56:04 PM UTC 25
Finished Feb 09 01:56:06 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272007058 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_T
EST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.272007058
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/2.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/2.edn_intr_test.2115614378
Short name T1008
Test name
Test status
Simulation time 41407021 ps
CPU time 1.21 seconds
Started Feb 09 01:56:04 PM UTC 25
Finished Feb 09 01:56:06 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115614378 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.2115614378
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/2.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/2.edn_same_csr_outstanding.3413969727
Short name T290
Test name
Test status
Simulation time 23255451 ps
CPU time 1.74 seconds
Started Feb 09 01:56:05 PM UTC 25
Finished Feb 09 01:56:08 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413969727 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_outstanding.3413969727
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/2.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/2.edn_tl_errors.698550455
Short name T1007
Test name
Test status
Simulation time 86639420 ps
CPU time 2.05 seconds
Started Feb 09 01:56:03 PM UTC 25
Finished Feb 09 01:56:06 PM UTC 25
Peak memory 227884 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698550455 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST
_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.698550455
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/2.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/2.edn_tl_intg_err.3284166615
Short name T305
Test name
Test status
Simulation time 347330784 ps
CPU time 3.25 seconds
Started Feb 09 01:56:03 PM UTC 25
Finished Feb 09 01:56:07 PM UTC 25
Peak memory 217828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284166615 -assert nopostproc +UVM_TESTNAME=edn_base_t
est +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.3284166615
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/2.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/20.edn_intr_test.3769987071
Short name T1100
Test name
Test status
Simulation time 28133905 ps
CPU time 1.24 seconds
Started Feb 09 01:56:37 PM UTC 25
Finished Feb 09 01:56:40 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769987071 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.3769987071
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/20.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/21.edn_intr_test.3368589390
Short name T1099
Test name
Test status
Simulation time 13174131 ps
CPU time 1.14 seconds
Started Feb 09 01:56:37 PM UTC 25
Finished Feb 09 01:56:40 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368589390 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.3368589390
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/21.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/22.edn_intr_test.556966390
Short name T1102
Test name
Test status
Simulation time 26258462 ps
CPU time 1.32 seconds
Started Feb 09 01:56:38 PM UTC 25
Finished Feb 09 01:56:40 PM UTC 25
Peak memory 215784 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556966390 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST
_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.556966390
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/22.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/23.edn_intr_test.3814796864
Short name T1103
Test name
Test status
Simulation time 22056655 ps
CPU time 0.95 seconds
Started Feb 09 01:56:39 PM UTC 25
Finished Feb 09 01:56:41 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814796864 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.3814796864
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/23.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/24.edn_intr_test.299134570
Short name T1106
Test name
Test status
Simulation time 20831041 ps
CPU time 1.2 seconds
Started Feb 09 01:56:39 PM UTC 25
Finished Feb 09 01:56:41 PM UTC 25
Peak memory 215784 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299134570 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST
_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.299134570
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/24.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/25.edn_intr_test.3349452103
Short name T1105
Test name
Test status
Simulation time 37542164 ps
CPU time 1.13 seconds
Started Feb 09 01:56:39 PM UTC 25
Finished Feb 09 01:56:41 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349452103 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.3349452103
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/25.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/26.edn_intr_test.343858081
Short name T1108
Test name
Test status
Simulation time 10768322 ps
CPU time 1.19 seconds
Started Feb 09 01:56:40 PM UTC 25
Finished Feb 09 01:56:42 PM UTC 25
Peak memory 215600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343858081 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST
_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.343858081
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/26.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/27.edn_intr_test.1656639380
Short name T1110
Test name
Test status
Simulation time 21574726 ps
CPU time 1.21 seconds
Started Feb 09 01:56:40 PM UTC 25
Finished Feb 09 01:56:42 PM UTC 25
Peak memory 215592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656639380 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.1656639380
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/27.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/28.edn_intr_test.1401987775
Short name T1107
Test name
Test status
Simulation time 40287766 ps
CPU time 1.2 seconds
Started Feb 09 01:56:40 PM UTC 25
Finished Feb 09 01:56:42 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401987775 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.1401987775
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/28.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/29.edn_intr_test.1726547264
Short name T1109
Test name
Test status
Simulation time 16916532 ps
CPU time 1.09 seconds
Started Feb 09 01:56:40 PM UTC 25
Finished Feb 09 01:56:42 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726547264 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.1726547264
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/29.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_aliasing.472345785
Short name T280
Test name
Test status
Simulation time 79623104 ps
CPU time 1.7 seconds
Started Feb 09 01:56:08 PM UTC 25
Finished Feb 09 01:56:11 PM UTC 25
Peak memory 215600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472345785 -assert nopostproc +UVM_TESTNAME=edn_base_test
+UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.472345785
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/3.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_bit_bash.757367121
Short name T1022
Test name
Test status
Simulation time 348553465 ps
CPU time 6.52 seconds
Started Feb 09 01:56:08 PM UTC 25
Finished Feb 09 01:56:15 PM UTC 25
Peak memory 217772 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757367121 -assert nopostproc +UVM_TESTNAME=edn_base_test
+UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.757367121
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/3.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_hw_reset.874298707
Short name T1012
Test name
Test status
Simulation time 13272639 ps
CPU time 1.35 seconds
Started Feb 09 01:56:06 PM UTC 25
Finished Feb 09 01:56:09 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874298707 -assert nopostproc +UVM_TESTNAME=edn_base_test
+UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.874298707
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/3.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.50705550
Short name T1013
Test name
Test status
Simulation time 36954377 ps
CPU time 1.69 seconds
Started Feb 09 01:56:08 PM UTC 25
Finished Feb 09 01:56:11 PM UTC 25
Peak memory 226004 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50705550 -
assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.50705550
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_rw.3630122565
Short name T291
Test name
Test status
Simulation time 15208724 ps
CPU time 1.37 seconds
Started Feb 09 01:56:08 PM UTC 25
Finished Feb 09 01:56:10 PM UTC 25
Peak memory 215492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630122565 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_
TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.3630122565
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/3.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/3.edn_intr_test.1188110178
Short name T1010
Test name
Test status
Simulation time 14017241 ps
CPU time 1.09 seconds
Started Feb 09 01:56:05 PM UTC 25
Finished Feb 09 01:56:07 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188110178 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.1188110178
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/3.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/3.edn_same_csr_outstanding.1598186929
Short name T292
Test name
Test status
Simulation time 126801489 ps
CPU time 2.14 seconds
Started Feb 09 01:56:08 PM UTC 25
Finished Feb 09 01:56:11 PM UTC 25
Peak memory 217984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598186929 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_outstanding.1598186929
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/3.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/3.edn_tl_errors.460304918
Short name T1018
Test name
Test status
Simulation time 517976091 ps
CPU time 6.65 seconds
Started Feb 09 01:56:05 PM UTC 25
Finished Feb 09 01:56:13 PM UTC 25
Peak memory 228148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460304918 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST
_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.460304918
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/3.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/30.edn_intr_test.1809678607
Short name T1112
Test name
Test status
Simulation time 15233785 ps
CPU time 1.29 seconds
Started Feb 09 01:56:40 PM UTC 25
Finished Feb 09 01:56:42 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809678607 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.1809678607
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/30.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/31.edn_intr_test.1088439447
Short name T1111
Test name
Test status
Simulation time 13055414 ps
CPU time 1.13 seconds
Started Feb 09 01:56:40 PM UTC 25
Finished Feb 09 01:56:42 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088439447 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.1088439447
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/31.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/32.edn_intr_test.3015901005
Short name T1113
Test name
Test status
Simulation time 68747673 ps
CPU time 1.26 seconds
Started Feb 09 01:56:40 PM UTC 25
Finished Feb 09 01:56:42 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015901005 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.3015901005
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/32.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/33.edn_intr_test.441079051
Short name T1116
Test name
Test status
Simulation time 24695047 ps
CPU time 1.2 seconds
Started Feb 09 01:56:41 PM UTC 25
Finished Feb 09 01:56:43 PM UTC 25
Peak memory 215792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441079051 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST
_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.441079051
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/33.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/34.edn_intr_test.1978177670
Short name T1114
Test name
Test status
Simulation time 32696298 ps
CPU time 1.1 seconds
Started Feb 09 01:56:41 PM UTC 25
Finished Feb 09 01:56:43 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978177670 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.1978177670
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/34.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/35.edn_intr_test.395348109
Short name T1115
Test name
Test status
Simulation time 13691358 ps
CPU time 1.03 seconds
Started Feb 09 01:56:41 PM UTC 25
Finished Feb 09 01:56:43 PM UTC 25
Peak memory 215792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395348109 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST
_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.395348109
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/35.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/36.edn_intr_test.3966058367
Short name T1119
Test name
Test status
Simulation time 17506692 ps
CPU time 1.35 seconds
Started Feb 09 01:56:41 PM UTC 25
Finished Feb 09 01:56:44 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966058367 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.3966058367
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/36.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/37.edn_intr_test.68267504
Short name T1118
Test name
Test status
Simulation time 18366936 ps
CPU time 1.33 seconds
Started Feb 09 01:56:41 PM UTC 25
Finished Feb 09 01:56:44 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68267504 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_
SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.68267504
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/37.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/38.edn_intr_test.1928903564
Short name T1117
Test name
Test status
Simulation time 36199927 ps
CPU time 1.14 seconds
Started Feb 09 01:56:41 PM UTC 25
Finished Feb 09 01:56:44 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928903564 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.1928903564
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/38.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/39.edn_intr_test.3833661349
Short name T1120
Test name
Test status
Simulation time 14862912 ps
CPU time 1.15 seconds
Started Feb 09 01:56:42 PM UTC 25
Finished Feb 09 01:56:45 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833661349 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.3833661349
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/39.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_aliasing.334614533
Short name T281
Test name
Test status
Simulation time 22918097 ps
CPU time 1.46 seconds
Started Feb 09 01:56:10 PM UTC 25
Finished Feb 09 01:56:13 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334614533 -assert nopostproc +UVM_TESTNAME=edn_base_test
+UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.334614533
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/4.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_bit_bash.3782985807
Short name T286
Test name
Test status
Simulation time 611631385 ps
CPU time 8.94 seconds
Started Feb 09 01:56:09 PM UTC 25
Finished Feb 09 01:56:19 PM UTC 25
Peak memory 217516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782985807 -assert nopostproc +UVM_TESTNAME=edn_base_test
+UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.3782985807
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/4.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_hw_reset.2505591250
Short name T1017
Test name
Test status
Simulation time 75695970 ps
CPU time 1.34 seconds
Started Feb 09 01:56:09 PM UTC 25
Finished Feb 09 01:56:11 PM UTC 25
Peak memory 215744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505591250 -assert nopostproc +UVM_TESTNAME=edn_base_test
+UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.2505591250
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/4.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.892684605
Short name T1019
Test name
Test status
Simulation time 111096070 ps
CPU time 1.41 seconds
Started Feb 09 01:56:11 PM UTC 25
Finished Feb 09 01:56:14 PM UTC 25
Peak memory 226024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892684605
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.892684605
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_rw.1811798909
Short name T293
Test name
Test status
Simulation time 38171126 ps
CPU time 1.29 seconds
Started Feb 09 01:56:09 PM UTC 25
Finished Feb 09 01:56:11 PM UTC 25
Peak memory 215696 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811798909 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_
TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.1811798909
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/4.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/4.edn_intr_test.2216643572
Short name T1015
Test name
Test status
Simulation time 25356514 ps
CPU time 1.27 seconds
Started Feb 09 01:56:09 PM UTC 25
Finished Feb 09 01:56:11 PM UTC 25
Peak memory 215592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216643572 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.2216643572
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/4.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/4.edn_same_csr_outstanding.3393200980
Short name T294
Test name
Test status
Simulation time 56799374 ps
CPU time 1.31 seconds
Started Feb 09 01:56:11 PM UTC 25
Finished Feb 09 01:56:14 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393200980 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_outstanding.3393200980
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/4.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/4.edn_tl_errors.2876159826
Short name T1016
Test name
Test status
Simulation time 47056394 ps
CPU time 2.44 seconds
Started Feb 09 01:56:08 PM UTC 25
Finished Feb 09 01:56:11 PM UTC 25
Peak memory 228036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876159826 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.2876159826
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/4.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/4.edn_tl_intg_err.27745332
Short name T318
Test name
Test status
Simulation time 176982030 ps
CPU time 1.92 seconds
Started Feb 09 01:56:09 PM UTC 25
Finished Feb 09 01:56:12 PM UTC 25
Peak memory 225828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27745332 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.27745332
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/4.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/40.edn_intr_test.764393654
Short name T1121
Test name
Test status
Simulation time 14486371 ps
CPU time 1.33 seconds
Started Feb 09 01:56:42 PM UTC 25
Finished Feb 09 01:56:45 PM UTC 25
Peak memory 215784 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764393654 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST
_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.764393654
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/40.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/41.edn_intr_test.390369879
Short name T1123
Test name
Test status
Simulation time 41496152 ps
CPU time 1.15 seconds
Started Feb 09 01:56:43 PM UTC 25
Finished Feb 09 01:56:46 PM UTC 25
Peak memory 215368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390369879 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST
_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.390369879
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/41.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/42.edn_intr_test.4092798148
Short name T1125
Test name
Test status
Simulation time 40266247 ps
CPU time 1.34 seconds
Started Feb 09 01:56:43 PM UTC 25
Finished Feb 09 01:56:46 PM UTC 25
Peak memory 215516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092798148 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.4092798148
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/42.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/43.edn_intr_test.2981519473
Short name T1124
Test name
Test status
Simulation time 59263139 ps
CPU time 1.16 seconds
Started Feb 09 01:56:43 PM UTC 25
Finished Feb 09 01:56:46 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981519473 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.2981519473
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/43.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/44.edn_intr_test.1133402308
Short name T1122
Test name
Test status
Simulation time 43997575 ps
CPU time 1.01 seconds
Started Feb 09 01:56:43 PM UTC 25
Finished Feb 09 01:56:46 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133402308 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.1133402308
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/44.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/45.edn_intr_test.78626708
Short name T1126
Test name
Test status
Simulation time 114995898 ps
CPU time 1.19 seconds
Started Feb 09 01:56:44 PM UTC 25
Finished Feb 09 01:56:46 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78626708 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_
SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.78626708
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/45.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/46.edn_intr_test.3752239739
Short name T1127
Test name
Test status
Simulation time 15382953 ps
CPU time 1.24 seconds
Started Feb 09 01:56:44 PM UTC 25
Finished Feb 09 01:56:46 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752239739 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.3752239739
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/46.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/47.edn_intr_test.2450671796
Short name T1128
Test name
Test status
Simulation time 28462131 ps
CPU time 1.32 seconds
Started Feb 09 01:56:44 PM UTC 25
Finished Feb 09 01:56:46 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450671796 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.2450671796
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/47.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/48.edn_intr_test.3576734942
Short name T1129
Test name
Test status
Simulation time 11843495 ps
CPU time 0.92 seconds
Started Feb 09 01:56:45 PM UTC 25
Finished Feb 09 01:56:47 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576734942 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.3576734942
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/48.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/49.edn_intr_test.1290742324
Short name T1130
Test name
Test status
Simulation time 16245364 ps
CPU time 1.38 seconds
Started Feb 09 01:56:45 PM UTC 25
Finished Feb 09 01:56:47 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290742324 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.1290742324
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/49.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1040048256
Short name T1024
Test name
Test status
Simulation time 48251131 ps
CPU time 1.92 seconds
Started Feb 09 01:56:13 PM UTC 25
Finished Feb 09 01:56:16 PM UTC 25
Peak memory 226032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040048256
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.1040048256
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/5.edn_csr_rw.1531794469
Short name T282
Test name
Test status
Simulation time 27444108 ps
CPU time 1.16 seconds
Started Feb 09 01:56:13 PM UTC 25
Finished Feb 09 01:56:15 PM UTC 25
Peak memory 215628 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531794469 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_
TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.1531794469
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/5.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/5.edn_intr_test.3588732318
Short name T1020
Test name
Test status
Simulation time 30005330 ps
CPU time 1.34 seconds
Started Feb 09 01:56:13 PM UTC 25
Finished Feb 09 01:56:15 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588732318 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.3588732318
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/5.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/5.edn_same_csr_outstanding.214517448
Short name T295
Test name
Test status
Simulation time 50948344 ps
CPU time 1.47 seconds
Started Feb 09 01:56:13 PM UTC 25
Finished Feb 09 01:56:15 PM UTC 25
Peak memory 215772 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214517448 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_outstanding.214517448
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/5.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/5.edn_tl_errors.1367212801
Short name T1028
Test name
Test status
Simulation time 118606467 ps
CPU time 5.39 seconds
Started Feb 09 01:56:11 PM UTC 25
Finished Feb 09 01:56:18 PM UTC 25
Peak memory 227948 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367212801 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.1367212801
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/5.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/5.edn_tl_intg_err.1372680139
Short name T317
Test name
Test status
Simulation time 71468754 ps
CPU time 3.31 seconds
Started Feb 09 01:56:12 PM UTC 25
Finished Feb 09 01:56:17 PM UTC 25
Peak memory 217712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1372680139 -assert nopostproc +UVM_TESTNAME=edn_base_t
est +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.1372680139
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/5.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2423029249
Short name T1030
Test name
Test status
Simulation time 50303202 ps
CPU time 2.04 seconds
Started Feb 09 01:56:15 PM UTC 25
Finished Feb 09 01:56:18 PM UTC 25
Peak memory 227948 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423029249
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.2423029249
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/6.edn_csr_rw.3794258849
Short name T1025
Test name
Test status
Simulation time 34502094 ps
CPU time 1.23 seconds
Started Feb 09 01:56:14 PM UTC 25
Finished Feb 09 01:56:16 PM UTC 25
Peak memory 215724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794258849 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_
TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.3794258849
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/6.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/6.edn_intr_test.615171877
Short name T1021
Test name
Test status
Simulation time 14670236 ps
CPU time 1.3 seconds
Started Feb 09 01:56:13 PM UTC 25
Finished Feb 09 01:56:15 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615171877 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST
_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.615171877
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/6.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/6.edn_same_csr_outstanding.3526150688
Short name T296
Test name
Test status
Simulation time 26872113 ps
CPU time 1.4 seconds
Started Feb 09 01:56:14 PM UTC 25
Finished Feb 09 01:56:16 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526150688 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_outstanding.3526150688
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/6.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_errors.2489957206
Short name T1026
Test name
Test status
Simulation time 39952951 ps
CPU time 2.9 seconds
Started Feb 09 01:56:13 PM UTC 25
Finished Feb 09 01:56:17 PM UTC 25
Peak memory 227932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489957206 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.2489957206
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/6.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_intg_err.3132617168
Short name T1023
Test name
Test status
Simulation time 44797481 ps
CPU time 1.85 seconds
Started Feb 09 01:56:13 PM UTC 25
Finished Feb 09 01:56:16 PM UTC 25
Peak memory 215632 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132617168 -assert nopostproc +UVM_TESTNAME=edn_base_t
est +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.3132617168
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/6.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3242117102
Short name T1033
Test name
Test status
Simulation time 20294407 ps
CPU time 1.54 seconds
Started Feb 09 01:56:16 PM UTC 25
Finished Feb 09 01:56:19 PM UTC 25
Peak memory 226032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242117102
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.3242117102
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_rw.3743040019
Short name T1031
Test name
Test status
Simulation time 12945975 ps
CPU time 1.17 seconds
Started Feb 09 01:56:16 PM UTC 25
Finished Feb 09 01:56:18 PM UTC 25
Peak memory 215696 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743040019 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_
TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.3743040019
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/7.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/7.edn_intr_test.1515648190
Short name T1032
Test name
Test status
Simulation time 23707676 ps
CPU time 1.29 seconds
Started Feb 09 01:56:16 PM UTC 25
Finished Feb 09 01:56:18 PM UTC 25
Peak memory 215568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515648190 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.1515648190
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/7.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/7.edn_same_csr_outstanding.2215685774
Short name T1035
Test name
Test status
Simulation time 63608029 ps
CPU time 2.09 seconds
Started Feb 09 01:56:16 PM UTC 25
Finished Feb 09 01:56:19 PM UTC 25
Peak memory 217640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215685774 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_outstanding.2215685774
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/7.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_errors.684528219
Short name T1029
Test name
Test status
Simulation time 23430607 ps
CPU time 1.73 seconds
Started Feb 09 01:56:15 PM UTC 25
Finished Feb 09 01:56:18 PM UTC 25
Peak memory 225972 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684528219 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST
_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.684528219
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/7.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_intg_err.3437040200
Short name T1034
Test name
Test status
Simulation time 219483141 ps
CPU time 1.98 seconds
Started Feb 09 01:56:16 PM UTC 25
Finished Feb 09 01:56:19 PM UTC 25
Peak memory 215492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437040200 -assert nopostproc +UVM_TESTNAME=edn_base_t
est +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.3437040200
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/7.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1614726554
Short name T1038
Test name
Test status
Simulation time 35883610 ps
CPU time 1.56 seconds
Started Feb 09 01:56:18 PM UTC 25
Finished Feb 09 01:56:21 PM UTC 25
Peak memory 226032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614726554
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.1614726554
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_rw.1185936968
Short name T283
Test name
Test status
Simulation time 25393409 ps
CPU time 1.14 seconds
Started Feb 09 01:56:17 PM UTC 25
Finished Feb 09 01:56:20 PM UTC 25
Peak memory 215724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185936968 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_
TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.1185936968
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/8.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/8.edn_intr_test.1623506295
Short name T1036
Test name
Test status
Simulation time 83966321 ps
CPU time 1.05 seconds
Started Feb 09 01:56:17 PM UTC 25
Finished Feb 09 01:56:19 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623506295 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.1623506295
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/8.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/8.edn_same_csr_outstanding.63854798
Short name T1037
Test name
Test status
Simulation time 26561771 ps
CPU time 1.49 seconds
Started Feb 09 01:56:18 PM UTC 25
Finished Feb 09 01:56:21 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63854798 -assert nopostproc +UVM_TESTNAME=edn
_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_outstanding.63854798
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/8.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_errors.2969369753
Short name T1047
Test name
Test status
Simulation time 526935755 ps
CPU time 5.96 seconds
Started Feb 09 01:56:17 PM UTC 25
Finished Feb 09 01:56:24 PM UTC 25
Peak memory 228140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969369753 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.2969369753
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/8.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_intg_err.1942028306
Short name T1039
Test name
Test status
Simulation time 124838966 ps
CPU time 3.36 seconds
Started Feb 09 01:56:17 PM UTC 25
Finished Feb 09 01:56:22 PM UTC 25
Peak memory 217828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942028306 -assert nopostproc +UVM_TESTNAME=edn_base_t
est +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.1942028306
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/8.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1305716418
Short name T1027
Test name
Test status
Simulation time 31224259 ps
CPU time 1.59 seconds
Started Feb 09 01:56:20 PM UTC 25
Finished Feb 09 01:56:22 PM UTC 25
Peak memory 226032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305716418
-assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.1305716418
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_rw.3637737814
Short name T284
Test name
Test status
Simulation time 13730469 ps
CPU time 1.18 seconds
Started Feb 09 01:56:20 PM UTC 25
Finished Feb 09 01:56:22 PM UTC 25
Peak memory 215724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637737814 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_
TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.3637737814
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/9.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/9.edn_intr_test.4191567364
Short name T1041
Test name
Test status
Simulation time 20050435 ps
CPU time 1.17 seconds
Started Feb 09 01:56:20 PM UTC 25
Finished Feb 09 01:56:22 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191567364 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TES
T_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.4191567364
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/9.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/9.edn_same_csr_outstanding.4285886888
Short name T1043
Test name
Test status
Simulation time 56613538 ps
CPU time 1.37 seconds
Started Feb 09 01:56:20 PM UTC 25
Finished Feb 09 01:56:22 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285886888 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_outstanding.4285886888
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/9.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_errors.267604081
Short name T1042
Test name
Test status
Simulation time 42311672 ps
CPU time 2.36 seconds
Started Feb 09 01:56:18 PM UTC 25
Finished Feb 09 01:56:22 PM UTC 25
Peak memory 228044 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267604081 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST
_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.267604081
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/9.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_intg_err.720359574
Short name T1040
Test name
Test status
Simulation time 71674102 ps
CPU time 2.15 seconds
Started Feb 09 01:56:18 PM UTC 25
Finished Feb 09 01:56:22 PM UTC 25
Peak memory 217676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720359574 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.720359574
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/9.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/0.edn_alert_test.2452649236
Short name T25
Test name
Test status
Simulation time 25361221 ps
CPU time 1.35 seconds
Started Feb 09 01:27:57 PM UTC 25
Finished Feb 09 01:27:59 PM UTC 25
Peak memory 226692 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452649236 -assert nopostproc +UVM_TESTNAME=edn_base_test +UV
M_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.2452649236
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/0.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/0.edn_disable.1286007869
Short name T24
Test name
Test status
Simulation time 39168543 ps
CPU time 1.23 seconds
Started Feb 09 01:27:53 PM UTC 25
Finished Feb 09 01:27:55 PM UTC 25
Peak memory 226448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286007869 -assert nopostproc +UVM_TESTNAME=edn_disable_test +
UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.edn_disable.1286007869
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/0.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/0.edn_sec_cm.1634395684
Short name T16
Test name
Test status
Simulation time 1143393803 ps
CPU time 14.1 seconds
Started Feb 09 01:27:56 PM UTC 25
Finished Feb 09 01:28:11 PM UTC 25
Peak memory 262500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634395684 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM
_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.1634395684
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/0.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/0.edn_smoke.3858184359
Short name T1
Test name
Test status
Simulation time 27566790 ps
CPU time 1.51 seconds
Started Feb 09 01:27:35 PM UTC 25
Finished Feb 09 01:27:37 PM UTC 25
Peak memory 226632 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858184359 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 0.edn_smoke.3858184359
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/0.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/0.edn_stress_all.729250921
Short name T4
Test name
Test status
Simulation time 122847523 ps
CPU time 2.81 seconds
Started Feb 09 01:27:43 PM UTC 25
Finished Feb 09 01:27:48 PM UTC 25
Peak memory 229264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729250921 -assert nopostproc +UVM_TESTNAME=edn_stress_all_
test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.729250921
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/0.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/0.edn_stress_all_with_rand_reset.2908868633
Short name T247
Test name
Test status
Simulation time 331164033503 ps
CPU time 1745.34 seconds
Started Feb 09 01:27:44 PM UTC 25
Finished Feb 09 01:57:08 PM UTC 25
Peak memory 234316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2908868633 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.2908868633
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/0.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/1.edn_alert_test.2318309376
Short name T64
Test name
Test status
Simulation time 27038896 ps
CPU time 1.38 seconds
Started Feb 09 01:28:19 PM UTC 25
Finished Feb 09 01:28:22 PM UTC 25
Peak memory 217012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318309376 -assert nopostproc +UVM_TESTNAME=edn_base_test +UV
M_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.2318309376
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/1.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/1.edn_disable.328940923
Short name T63
Test name
Test status
Simulation time 69467513 ps
CPU time 1.27 seconds
Started Feb 09 01:28:15 PM UTC 25
Finished Feb 09 01:28:17 PM UTC 25
Peak memory 226012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328940923 -assert nopostproc +UVM_TESTNAME=edn_disable_test +U
VM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.edn_disable.328940923
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/1.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/1.edn_err.4195443430
Short name T7
Test name
Test status
Simulation time 26437385 ps
CPU time 1.79 seconds
Started Feb 09 01:28:15 PM UTC 25
Finished Feb 09 01:28:18 PM UTC 25
Peak memory 230296 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195443430 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 1.edn_err.4195443430
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/1.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/1.edn_intr.516973118
Short name T31
Test name
Test status
Simulation time 21285660 ps
CPU time 1.67 seconds
Started Feb 09 01:28:11 PM UTC 25
Finished Feb 09 01:28:14 PM UTC 25
Peak memory 226208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516973118 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 1.edn_intr.516973118
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/1.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/1.edn_regwen.3616400626
Short name T26
Test name
Test status
Simulation time 39219969 ps
CPU time 1.26 seconds
Started Feb 09 01:28:02 PM UTC 25
Finished Feb 09 01:28:04 PM UTC 25
Peak memory 215908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616400626 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 1.edn_regwen.3616400626
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/1.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/1.edn_sec_cm.295174649
Short name T17
Test name
Test status
Simulation time 1660222946 ps
CPU time 7.01 seconds
Started Feb 09 01:28:18 PM UTC 25
Finished Feb 09 01:28:26 PM UTC 25
Peak memory 260388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295174649 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_
TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.295174649
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/1.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/1.edn_smoke.620357755
Short name T67
Test name
Test status
Simulation time 43925963 ps
CPU time 1.35 seconds
Started Feb 09 01:28:00 PM UTC 25
Finished Feb 09 01:28:02 PM UTC 25
Peak memory 226140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620357755 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 1.edn_smoke.620357755
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/1.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/1.edn_stress_all.2864812404
Short name T56
Test name
Test status
Simulation time 1893422658 ps
CPU time 6.27 seconds
Started Feb 09 01:28:05 PM UTC 25
Finished Feb 09 01:28:13 PM UTC 25
Peak memory 231480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864812404 -assert nopostproc +UVM_TESTNAME=edn_stress_all
_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.2864812404
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/1.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/10.edn_alert.192354822
Short name T140
Test name
Test status
Simulation time 42099006 ps
CPU time 1.73 seconds
Started Feb 09 01:31:00 PM UTC 25
Finished Feb 09 01:31:03 PM UTC 25
Peak memory 227940 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192354822 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 10.edn_alert.192354822
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/10.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/10.edn_alert_test.2794171196
Short name T378
Test name
Test status
Simulation time 86034329 ps
CPU time 1.31 seconds
Started Feb 09 01:31:04 PM UTC 25
Finished Feb 09 01:31:07 PM UTC 25
Peak memory 216088 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794171196 -assert nopostproc +UVM_TESTNAME=edn_base_test +UV
M_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.2794171196
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/10.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/10.edn_disable.453368033
Short name T99
Test name
Test status
Simulation time 40572175 ps
CPU time 1.34 seconds
Started Feb 09 01:31:02 PM UTC 25
Finished Feb 09 01:31:05 PM UTC 25
Peak memory 226012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453368033 -assert nopostproc +UVM_TESTNAME=edn_disable_test +U
VM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.edn_disable.453368033
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/10.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/10.edn_err.2849700697
Short name T220
Test name
Test status
Simulation time 23968670 ps
CPU time 1.41 seconds
Started Feb 09 01:31:00 PM UTC 25
Finished Feb 09 01:31:03 PM UTC 25
Peak memory 230404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849700697 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 10.edn_err.2849700697
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/10.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/10.edn_genbits.3424880445
Short name T50
Test name
Test status
Simulation time 61467979 ps
CPU time 2.02 seconds
Started Feb 09 01:30:53 PM UTC 25
Finished Feb 09 01:30:56 PM UTC 25
Peak memory 231672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424880445 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.edn_genbits.3424880445
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/10.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/10.edn_intr.1239209722
Short name T377
Test name
Test status
Simulation time 30186690 ps
CPU time 1.37 seconds
Started Feb 09 01:30:57 PM UTC 25
Finished Feb 09 01:30:59 PM UTC 25
Peak memory 226448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239209722 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 10.edn_intr.1239209722
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/10.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/10.edn_smoke.1894615421
Short name T376
Test name
Test status
Simulation time 18242331 ps
CPU time 1.46 seconds
Started Feb 09 01:30:50 PM UTC 25
Finished Feb 09 01:30:53 PM UTC 25
Peak memory 226152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894615421 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 10.edn_smoke.1894615421
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/10.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/10.edn_stress_all.1416018767
Short name T108
Test name
Test status
Simulation time 780723873 ps
CPU time 6.97 seconds
Started Feb 09 01:30:54 PM UTC 25
Finished Feb 09 01:31:02 PM UTC 25
Peak memory 227620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416018767 -assert nopostproc +UVM_TESTNAME=edn_stress_all
_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.1416018767
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/10.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/100.edn_alert.1755189523
Short name T691
Test name
Test status
Simulation time 89329071 ps
CPU time 1.7 seconds
Started Feb 09 01:53:53 PM UTC 25
Finished Feb 09 01:53:56 PM UTC 25
Peak memory 230308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755189523 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 100.edn_alert.1755189523
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/100.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/101.edn_alert.2455652252
Short name T692
Test name
Test status
Simulation time 21494589 ps
CPU time 1.61 seconds
Started Feb 09 01:53:53 PM UTC 25
Finished Feb 09 01:53:56 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455652252 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 101.edn_alert.2455652252
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/101.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/101.edn_genbits.3095435046
Short name T695
Test name
Test status
Simulation time 79833350 ps
CPU time 2.4 seconds
Started Feb 09 01:53:53 PM UTC 25
Finished Feb 09 01:53:57 PM UTC 25
Peak memory 231416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095435046 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 101.edn_genbits.3095435046
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/101.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/102.edn_alert.1644358796
Short name T696
Test name
Test status
Simulation time 78781268 ps
CPU time 1.88 seconds
Started Feb 09 01:53:54 PM UTC 25
Finished Feb 09 01:53:57 PM UTC 25
Peak memory 226252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644358796 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 102.edn_alert.1644358796
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/102.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/102.edn_genbits.3485479356
Short name T694
Test name
Test status
Simulation time 61350062 ps
CPU time 2.21 seconds
Started Feb 09 01:53:53 PM UTC 25
Finished Feb 09 01:53:57 PM UTC 25
Peak memory 231404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485479356 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 102.edn_genbits.3485479356
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/102.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/103.edn_alert.80572117
Short name T697
Test name
Test status
Simulation time 48620157 ps
CPU time 1.82 seconds
Started Feb 09 01:53:55 PM UTC 25
Finished Feb 09 01:53:58 PM UTC 25
Peak memory 230308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80572117 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 103.edn_alert.80572117
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/103.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/103.edn_genbits.1957355165
Short name T698
Test name
Test status
Simulation time 88440332 ps
CPU time 1.98 seconds
Started Feb 09 01:53:55 PM UTC 25
Finished Feb 09 01:53:58 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957355165 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 103.edn_genbits.1957355165
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/103.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/104.edn_alert.3223106180
Short name T313
Test name
Test status
Simulation time 60642206 ps
CPU time 1.76 seconds
Started Feb 09 01:53:56 PM UTC 25
Finished Feb 09 01:53:59 PM UTC 25
Peak memory 230308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223106180 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 104.edn_alert.3223106180
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/104.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/104.edn_genbits.1501305106
Short name T700
Test name
Test status
Simulation time 49534017 ps
CPU time 1.81 seconds
Started Feb 09 01:53:56 PM UTC 25
Finished Feb 09 01:53:59 PM UTC 25
Peak memory 230592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501305106 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 104.edn_genbits.1501305106
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/104.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/105.edn_genbits.2541619733
Short name T701
Test name
Test status
Simulation time 104702059 ps
CPU time 2.04 seconds
Started Feb 09 01:53:56 PM UTC 25
Finished Feb 09 01:54:00 PM UTC 25
Peak memory 231412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541619733 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 105.edn_genbits.2541619733
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/105.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/106.edn_alert.2268805681
Short name T704
Test name
Test status
Simulation time 113867677 ps
CPU time 1.94 seconds
Started Feb 09 01:53:58 PM UTC 25
Finished Feb 09 01:54:01 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268805681 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 106.edn_alert.2268805681
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/106.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/106.edn_genbits.490596067
Short name T702
Test name
Test status
Simulation time 70977048 ps
CPU time 1.86 seconds
Started Feb 09 01:53:58 PM UTC 25
Finished Feb 09 01:54:00 PM UTC 25
Peak memory 230304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490596067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 106.edn_genbits.490596067
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/106.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/107.edn_alert.3886233914
Short name T705
Test name
Test status
Simulation time 29762522 ps
CPU time 1.82 seconds
Started Feb 09 01:53:59 PM UTC 25
Finished Feb 09 01:54:02 PM UTC 25
Peak memory 226252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886233914 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 107.edn_alert.3886233914
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/107.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/107.edn_genbits.1601317513
Short name T713
Test name
Test status
Simulation time 568729955 ps
CPU time 5.44 seconds
Started Feb 09 01:53:59 PM UTC 25
Finished Feb 09 01:54:05 PM UTC 25
Peak memory 231408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601317513 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 107.edn_genbits.1601317513
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/107.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/108.edn_genbits.3846640956
Short name T708
Test name
Test status
Simulation time 48708222 ps
CPU time 2.35 seconds
Started Feb 09 01:54:00 PM UTC 25
Finished Feb 09 01:54:03 PM UTC 25
Peak memory 229496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846640956 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 108.edn_genbits.3846640956
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/108.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/109.edn_alert.943514482
Short name T711
Test name
Test status
Simulation time 29191640 ps
CPU time 1.77 seconds
Started Feb 09 01:54:01 PM UTC 25
Finished Feb 09 01:54:04 PM UTC 25
Peak memory 230304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943514482 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 109.edn_alert.943514482
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/109.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/109.edn_genbits.2633092913
Short name T707
Test name
Test status
Simulation time 78943784 ps
CPU time 1.83 seconds
Started Feb 09 01:54:00 PM UTC 25
Finished Feb 09 01:54:03 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633092913 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 109.edn_genbits.2633092913
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/109.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/11.edn_alert.821984600
Short name T100
Test name
Test status
Simulation time 105277087 ps
CPU time 1.91 seconds
Started Feb 09 01:31:11 PM UTC 25
Finished Feb 09 01:31:14 PM UTC 25
Peak memory 228320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821984600 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 11.edn_alert.821984600
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/11.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/11.edn_alert_test.3791139276
Short name T380
Test name
Test status
Simulation time 17189349 ps
CPU time 1.47 seconds
Started Feb 09 01:31:16 PM UTC 25
Finished Feb 09 01:31:19 PM UTC 25
Peak memory 217080 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791139276 -assert nopostproc +UVM_TESTNAME=edn_base_test +UV
M_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.3791139276
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/11.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/11.edn_disable.2793179118
Short name T228
Test name
Test status
Simulation time 13092437 ps
CPU time 1.35 seconds
Started Feb 09 01:31:14 PM UTC 25
Finished Feb 09 01:31:16 PM UTC 25
Peak memory 226272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793179118 -assert nopostproc +UVM_TESTNAME=edn_disable_test +
UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.edn_disable.2793179118
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/11.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/11.edn_disable_auto_req_mode.3148559280
Short name T92
Test name
Test status
Simulation time 100546183 ps
CPU time 1.71 seconds
Started Feb 09 01:31:15 PM UTC 25
Finished Feb 09 01:31:18 PM UTC 25
Peak memory 228128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148559280 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_r
eq_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable_auto_req_mode.3148559280
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/11.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/11.edn_err.2078322810
Short name T173
Test name
Test status
Simulation time 44287724 ps
CPU time 1.71 seconds
Started Feb 09 01:31:13 PM UTC 25
Finished Feb 09 01:31:16 PM UTC 25
Peak memory 230308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078322810 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 11.edn_err.2078322810
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/11.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/11.edn_intr.3683940862
Short name T33
Test name
Test status
Simulation time 20181527 ps
CPU time 1.47 seconds
Started Feb 09 01:31:10 PM UTC 25
Finished Feb 09 01:31:13 PM UTC 25
Peak memory 228256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683940862 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 11.edn_intr.3683940862
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/11.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/11.edn_smoke.54257004
Short name T379
Test name
Test status
Simulation time 66122268 ps
CPU time 1.4 seconds
Started Feb 09 01:31:05 PM UTC 25
Finished Feb 09 01:31:08 PM UTC 25
Peak memory 226160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54257004 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 11.edn_smoke.54257004
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/11.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/11.edn_stress_all.3878732783
Short name T307
Test name
Test status
Simulation time 193547221 ps
CPU time 4.04 seconds
Started Feb 09 01:31:07 PM UTC 25
Finished Feb 09 01:31:13 PM UTC 25
Peak memory 229200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878732783 -assert nopostproc +UVM_TESTNAME=edn_stress_all
_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.3878732783
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/11.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/11.edn_stress_all_with_rand_reset.1099992688
Short name T237
Test name
Test status
Simulation time 44717870329 ps
CPU time 767.09 seconds
Started Feb 09 01:31:09 PM UTC 25
Finished Feb 09 01:44:05 PM UTC 25
Peak memory 234120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1099992688 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.1099992688
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/11.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/110.edn_alert.4227301700
Short name T709
Test name
Test status
Simulation time 141361266 ps
CPU time 1.66 seconds
Started Feb 09 01:54:01 PM UTC 25
Finished Feb 09 01:54:04 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227301700 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 110.edn_alert.4227301700
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/110.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/110.edn_genbits.3411866176
Short name T710
Test name
Test status
Simulation time 108149735 ps
CPU time 1.73 seconds
Started Feb 09 01:54:01 PM UTC 25
Finished Feb 09 01:54:04 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411866176 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 110.edn_genbits.3411866176
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/110.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/111.edn_alert.616303004
Short name T712
Test name
Test status
Simulation time 28319132 ps
CPU time 1.72 seconds
Started Feb 09 01:54:02 PM UTC 25
Finished Feb 09 01:54:05 PM UTC 25
Peak memory 228316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616303004 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 111.edn_alert.616303004
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/111.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/112.edn_alert.212902588
Short name T715
Test name
Test status
Simulation time 34807479 ps
CPU time 1.55 seconds
Started Feb 09 01:54:04 PM UTC 25
Finished Feb 09 01:54:07 PM UTC 25
Peak memory 228256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212902588 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 112.edn_alert.212902588
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/112.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/112.edn_genbits.3914418389
Short name T714
Test name
Test status
Simulation time 31116402 ps
CPU time 1.57 seconds
Started Feb 09 01:54:03 PM UTC 25
Finished Feb 09 01:54:06 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914418389 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 112.edn_genbits.3914418389
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/112.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/113.edn_alert.2368107245
Short name T718
Test name
Test status
Simulation time 282847038 ps
CPU time 2.18 seconds
Started Feb 09 01:54:04 PM UTC 25
Finished Feb 09 01:54:08 PM UTC 25
Peak memory 232132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368107245 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 113.edn_alert.2368107245
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/113.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/113.edn_genbits.3934351083
Short name T717
Test name
Test status
Simulation time 38598931 ps
CPU time 2.05 seconds
Started Feb 09 01:54:04 PM UTC 25
Finished Feb 09 01:54:07 PM UTC 25
Peak memory 229432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934351083 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 113.edn_genbits.3934351083
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/113.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/114.edn_alert.2648151426
Short name T186
Test name
Test status
Simulation time 23834230 ps
CPU time 1.66 seconds
Started Feb 09 01:54:04 PM UTC 25
Finished Feb 09 01:54:07 PM UTC 25
Peak memory 228320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648151426 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 114.edn_alert.2648151426
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/114.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/114.edn_genbits.2911659172
Short name T716
Test name
Test status
Simulation time 114915914 ps
CPU time 1.5 seconds
Started Feb 09 01:54:04 PM UTC 25
Finished Feb 09 01:54:07 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911659172 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 114.edn_genbits.2911659172
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/114.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/115.edn_alert.434075385
Short name T719
Test name
Test status
Simulation time 22858385 ps
CPU time 1.73 seconds
Started Feb 09 01:54:06 PM UTC 25
Finished Feb 09 01:54:09 PM UTC 25
Peak memory 230304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434075385 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 115.edn_alert.434075385
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/115.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/115.edn_genbits.2450030090
Short name T720
Test name
Test status
Simulation time 120963722 ps
CPU time 3.45 seconds
Started Feb 09 01:54:05 PM UTC 25
Finished Feb 09 01:54:10 PM UTC 25
Peak memory 231668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450030090 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 115.edn_genbits.2450030090
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/115.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/116.edn_alert.2272601935
Short name T721
Test name
Test status
Simulation time 340735440 ps
CPU time 2.69 seconds
Started Feb 09 01:54:07 PM UTC 25
Finished Feb 09 01:54:10 PM UTC 25
Peak memory 230088 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272601935 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 116.edn_alert.2272601935
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/116.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/116.edn_genbits.3890494017
Short name T337
Test name
Test status
Simulation time 26814737 ps
CPU time 1.95 seconds
Started Feb 09 01:54:06 PM UTC 25
Finished Feb 09 01:54:10 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890494017 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 116.edn_genbits.3890494017
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/116.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/117.edn_alert.3257863090
Short name T722
Test name
Test status
Simulation time 79498748 ps
CPU time 1.67 seconds
Started Feb 09 01:54:08 PM UTC 25
Finished Feb 09 01:54:11 PM UTC 25
Peak memory 228320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257863090 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 117.edn_alert.3257863090
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/117.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/117.edn_genbits.3257309065
Short name T725
Test name
Test status
Simulation time 236265494 ps
CPU time 3.5 seconds
Started Feb 09 01:54:08 PM UTC 25
Finished Feb 09 01:54:12 PM UTC 25
Peak memory 229360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257309065 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 117.edn_genbits.3257309065
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/117.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/118.edn_alert.3277115528
Short name T724
Test name
Test status
Simulation time 47283646 ps
CPU time 1.66 seconds
Started Feb 09 01:54:09 PM UTC 25
Finished Feb 09 01:54:12 PM UTC 25
Peak memory 228320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277115528 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 118.edn_alert.3277115528
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/118.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/118.edn_genbits.1588335079
Short name T723
Test name
Test status
Simulation time 38680394 ps
CPU time 1.96 seconds
Started Feb 09 01:54:08 PM UTC 25
Finished Feb 09 01:54:11 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588335079 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 118.edn_genbits.1588335079
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/118.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/119.edn_alert.4095434707
Short name T727
Test name
Test status
Simulation time 160594249 ps
CPU time 1.7 seconds
Started Feb 09 01:54:10 PM UTC 25
Finished Feb 09 01:54:13 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095434707 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 119.edn_alert.4095434707
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/119.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/119.edn_genbits.4002251930
Short name T726
Test name
Test status
Simulation time 35739811 ps
CPU time 2.23 seconds
Started Feb 09 01:54:09 PM UTC 25
Finished Feb 09 01:54:13 PM UTC 25
Peak memory 229432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002251930 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 119.edn_genbits.4002251930
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/119.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/12.edn_alert_test.2278357680
Short name T384
Test name
Test status
Simulation time 21297784 ps
CPU time 1.53 seconds
Started Feb 09 01:31:31 PM UTC 25
Finished Feb 09 01:31:33 PM UTC 25
Peak memory 226776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278357680 -assert nopostproc +UVM_TESTNAME=edn_base_test +UV
M_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.2278357680
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/12.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/12.edn_disable.4038750199
Short name T43
Test name
Test status
Simulation time 14217215 ps
CPU time 1.39 seconds
Started Feb 09 01:31:28 PM UTC 25
Finished Feb 09 01:31:30 PM UTC 25
Peak memory 226012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038750199 -assert nopostproc +UVM_TESTNAME=edn_disable_test +
UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.edn_disable.4038750199
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/12.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/12.edn_disable_auto_req_mode.985530916
Short name T109
Test name
Test status
Simulation time 108453402 ps
CPU time 1.74 seconds
Started Feb 09 01:31:30 PM UTC 25
Finished Feb 09 01:31:32 PM UTC 25
Peak memory 230172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985530916 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_re
q_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable_auto_req_mode.985530916
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/12.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/12.edn_err.2484168396
Short name T154
Test name
Test status
Simulation time 39618009 ps
CPU time 1.62 seconds
Started Feb 09 01:31:25 PM UTC 25
Finished Feb 09 01:31:28 PM UTC 25
Peak memory 230304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484168396 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 12.edn_err.2484168396
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/12.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/12.edn_genbits.3692825739
Short name T93
Test name
Test status
Simulation time 38268674 ps
CPU time 1.62 seconds
Started Feb 09 01:31:19 PM UTC 25
Finished Feb 09 01:31:22 PM UTC 25
Peak memory 230304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692825739 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.edn_genbits.3692825739
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/12.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/12.edn_intr.3833922652
Short name T383
Test name
Test status
Simulation time 21240364 ps
CPU time 1.62 seconds
Started Feb 09 01:31:22 PM UTC 25
Finished Feb 09 01:31:25 PM UTC 25
Peak memory 226208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833922652 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 12.edn_intr.3833922652
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/12.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/12.edn_smoke.1419574633
Short name T381
Test name
Test status
Simulation time 159909422 ps
CPU time 1.44 seconds
Started Feb 09 01:31:17 PM UTC 25
Finished Feb 09 01:31:20 PM UTC 25
Peak memory 226148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419574633 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 12.edn_smoke.1419574633
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/12.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/12.edn_stress_all.1577280173
Short name T382
Test name
Test status
Simulation time 65034768 ps
CPU time 2.38 seconds
Started Feb 09 01:31:19 PM UTC 25
Finished Feb 09 01:31:23 PM UTC 25
Peak memory 229264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577280173 -assert nopostproc +UVM_TESTNAME=edn_stress_all
_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.1577280173
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/12.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/12.edn_stress_all_with_rand_reset.2355960244
Short name T39
Test name
Test status
Simulation time 111763602254 ps
CPU time 524.92 seconds
Started Feb 09 01:31:20 PM UTC 25
Finished Feb 09 01:40:11 PM UTC 25
Peak memory 233644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2355960244 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.2355960244
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/12.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/120.edn_alert.3187746094
Short name T728
Test name
Test status
Simulation time 51292798 ps
CPU time 1.71 seconds
Started Feb 09 01:54:11 PM UTC 25
Finished Feb 09 01:54:14 PM UTC 25
Peak memory 228260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187746094 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 120.edn_alert.3187746094
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/120.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/120.edn_genbits.301725005
Short name T729
Test name
Test status
Simulation time 78328470 ps
CPU time 1.74 seconds
Started Feb 09 01:54:11 PM UTC 25
Finished Feb 09 01:54:14 PM UTC 25
Peak memory 228256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301725005 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 120.edn_genbits.301725005
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/120.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/121.edn_genbits.2043527419
Short name T731
Test name
Test status
Simulation time 108015168 ps
CPU time 2.04 seconds
Started Feb 09 01:54:11 PM UTC 25
Finished Feb 09 01:54:14 PM UTC 25
Peak memory 231668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043527419 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 121.edn_genbits.2043527419
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/121.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/122.edn_alert.2153627489
Short name T732
Test name
Test status
Simulation time 80136514 ps
CPU time 1.86 seconds
Started Feb 09 01:54:13 PM UTC 25
Finished Feb 09 01:54:16 PM UTC 25
Peak memory 228320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153627489 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 122.edn_alert.2153627489
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/122.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/122.edn_genbits.4087991909
Short name T733
Test name
Test status
Simulation time 113704390 ps
CPU time 1.95 seconds
Started Feb 09 01:54:12 PM UTC 25
Finished Feb 09 01:54:15 PM UTC 25
Peak memory 230516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087991909 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 122.edn_genbits.4087991909
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/122.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/123.edn_alert.196271065
Short name T268
Test name
Test status
Simulation time 32018901 ps
CPU time 2.03 seconds
Started Feb 09 01:54:13 PM UTC 25
Finished Feb 09 01:54:17 PM UTC 25
Peak memory 232128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196271065 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 123.edn_alert.196271065
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/123.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/123.edn_genbits.2361883724
Short name T738
Test name
Test status
Simulation time 245263998 ps
CPU time 4.16 seconds
Started Feb 09 01:54:13 PM UTC 25
Finished Feb 09 01:54:19 PM UTC 25
Peak memory 231452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361883724 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 123.edn_genbits.2361883724
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/123.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/124.edn_alert.3994400350
Short name T735
Test name
Test status
Simulation time 54397405 ps
CPU time 1.91 seconds
Started Feb 09 01:54:14 PM UTC 25
Finished Feb 09 01:54:18 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994400350 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 124.edn_alert.3994400350
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/124.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/124.edn_genbits.39344703
Short name T699
Test name
Test status
Simulation time 71662074 ps
CPU time 1.68 seconds
Started Feb 09 01:54:13 PM UTC 25
Finished Feb 09 01:54:16 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39344703 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 124.edn_genbits.39344703
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/124.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/125.edn_alert.2136383103
Short name T734
Test name
Test status
Simulation time 71385823 ps
CPU time 1.53 seconds
Started Feb 09 01:54:14 PM UTC 25
Finished Feb 09 01:54:18 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136383103 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 125.edn_alert.2136383103
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/125.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/125.edn_genbits.2667885735
Short name T736
Test name
Test status
Simulation time 40908412 ps
CPU time 2.49 seconds
Started Feb 09 01:54:14 PM UTC 25
Finished Feb 09 01:54:19 PM UTC 25
Peak memory 229368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667885735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 125.edn_genbits.2667885735
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/125.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/126.edn_alert.2112842937
Short name T740
Test name
Test status
Simulation time 211556014 ps
CPU time 2.2 seconds
Started Feb 09 01:54:15 PM UTC 25
Finished Feb 09 01:54:19 PM UTC 25
Peak memory 230024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112842937 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 126.edn_alert.2112842937
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/126.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/126.edn_genbits.4275369311
Short name T739
Test name
Test status
Simulation time 44856710 ps
CPU time 2.08 seconds
Started Feb 09 01:54:15 PM UTC 25
Finished Feb 09 01:54:19 PM UTC 25
Peak memory 229684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275369311 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 126.edn_genbits.4275369311
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/126.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/127.edn_alert.2340288803
Short name T744
Test name
Test status
Simulation time 428194995 ps
CPU time 2.31 seconds
Started Feb 09 01:54:18 PM UTC 25
Finished Feb 09 01:54:21 PM UTC 25
Peak memory 232132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340288803 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 127.edn_alert.2340288803
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/127.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/127.edn_genbits.3585469645
Short name T741
Test name
Test status
Simulation time 37456898 ps
CPU time 2.21 seconds
Started Feb 09 01:54:16 PM UTC 25
Finished Feb 09 01:54:20 PM UTC 25
Peak memory 229280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585469645 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 127.edn_genbits.3585469645
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/127.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/128.edn_alert.3128595013
Short name T743
Test name
Test status
Simulation time 22004275 ps
CPU time 1.44 seconds
Started Feb 09 01:54:19 PM UTC 25
Finished Feb 09 01:54:21 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128595013 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 128.edn_alert.3128595013
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/128.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/128.edn_genbits.2674591994
Short name T742
Test name
Test status
Simulation time 73056606 ps
CPU time 1.73 seconds
Started Feb 09 01:54:18 PM UTC 25
Finished Feb 09 01:54:21 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674591994 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 128.edn_genbits.2674591994
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/128.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/129.edn_genbits.3557613023
Short name T745
Test name
Test status
Simulation time 34219481 ps
CPU time 2.01 seconds
Started Feb 09 01:54:19 PM UTC 25
Finished Feb 09 01:54:22 PM UTC 25
Peak memory 229412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557613023 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 129.edn_genbits.3557613023
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/129.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/13.edn_alert.4206308836
Short name T159
Test name
Test status
Simulation time 24469974 ps
CPU time 1.77 seconds
Started Feb 09 01:31:49 PM UTC 25
Finished Feb 09 01:31:52 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206308836 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 13.edn_alert.4206308836
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/13.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/13.edn_alert_test.1043248960
Short name T386
Test name
Test status
Simulation time 13328257 ps
CPU time 1.35 seconds
Started Feb 09 01:32:04 PM UTC 25
Finished Feb 09 01:32:07 PM UTC 25
Peak memory 215712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043248960 -assert nopostproc +UVM_TESTNAME=edn_base_test +UV
M_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.1043248960
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/13.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/13.edn_disable.2787984953
Short name T80
Test name
Test status
Simulation time 22692113 ps
CPU time 1.34 seconds
Started Feb 09 01:31:57 PM UTC 25
Finished Feb 09 01:32:00 PM UTC 25
Peak memory 226272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787984953 -assert nopostproc +UVM_TESTNAME=edn_disable_test +
UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.edn_disable.2787984953
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/13.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/13.edn_err.1762118366
Short name T143
Test name
Test status
Simulation time 21491741 ps
CPU time 1.66 seconds
Started Feb 09 01:31:53 PM UTC 25
Finished Feb 09 01:31:56 PM UTC 25
Peak memory 230304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762118366 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 13.edn_err.1762118366
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/13.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/13.edn_genbits.959521067
Short name T79
Test name
Test status
Simulation time 34405885 ps
CPU time 1.79 seconds
Started Feb 09 01:31:34 PM UTC 25
Finished Feb 09 01:31:37 PM UTC 25
Peak memory 230080 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959521067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.edn_genbits.959521067
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/13.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/13.edn_intr.1325647606
Short name T121
Test name
Test status
Simulation time 50141116 ps
CPU time 1.5 seconds
Started Feb 09 01:31:45 PM UTC 25
Finished Feb 09 01:31:48 PM UTC 25
Peak memory 237572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325647606 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 13.edn_intr.1325647606
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/13.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/13.edn_smoke.2078131676
Short name T385
Test name
Test status
Simulation time 15016568 ps
CPU time 1.45 seconds
Started Feb 09 01:31:34 PM UTC 25
Finished Feb 09 01:31:36 PM UTC 25
Peak memory 225888 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078131676 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 13.edn_smoke.2078131676
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/13.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/13.edn_stress_all.624623546
Short name T308
Test name
Test status
Simulation time 444477256 ps
CPU time 5.83 seconds
Started Feb 09 01:31:37 PM UTC 25
Finished Feb 09 01:31:44 PM UTC 25
Peak memory 229352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624623546 -assert nopostproc +UVM_TESTNAME=edn_stress_all_
test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.624623546
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/13.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/130.edn_alert.2078196244
Short name T746
Test name
Test status
Simulation time 33815049 ps
CPU time 1.86 seconds
Started Feb 09 01:54:20 PM UTC 25
Finished Feb 09 01:54:23 PM UTC 25
Peak memory 228260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078196244 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 130.edn_alert.2078196244
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/130.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/130.edn_genbits.2072763178
Short name T749
Test name
Test status
Simulation time 140655661 ps
CPU time 3.11 seconds
Started Feb 09 01:54:20 PM UTC 25
Finished Feb 09 01:54:24 PM UTC 25
Peak memory 231608 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072763178 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 130.edn_genbits.2072763178
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/130.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/131.edn_alert.4111708624
Short name T748
Test name
Test status
Simulation time 25926295 ps
CPU time 1.82 seconds
Started Feb 09 01:54:21 PM UTC 25
Finished Feb 09 01:54:24 PM UTC 25
Peak memory 228320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111708624 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 131.edn_alert.4111708624
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/131.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/131.edn_genbits.4253046516
Short name T747
Test name
Test status
Simulation time 35259008 ps
CPU time 2.08 seconds
Started Feb 09 01:54:20 PM UTC 25
Finished Feb 09 01:54:23 PM UTC 25
Peak memory 229612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253046516 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 131.edn_genbits.4253046516
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/131.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/132.edn_alert.3140191888
Short name T750
Test name
Test status
Simulation time 46534181 ps
CPU time 1.72 seconds
Started Feb 09 01:54:22 PM UTC 25
Finished Feb 09 01:54:25 PM UTC 25
Peak memory 230308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140191888 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 132.edn_alert.3140191888
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/132.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/132.edn_genbits.1583918243
Short name T751
Test name
Test status
Simulation time 112051757 ps
CPU time 1.8 seconds
Started Feb 09 01:54:22 PM UTC 25
Finished Feb 09 01:54:25 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583918243 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 132.edn_genbits.1583918243
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/132.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/133.edn_alert.1934934740
Short name T756
Test name
Test status
Simulation time 35827891 ps
CPU time 1.88 seconds
Started Feb 09 01:54:23 PM UTC 25
Finished Feb 09 01:54:26 PM UTC 25
Peak memory 228320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934934740 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 133.edn_alert.1934934740
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/133.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/133.edn_genbits.1608297119
Short name T752
Test name
Test status
Simulation time 38942202 ps
CPU time 1.93 seconds
Started Feb 09 01:54:22 PM UTC 25
Finished Feb 09 01:54:25 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1608297119 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 133.edn_genbits.1608297119
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/133.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/134.edn_alert.297326058
Short name T758
Test name
Test status
Simulation time 28440215 ps
CPU time 1.83 seconds
Started Feb 09 01:54:24 PM UTC 25
Finished Feb 09 01:54:27 PM UTC 25
Peak memory 230304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297326058 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 134.edn_alert.297326058
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/134.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/134.edn_genbits.1094495888
Short name T757
Test name
Test status
Simulation time 71735405 ps
CPU time 1.57 seconds
Started Feb 09 01:54:24 PM UTC 25
Finished Feb 09 01:54:27 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094495888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 134.edn_genbits.1094495888
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/134.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/135.edn_alert.1063844492
Short name T760
Test name
Test status
Simulation time 33213220 ps
CPU time 1.85 seconds
Started Feb 09 01:54:25 PM UTC 25
Finished Feb 09 01:54:28 PM UTC 25
Peak memory 228320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063844492 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 135.edn_alert.1063844492
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/135.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/135.edn_genbits.220100926
Short name T759
Test name
Test status
Simulation time 37695642 ps
CPU time 2.15 seconds
Started Feb 09 01:54:24 PM UTC 25
Finished Feb 09 01:54:28 PM UTC 25
Peak memory 229352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220100926 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 135.edn_genbits.220100926
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/135.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/136.edn_alert.4288577020
Short name T761
Test name
Test status
Simulation time 89554859 ps
CPU time 1.88 seconds
Started Feb 09 01:54:25 PM UTC 25
Finished Feb 09 01:54:28 PM UTC 25
Peak memory 228320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288577020 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 136.edn_alert.4288577020
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/136.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/136.edn_genbits.1784282047
Short name T762
Test name
Test status
Simulation time 106454216 ps
CPU time 2.23 seconds
Started Feb 09 01:54:25 PM UTC 25
Finished Feb 09 01:54:29 PM UTC 25
Peak memory 229540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784282047 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 136.edn_genbits.1784282047
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/136.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/137.edn_alert.3299658340
Short name T269
Test name
Test status
Simulation time 46353124 ps
CPU time 1.75 seconds
Started Feb 09 01:54:26 PM UTC 25
Finished Feb 09 01:54:29 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299658340 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 137.edn_alert.3299658340
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/137.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/137.edn_genbits.573861920
Short name T763
Test name
Test status
Simulation time 85888748 ps
CPU time 1.63 seconds
Started Feb 09 01:54:26 PM UTC 25
Finished Feb 09 01:54:29 PM UTC 25
Peak memory 228256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573861920 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 137.edn_genbits.573861920
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/137.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/138.edn_alert.2370066458
Short name T765
Test name
Test status
Simulation time 26640756 ps
CPU time 1.67 seconds
Started Feb 09 01:54:28 PM UTC 25
Finished Feb 09 01:54:30 PM UTC 25
Peak memory 228080 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370066458 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 138.edn_alert.2370066458
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/138.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/138.edn_genbits.2121380048
Short name T764
Test name
Test status
Simulation time 58532383 ps
CPU time 1.5 seconds
Started Feb 09 01:54:28 PM UTC 25
Finished Feb 09 01:54:30 PM UTC 25
Peak memory 230144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121380048 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 138.edn_genbits.2121380048
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/138.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/139.edn_alert.2303446404
Short name T766
Test name
Test status
Simulation time 44836307 ps
CPU time 1.73 seconds
Started Feb 09 01:54:29 PM UTC 25
Finished Feb 09 01:54:32 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303446404 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 139.edn_alert.2303446404
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/139.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/139.edn_genbits.2599951658
Short name T775
Test name
Test status
Simulation time 84067758 ps
CPU time 4.34 seconds
Started Feb 09 01:54:29 PM UTC 25
Finished Feb 09 01:54:35 PM UTC 25
Peak memory 231668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599951658 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 139.edn_genbits.2599951658
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/139.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/14.edn_alert.166139507
Short name T95
Test name
Test status
Simulation time 155186221 ps
CPU time 1.87 seconds
Started Feb 09 01:32:24 PM UTC 25
Finished Feb 09 01:32:27 PM UTC 25
Peak memory 228320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166139507 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 14.edn_alert.166139507
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/14.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/14.edn_alert_test.1628950008
Short name T297
Test name
Test status
Simulation time 25503236 ps
CPU time 1.57 seconds
Started Feb 09 01:32:37 PM UTC 25
Finished Feb 09 01:32:40 PM UTC 25
Peak memory 226720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628950008 -assert nopostproc +UVM_TESTNAME=edn_base_test +UV
M_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.1628950008
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/14.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/14.edn_disable_auto_req_mode.473782773
Short name T257
Test name
Test status
Simulation time 25414844 ps
CPU time 1.45 seconds
Started Feb 09 01:32:34 PM UTC 25
Finished Feb 09 01:32:36 PM UTC 25
Peak memory 228124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473782773 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_re
q_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable_auto_req_mode.473782773
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/14.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/14.edn_err.2804250973
Short name T215
Test name
Test status
Simulation time 33970416 ps
CPU time 1.4 seconds
Started Feb 09 01:32:28 PM UTC 25
Finished Feb 09 01:32:30 PM UTC 25
Peak memory 230292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804250973 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 14.edn_err.2804250973
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/14.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/14.edn_genbits.3843375553
Short name T44
Test name
Test status
Simulation time 110326959 ps
CPU time 2 seconds
Started Feb 09 01:32:08 PM UTC 25
Finished Feb 09 01:32:11 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843375553 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.edn_genbits.3843375553
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/14.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/14.edn_smoke.3662599068
Short name T387
Test name
Test status
Simulation time 45506556 ps
CPU time 1.41 seconds
Started Feb 09 01:32:06 PM UTC 25
Finished Feb 09 01:32:09 PM UTC 25
Peak memory 226148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662599068 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 14.edn_smoke.3662599068
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/14.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/14.edn_stress_all.1602192505
Short name T114
Test name
Test status
Simulation time 535769507 ps
CPU time 7.46 seconds
Started Feb 09 01:32:10 PM UTC 25
Finished Feb 09 01:32:19 PM UTC 25
Peak memory 227544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602192505 -assert nopostproc +UVM_TESTNAME=edn_stress_all
_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.1602192505
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/14.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/14.edn_stress_all_with_rand_reset.3421037680
Short name T977
Test name
Test status
Simulation time 54210242573 ps
CPU time 1609.01 seconds
Started Feb 09 01:32:12 PM UTC 25
Finished Feb 09 01:59:19 PM UTC 25
Peak memory 234196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3421037680 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.3421037680
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/14.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/140.edn_alert.1538965048
Short name T767
Test name
Test status
Simulation time 43874226 ps
CPU time 1.63 seconds
Started Feb 09 01:54:30 PM UTC 25
Finished Feb 09 01:54:33 PM UTC 25
Peak memory 228044 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538965048 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 140.edn_alert.1538965048
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/140.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/140.edn_genbits.857553439
Short name T772
Test name
Test status
Simulation time 31873220 ps
CPU time 1.95 seconds
Started Feb 09 01:54:30 PM UTC 25
Finished Feb 09 01:54:33 PM UTC 25
Peak memory 230060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857553439 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 140.edn_genbits.857553439
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/140.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/141.edn_alert.212928762
Short name T771
Test name
Test status
Simulation time 63995262 ps
CPU time 1.78 seconds
Started Feb 09 01:54:30 PM UTC 25
Finished Feb 09 01:54:33 PM UTC 25
Peak memory 230208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212928762 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 141.edn_alert.212928762
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/141.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/141.edn_genbits.748920669
Short name T768
Test name
Test status
Simulation time 25491617 ps
CPU time 1.76 seconds
Started Feb 09 01:54:30 PM UTC 25
Finished Feb 09 01:54:33 PM UTC 25
Peak memory 230304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748920669 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 141.edn_genbits.748920669
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/141.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/142.edn_alert.3040351414
Short name T773
Test name
Test status
Simulation time 86750880 ps
CPU time 1.77 seconds
Started Feb 09 01:54:31 PM UTC 25
Finished Feb 09 01:54:34 PM UTC 25
Peak memory 228320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040351414 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 142.edn_alert.3040351414
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/142.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/143.edn_genbits.2301958862
Short name T774
Test name
Test status
Simulation time 52696616 ps
CPU time 1.86 seconds
Started Feb 09 01:54:31 PM UTC 25
Finished Feb 09 01:54:34 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301958862 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 143.edn_genbits.2301958862
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/143.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/144.edn_alert.867842776
Short name T270
Test name
Test status
Simulation time 56086679 ps
CPU time 1.99 seconds
Started Feb 09 01:54:34 PM UTC 25
Finished Feb 09 01:54:37 PM UTC 25
Peak memory 226248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867842776 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 144.edn_alert.867842776
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/144.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/144.edn_genbits.3382164650
Short name T778
Test name
Test status
Simulation time 373104588 ps
CPU time 3.3 seconds
Started Feb 09 01:54:33 PM UTC 25
Finished Feb 09 01:54:38 PM UTC 25
Peak memory 231652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382164650 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 144.edn_genbits.3382164650
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/144.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/145.edn_genbits.2439120227
Short name T776
Test name
Test status
Simulation time 44974041 ps
CPU time 1.8 seconds
Started Feb 09 01:54:34 PM UTC 25
Finished Feb 09 01:54:37 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439120227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 145.edn_genbits.2439120227
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/145.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/146.edn_alert.3771126239
Short name T781
Test name
Test status
Simulation time 56460026 ps
CPU time 1.87 seconds
Started Feb 09 01:54:35 PM UTC 25
Finished Feb 09 01:54:38 PM UTC 25
Peak memory 226116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771126239 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 146.edn_alert.3771126239
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/146.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/146.edn_genbits.943689400
Short name T782
Test name
Test status
Simulation time 82681225 ps
CPU time 4.29 seconds
Started Feb 09 01:54:34 PM UTC 25
Finished Feb 09 01:54:40 PM UTC 25
Peak memory 231656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943689400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 146.edn_genbits.943689400
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/146.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/147.edn_alert.3653365510
Short name T780
Test name
Test status
Simulation time 26541820 ps
CPU time 1.8 seconds
Started Feb 09 01:54:35 PM UTC 25
Finished Feb 09 01:54:38 PM UTC 25
Peak memory 230304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653365510 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 147.edn_alert.3653365510
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/147.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/147.edn_genbits.439073759
Short name T779
Test name
Test status
Simulation time 25692917 ps
CPU time 1.77 seconds
Started Feb 09 01:54:35 PM UTC 25
Finished Feb 09 01:54:38 PM UTC 25
Peak memory 228100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439073759 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 147.edn_genbits.439073759
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/147.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/148.edn_alert.1632166998
Short name T785
Test name
Test status
Simulation time 88929784 ps
CPU time 1.82 seconds
Started Feb 09 01:54:39 PM UTC 25
Finished Feb 09 01:54:42 PM UTC 25
Peak memory 228260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632166998 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 148.edn_alert.1632166998
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/148.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/148.edn_genbits.3041983803
Short name T783
Test name
Test status
Simulation time 111589523 ps
CPU time 2.44 seconds
Started Feb 09 01:54:37 PM UTC 25
Finished Feb 09 01:54:41 PM UTC 25
Peak memory 231592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041983803 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 148.edn_genbits.3041983803
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/148.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/149.edn_alert.2169616102
Short name T788
Test name
Test status
Simulation time 67189594 ps
CPU time 1.96 seconds
Started Feb 09 01:54:39 PM UTC 25
Finished Feb 09 01:54:42 PM UTC 25
Peak memory 226252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169616102 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 149.edn_alert.2169616102
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/149.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/149.edn_genbits.2341148911
Short name T787
Test name
Test status
Simulation time 68468791 ps
CPU time 1.93 seconds
Started Feb 09 01:54:39 PM UTC 25
Finished Feb 09 01:54:42 PM UTC 25
Peak memory 230312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341148911 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 149.edn_genbits.2341148911
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/149.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/15.edn_alert.1513250110
Short name T127
Test name
Test status
Simulation time 22307363 ps
CPU time 1.68 seconds
Started Feb 09 01:33:10 PM UTC 25
Finished Feb 09 01:33:13 PM UTC 25
Peak memory 230364 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513250110 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 15.edn_alert.1513250110
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/15.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/15.edn_alert_test.5211179
Short name T388
Test name
Test status
Simulation time 11201817 ps
CPU time 1.25 seconds
Started Feb 09 01:33:24 PM UTC 25
Finished Feb 09 01:33:27 PM UTC 25
Peak memory 216512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5211179 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_T
EST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 15.edn_alert_test.5211179
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/15.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/15.edn_disable.2166038521
Short name T73
Test name
Test status
Simulation time 14206455 ps
CPU time 1.4 seconds
Started Feb 09 01:33:17 PM UTC 25
Finished Feb 09 01:33:19 PM UTC 25
Peak memory 226012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166038521 -assert nopostproc +UVM_TESTNAME=edn_disable_test +
UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.edn_disable.2166038521
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/15.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/15.edn_err.2555950863
Short name T157
Test name
Test status
Simulation time 38807072 ps
CPU time 1.52 seconds
Started Feb 09 01:33:14 PM UTC 25
Finished Feb 09 01:33:16 PM UTC 25
Peak memory 236856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555950863 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 15.edn_err.2555950863
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/15.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/15.edn_genbits.628382968
Short name T299
Test name
Test status
Simulation time 45498233 ps
CPU time 1.69 seconds
Started Feb 09 01:32:43 PM UTC 25
Finished Feb 09 01:32:46 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628382968 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.edn_genbits.628382968
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/15.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/15.edn_intr.2452907536
Short name T111
Test name
Test status
Simulation time 58292753 ps
CPU time 1.28 seconds
Started Feb 09 01:33:07 PM UTC 25
Finished Feb 09 01:33:09 PM UTC 25
Peak memory 226208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452907536 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 15.edn_intr.2452907536
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/15.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/15.edn_smoke.1889828119
Short name T298
Test name
Test status
Simulation time 101611367 ps
CPU time 1.37 seconds
Started Feb 09 01:32:40 PM UTC 25
Finished Feb 09 01:32:43 PM UTC 25
Peak memory 226148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889828119 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 15.edn_smoke.1889828119
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/15.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/15.edn_stress_all.2825292883
Short name T300
Test name
Test status
Simulation time 551775447 ps
CPU time 7.4 seconds
Started Feb 09 01:32:47 PM UTC 25
Finished Feb 09 01:32:56 PM UTC 25
Peak memory 227292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825292883 -assert nopostproc +UVM_TESTNAME=edn_stress_all
_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.2825292883
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/15.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/15.edn_stress_all_with_rand_reset.1127707348
Short name T239
Test name
Test status
Simulation time 114645554628 ps
CPU time 766.46 seconds
Started Feb 09 01:32:56 PM UTC 25
Finished Feb 09 01:45:51 PM UTC 25
Peak memory 234196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1127707348 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.1127707348
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/15.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/150.edn_genbits.1889204239
Short name T784
Test name
Test status
Simulation time 66815640 ps
CPU time 1.54 seconds
Started Feb 09 01:54:39 PM UTC 25
Finished Feb 09 01:54:41 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889204239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 150.edn_genbits.1889204239
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/150.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/151.edn_alert.1005654993
Short name T791
Test name
Test status
Simulation time 46232990 ps
CPU time 1.74 seconds
Started Feb 09 01:54:40 PM UTC 25
Finished Feb 09 01:54:43 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005654993 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 151.edn_alert.1005654993
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/151.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/151.edn_genbits.698198325
Short name T789
Test name
Test status
Simulation time 18278699 ps
CPU time 1.56 seconds
Started Feb 09 01:54:40 PM UTC 25
Finished Feb 09 01:54:43 PM UTC 25
Peak memory 228256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698198325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 151.edn_genbits.698198325
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/151.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/152.edn_alert.1754110387
Short name T794
Test name
Test status
Simulation time 84086354 ps
CPU time 1.78 seconds
Started Feb 09 01:54:42 PM UTC 25
Finished Feb 09 01:54:45 PM UTC 25
Peak memory 228276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754110387 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 152.edn_alert.1754110387
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/152.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/152.edn_genbits.2593527786
Short name T792
Test name
Test status
Simulation time 49283042 ps
CPU time 2.04 seconds
Started Feb 09 01:54:41 PM UTC 25
Finished Feb 09 01:54:44 PM UTC 25
Peak memory 231648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593527786 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 152.edn_genbits.2593527786
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/152.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/153.edn_alert.745364813
Short name T796
Test name
Test status
Simulation time 87760887 ps
CPU time 1.87 seconds
Started Feb 09 01:54:43 PM UTC 25
Finished Feb 09 01:54:46 PM UTC 25
Peak memory 230344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745364813 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 153.edn_alert.745364813
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/153.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/153.edn_genbits.758606188
Short name T793
Test name
Test status
Simulation time 73523538 ps
CPU time 1.72 seconds
Started Feb 09 01:54:42 PM UTC 25
Finished Feb 09 01:54:45 PM UTC 25
Peak memory 230244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758606188 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 153.edn_genbits.758606188
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/153.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/154.edn_alert.4054030276
Short name T795
Test name
Test status
Simulation time 130759944 ps
CPU time 1.58 seconds
Started Feb 09 01:54:43 PM UTC 25
Finished Feb 09 01:54:46 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054030276 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 154.edn_alert.4054030276
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/154.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/155.edn_alert.399050720
Short name T798
Test name
Test status
Simulation time 24732713 ps
CPU time 1.68 seconds
Started Feb 09 01:54:44 PM UTC 25
Finished Feb 09 01:54:47 PM UTC 25
Peak memory 228256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399050720 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 155.edn_alert.399050720
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/155.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/155.edn_genbits.502938703
Short name T799
Test name
Test status
Simulation time 30943032 ps
CPU time 1.92 seconds
Started Feb 09 01:54:44 PM UTC 25
Finished Feb 09 01:54:47 PM UTC 25
Peak memory 228256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502938703 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 155.edn_genbits.502938703
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/155.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/156.edn_alert.510651454
Short name T800
Test name
Test status
Simulation time 45337773 ps
CPU time 1.74 seconds
Started Feb 09 01:54:45 PM UTC 25
Finished Feb 09 01:54:48 PM UTC 25
Peak memory 226272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510651454 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 156.edn_alert.510651454
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/156.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/156.edn_genbits.2887904410
Short name T797
Test name
Test status
Simulation time 126127351 ps
CPU time 1.59 seconds
Started Feb 09 01:54:44 PM UTC 25
Finished Feb 09 01:54:47 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887904410 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 156.edn_genbits.2887904410
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/156.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/157.edn_alert.1949846771
Short name T801
Test name
Test status
Simulation time 36349244 ps
CPU time 1.69 seconds
Started Feb 09 01:54:46 PM UTC 25
Finished Feb 09 01:54:49 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949846771 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 157.edn_alert.1949846771
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/157.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/157.edn_genbits.3619367601
Short name T802
Test name
Test status
Simulation time 49091852 ps
CPU time 2.17 seconds
Started Feb 09 01:54:46 PM UTC 25
Finished Feb 09 01:54:50 PM UTC 25
Peak memory 229276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619367601 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 157.edn_genbits.3619367601
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/157.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/158.edn_alert.2554892275
Short name T805
Test name
Test status
Simulation time 40542126 ps
CPU time 1.67 seconds
Started Feb 09 01:54:47 PM UTC 25
Finished Feb 09 01:54:50 PM UTC 25
Peak memory 228320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554892275 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 158.edn_alert.2554892275
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/158.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/158.edn_genbits.3820435412
Short name T803
Test name
Test status
Simulation time 111009716 ps
CPU time 2.24 seconds
Started Feb 09 01:54:46 PM UTC 25
Finished Feb 09 01:54:50 PM UTC 25
Peak memory 231392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820435412 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 158.edn_genbits.3820435412
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/158.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/159.edn_alert.2445485609
Short name T806
Test name
Test status
Simulation time 24949230 ps
CPU time 1.78 seconds
Started Feb 09 01:54:47 PM UTC 25
Finished Feb 09 01:54:50 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445485609 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 159.edn_alert.2445485609
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/159.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/159.edn_genbits.588624365
Short name T804
Test name
Test status
Simulation time 59007900 ps
CPU time 1.67 seconds
Started Feb 09 01:54:47 PM UTC 25
Finished Feb 09 01:54:50 PM UTC 25
Peak memory 228164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588624365 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 159.edn_genbits.588624365
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/159.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/16.edn_alert.92868765
Short name T174
Test name
Test status
Simulation time 249150655 ps
CPU time 1.91 seconds
Started Feb 09 01:34:00 PM UTC 25
Finished Feb 09 01:34:03 PM UTC 25
Peak memory 232424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92868765 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 16.edn_alert.92868765
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/16.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/16.edn_alert_test.3277380115
Short name T391
Test name
Test status
Simulation time 25496109 ps
CPU time 1.23 seconds
Started Feb 09 01:34:14 PM UTC 25
Finished Feb 09 01:34:16 PM UTC 25
Peak memory 215712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277380115 -assert nopostproc +UVM_TESTNAME=edn_base_test +UV
M_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.3277380115
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/16.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/16.edn_disable.215478071
Short name T101
Test name
Test status
Simulation time 21010851 ps
CPU time 1.3 seconds
Started Feb 09 01:34:07 PM UTC 25
Finished Feb 09 01:34:09 PM UTC 25
Peak memory 226012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215478071 -assert nopostproc +UVM_TESTNAME=edn_disable_test +U
VM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.edn_disable.215478071
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/16.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/16.edn_disable_auto_req_mode.2816441426
Short name T390
Test name
Test status
Simulation time 50397635 ps
CPU time 1.94 seconds
Started Feb 09 01:34:10 PM UTC 25
Finished Feb 09 01:34:13 PM UTC 25
Peak memory 228132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816441426 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_r
eq_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable_auto_req_mode.2816441426
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/16.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/16.edn_err.3445832538
Short name T133
Test name
Test status
Simulation time 34261833 ps
CPU time 1.36 seconds
Started Feb 09 01:34:04 PM UTC 25
Finished Feb 09 01:34:06 PM UTC 25
Peak memory 230304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445832538 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 16.edn_err.3445832538
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/16.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/16.edn_genbits.2452591075
Short name T314
Test name
Test status
Simulation time 75842228 ps
CPU time 1.65 seconds
Started Feb 09 01:33:30 PM UTC 25
Finished Feb 09 01:33:33 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452591075 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.edn_genbits.2452591075
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/16.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/16.edn_intr.2957109442
Short name T36
Test name
Test status
Simulation time 27134822 ps
CPU time 1.31 seconds
Started Feb 09 01:33:57 PM UTC 25
Finished Feb 09 01:33:59 PM UTC 25
Peak memory 228256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957109442 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 16.edn_intr.2957109442
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/16.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/16.edn_smoke.253074601
Short name T389
Test name
Test status
Simulation time 53467097 ps
CPU time 1.36 seconds
Started Feb 09 01:33:27 PM UTC 25
Finished Feb 09 01:33:30 PM UTC 25
Peak memory 226152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253074601 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 16.edn_smoke.253074601
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/16.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/16.edn_stress_all.4098557845
Short name T306
Test name
Test status
Simulation time 376616823 ps
CPU time 11.09 seconds
Started Feb 09 01:33:33 PM UTC 25
Finished Feb 09 01:33:46 PM UTC 25
Peak memory 229412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098557845 -assert nopostproc +UVM_TESTNAME=edn_stress_all
_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.4098557845
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/16.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/16.edn_stress_all_with_rand_reset.1577680486
Short name T240
Test name
Test status
Simulation time 54055032752 ps
CPU time 785.66 seconds
Started Feb 09 01:33:46 PM UTC 25
Finished Feb 09 01:47:01 PM UTC 25
Peak memory 229632 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1577680486 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.1577680486
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/16.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/160.edn_alert.1682987101
Short name T807
Test name
Test status
Simulation time 28415099 ps
CPU time 1.79 seconds
Started Feb 09 01:54:49 PM UTC 25
Finished Feb 09 01:54:52 PM UTC 25
Peak memory 228320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682987101 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 160.edn_alert.1682987101
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/160.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/160.edn_genbits.2365873409
Short name T813
Test name
Test status
Simulation time 140281296 ps
CPU time 4.17 seconds
Started Feb 09 01:54:49 PM UTC 25
Finished Feb 09 01:54:54 PM UTC 25
Peak memory 231348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365873409 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 160.edn_genbits.2365873409
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/160.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/161.edn_alert.1010602342
Short name T809
Test name
Test status
Simulation time 108417801 ps
CPU time 1.73 seconds
Started Feb 09 01:54:50 PM UTC 25
Finished Feb 09 01:54:53 PM UTC 25
Peak memory 228320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010602342 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 161.edn_alert.1010602342
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/161.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/161.edn_genbits.1422155174
Short name T808
Test name
Test status
Simulation time 41687549 ps
CPU time 2.49 seconds
Started Feb 09 01:54:49 PM UTC 25
Finished Feb 09 01:54:52 PM UTC 25
Peak memory 229604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422155174 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 161.edn_genbits.1422155174
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/161.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/162.edn_alert.3550848001
Short name T810
Test name
Test status
Simulation time 28272268 ps
CPU time 1.8 seconds
Started Feb 09 01:54:51 PM UTC 25
Finished Feb 09 01:54:54 PM UTC 25
Peak memory 230308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550848001 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 162.edn_alert.3550848001
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/162.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/162.edn_genbits.525782251
Short name T812
Test name
Test status
Simulation time 54127753 ps
CPU time 1.86 seconds
Started Feb 09 01:54:51 PM UTC 25
Finished Feb 09 01:54:54 PM UTC 25
Peak memory 228436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525782251 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 162.edn_genbits.525782251
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/162.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/163.edn_alert.949643751
Short name T814
Test name
Test status
Simulation time 82454660 ps
CPU time 1.8 seconds
Started Feb 09 01:54:51 PM UTC 25
Finished Feb 09 01:54:54 PM UTC 25
Peak memory 230304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949643751 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 163.edn_alert.949643751
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/163.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/163.edn_genbits.864842492
Short name T811
Test name
Test status
Simulation time 46782210 ps
CPU time 1.76 seconds
Started Feb 09 01:54:51 PM UTC 25
Finished Feb 09 01:54:54 PM UTC 25
Peak memory 230300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864842492 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 163.edn_genbits.864842492
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/163.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/164.edn_alert.1539381301
Short name T816
Test name
Test status
Simulation time 255466786 ps
CPU time 1.79 seconds
Started Feb 09 01:54:52 PM UTC 25
Finished Feb 09 01:54:55 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539381301 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 164.edn_alert.1539381301
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/164.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/164.edn_genbits.2732632945
Short name T815
Test name
Test status
Simulation time 35737846 ps
CPU time 2.13 seconds
Started Feb 09 01:54:51 PM UTC 25
Finished Feb 09 01:54:54 PM UTC 25
Peak memory 229612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732632945 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 164.edn_genbits.2732632945
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/164.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/165.edn_alert.930484095
Short name T817
Test name
Test status
Simulation time 103845596 ps
CPU time 1.69 seconds
Started Feb 09 01:54:53 PM UTC 25
Finished Feb 09 01:54:56 PM UTC 25
Peak memory 230164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930484095 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 165.edn_alert.930484095
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/165.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/165.edn_genbits.1158211808
Short name T818
Test name
Test status
Simulation time 50392703 ps
CPU time 1.99 seconds
Started Feb 09 01:54:53 PM UTC 25
Finished Feb 09 01:54:56 PM UTC 25
Peak memory 230404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158211808 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 165.edn_genbits.1158211808
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/165.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/166.edn_alert.1117526507
Short name T271
Test name
Test status
Simulation time 225444163 ps
CPU time 2.03 seconds
Started Feb 09 01:54:54 PM UTC 25
Finished Feb 09 01:54:57 PM UTC 25
Peak memory 228040 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117526507 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 166.edn_alert.1117526507
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/166.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/166.edn_genbits.831770431
Short name T819
Test name
Test status
Simulation time 44258710 ps
CPU time 1.56 seconds
Started Feb 09 01:54:54 PM UTC 25
Finished Feb 09 01:54:57 PM UTC 25
Peak memory 230304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831770431 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 166.edn_genbits.831770431
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/166.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/167.edn_alert.2234157863
Short name T822
Test name
Test status
Simulation time 25247631 ps
CPU time 1.77 seconds
Started Feb 09 01:54:55 PM UTC 25
Finished Feb 09 01:54:58 PM UTC 25
Peak memory 230312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234157863 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 167.edn_alert.2234157863
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/167.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/167.edn_genbits.2781600492
Short name T821
Test name
Test status
Simulation time 38028068 ps
CPU time 1.43 seconds
Started Feb 09 01:54:55 PM UTC 25
Finished Feb 09 01:54:58 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781600492 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 167.edn_genbits.2781600492
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/167.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/168.edn_alert.160736809
Short name T824
Test name
Test status
Simulation time 84811942 ps
CPU time 1.7 seconds
Started Feb 09 01:54:55 PM UTC 25
Finished Feb 09 01:54:58 PM UTC 25
Peak memory 228256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160736809 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 168.edn_alert.160736809
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/168.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/168.edn_genbits.949856128
Short name T755
Test name
Test status
Simulation time 125509335 ps
CPU time 4.19 seconds
Started Feb 09 01:54:55 PM UTC 25
Finished Feb 09 01:55:01 PM UTC 25
Peak memory 229320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949856128 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 168.edn_genbits.949856128
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/168.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/169.edn_alert.614673765
Short name T753
Test name
Test status
Simulation time 24423033 ps
CPU time 1.71 seconds
Started Feb 09 01:54:56 PM UTC 25
Finished Feb 09 01:54:59 PM UTC 25
Peak memory 228316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614673765 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 169.edn_alert.614673765
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/169.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/169.edn_genbits.803797624
Short name T823
Test name
Test status
Simulation time 42618101 ps
CPU time 1.67 seconds
Started Feb 09 01:54:55 PM UTC 25
Finished Feb 09 01:54:58 PM UTC 25
Peak memory 228256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803797624 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 169.edn_genbits.803797624
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/169.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/17.edn_alert.3056027214
Short name T123
Test name
Test status
Simulation time 28134851 ps
CPU time 1.94 seconds
Started Feb 09 01:34:44 PM UTC 25
Finished Feb 09 01:34:47 PM UTC 25
Peak memory 226256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056027214 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 17.edn_alert.3056027214
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/17.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/17.edn_alert_test.3838998100
Short name T394
Test name
Test status
Simulation time 109703657 ps
CPU time 1.36 seconds
Started Feb 09 01:34:58 PM UTC 25
Finished Feb 09 01:35:00 PM UTC 25
Peak memory 216088 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838998100 -assert nopostproc +UVM_TESTNAME=edn_base_test +UV
M_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.3838998100
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/17.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/17.edn_disable.1955639214
Short name T393
Test name
Test status
Simulation time 37982025 ps
CPU time 1.28 seconds
Started Feb 09 01:34:51 PM UTC 25
Finished Feb 09 01:34:53 PM UTC 25
Peak memory 226328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955639214 -assert nopostproc +UVM_TESTNAME=edn_disable_test +
UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.edn_disable.1955639214
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/17.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/17.edn_disable_auto_req_mode.1591509764
Short name T155
Test name
Test status
Simulation time 117815603 ps
CPU time 1.71 seconds
Started Feb 09 01:34:54 PM UTC 25
Finished Feb 09 01:34:57 PM UTC 25
Peak memory 228192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591509764 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_r
eq_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable_auto_req_mode.1591509764
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/17.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/17.edn_err.2794900665
Short name T187
Test name
Test status
Simulation time 19182151 ps
CPU time 1.23 seconds
Started Feb 09 01:34:48 PM UTC 25
Finished Feb 09 01:34:50 PM UTC 25
Peak memory 228196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794900665 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 17.edn_err.2794900665
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/17.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/17.edn_genbits.2781160905
Short name T11
Test name
Test status
Simulation time 78092463 ps
CPU time 1.83 seconds
Started Feb 09 01:34:20 PM UTC 25
Finished Feb 09 01:34:23 PM UTC 25
Peak memory 230312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781160905 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.edn_genbits.2781160905
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/17.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/17.edn_intr.377695378
Short name T112
Test name
Test status
Simulation time 22103571 ps
CPU time 1.81 seconds
Started Feb 09 01:34:40 PM UTC 25
Finished Feb 09 01:34:43 PM UTC 25
Peak memory 237900 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377695378 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 17.edn_intr.377695378
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/17.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/17.edn_smoke.2482289792
Short name T392
Test name
Test status
Simulation time 29094778 ps
CPU time 1.45 seconds
Started Feb 09 01:34:17 PM UTC 25
Finished Feb 09 01:34:20 PM UTC 25
Peak memory 226148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482289792 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 17.edn_smoke.2482289792
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/17.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/17.edn_stress_all.2583336131
Short name T309
Test name
Test status
Simulation time 181329377 ps
CPU time 5.61 seconds
Started Feb 09 01:34:24 PM UTC 25
Finished Feb 09 01:34:31 PM UTC 25
Peak memory 229332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583336131 -assert nopostproc +UVM_TESTNAME=edn_stress_all
_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.2583336131
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/17.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/17.edn_stress_all_with_rand_reset.2914739685
Short name T618
Test name
Test status
Simulation time 40195386212 ps
CPU time 1096.12 seconds
Started Feb 09 01:34:32 PM UTC 25
Finished Feb 09 01:53:01 PM UTC 25
Peak memory 231680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2914739685 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.2914739685
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/17.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/170.edn_alert.3857979648
Short name T826
Test name
Test status
Simulation time 63789954 ps
CPU time 1.63 seconds
Started Feb 09 01:54:58 PM UTC 25
Finished Feb 09 01:55:00 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857979648 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 170.edn_alert.3857979648
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/170.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/170.edn_genbits.1925592566
Short name T754
Test name
Test status
Simulation time 42284017 ps
CPU time 1.64 seconds
Started Feb 09 01:54:57 PM UTC 25
Finished Feb 09 01:55:00 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925592566 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 170.edn_genbits.1925592566
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/170.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/171.edn_alert.689927138
Short name T737
Test name
Test status
Simulation time 26821498 ps
CPU time 1.77 seconds
Started Feb 09 01:54:59 PM UTC 25
Finished Feb 09 01:55:02 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689927138 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 171.edn_alert.689927138
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/171.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/172.edn_alert.3074874145
Short name T786
Test name
Test status
Simulation time 158261099 ps
CPU time 1.67 seconds
Started Feb 09 01:54:59 PM UTC 25
Finished Feb 09 01:55:02 PM UTC 25
Peak memory 230308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074874145 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 172.edn_alert.3074874145
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/172.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/172.edn_genbits.1412369099
Short name T769
Test name
Test status
Simulation time 29801220 ps
CPU time 1.81 seconds
Started Feb 09 01:54:59 PM UTC 25
Finished Feb 09 01:55:02 PM UTC 25
Peak memory 230312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412369099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 172.edn_genbits.1412369099
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/172.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/173.edn_alert.3897630407
Short name T827
Test name
Test status
Simulation time 22769846 ps
CPU time 1.68 seconds
Started Feb 09 01:55:00 PM UTC 25
Finished Feb 09 01:55:03 PM UTC 25
Peak memory 230308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897630407 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 173.edn_alert.3897630407
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/173.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/173.edn_genbits.500878645
Short name T820
Test name
Test status
Simulation time 177051597 ps
CPU time 1.83 seconds
Started Feb 09 01:54:59 PM UTC 25
Finished Feb 09 01:55:02 PM UTC 25
Peak memory 230304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500878645 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 173.edn_genbits.500878645
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/173.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/174.edn_alert.4200297591
Short name T828
Test name
Test status
Simulation time 46639920 ps
CPU time 1.72 seconds
Started Feb 09 01:55:01 PM UTC 25
Finished Feb 09 01:55:04 PM UTC 25
Peak memory 230308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200297591 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 174.edn_alert.4200297591
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/174.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/174.edn_genbits.4070481489
Short name T831
Test name
Test status
Simulation time 138782059 ps
CPU time 2.81 seconds
Started Feb 09 01:55:01 PM UTC 25
Finished Feb 09 01:55:05 PM UTC 25
Peak memory 229344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070481489 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 174.edn_genbits.4070481489
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/174.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/175.edn_alert.819908030
Short name T833
Test name
Test status
Simulation time 70688063 ps
CPU time 1.72 seconds
Started Feb 09 01:55:02 PM UTC 25
Finished Feb 09 01:55:05 PM UTC 25
Peak memory 228256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819908030 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 175.edn_alert.819908030
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/175.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/175.edn_genbits.697595866
Short name T829
Test name
Test status
Simulation time 75082637 ps
CPU time 1.7 seconds
Started Feb 09 01:55:01 PM UTC 25
Finished Feb 09 01:55:04 PM UTC 25
Peak memory 228256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697595866 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 175.edn_genbits.697595866
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/175.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/176.edn_alert.1926545939
Short name T832
Test name
Test status
Simulation time 64192158 ps
CPU time 1.62 seconds
Started Feb 09 01:55:02 PM UTC 25
Finished Feb 09 01:55:05 PM UTC 25
Peak memory 230248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926545939 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 176.edn_alert.1926545939
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/176.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/176.edn_genbits.3584611058
Short name T830
Test name
Test status
Simulation time 70749466 ps
CPU time 1.61 seconds
Started Feb 09 01:55:02 PM UTC 25
Finished Feb 09 01:55:05 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584611058 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 176.edn_genbits.3584611058
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/176.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/177.edn_alert.4239023997
Short name T836
Test name
Test status
Simulation time 223110460 ps
CPU time 1.93 seconds
Started Feb 09 01:55:03 PM UTC 25
Finished Feb 09 01:55:06 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239023997 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 177.edn_alert.4239023997
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/177.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/177.edn_genbits.1375426674
Short name T834
Test name
Test status
Simulation time 41354619 ps
CPU time 1.63 seconds
Started Feb 09 01:55:02 PM UTC 25
Finished Feb 09 01:55:05 PM UTC 25
Peak memory 226216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375426674 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 177.edn_genbits.1375426674
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/177.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/178.edn_alert.1500598586
Short name T837
Test name
Test status
Simulation time 50788551 ps
CPU time 1.29 seconds
Started Feb 09 01:55:04 PM UTC 25
Finished Feb 09 01:55:07 PM UTC 25
Peak memory 228320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500598586 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 178.edn_alert.1500598586
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/178.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/178.edn_genbits.995699010
Short name T835
Test name
Test status
Simulation time 186092714 ps
CPU time 1.48 seconds
Started Feb 09 01:55:03 PM UTC 25
Finished Feb 09 01:55:06 PM UTC 25
Peak memory 228256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995699010 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 178.edn_genbits.995699010
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/178.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/179.edn_alert.3283544484
Short name T839
Test name
Test status
Simulation time 41095944 ps
CPU time 1.6 seconds
Started Feb 09 01:55:05 PM UTC 25
Finished Feb 09 01:55:08 PM UTC 25
Peak memory 230320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283544484 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 179.edn_alert.3283544484
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/179.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/179.edn_genbits.517957065
Short name T838
Test name
Test status
Simulation time 26964222 ps
CPU time 1.76 seconds
Started Feb 09 01:55:04 PM UTC 25
Finished Feb 09 01:55:07 PM UTC 25
Peak memory 228256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517957065 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 179.edn_genbits.517957065
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/179.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/18.edn_alert.1615340102
Short name T102
Test name
Test status
Simulation time 39301730 ps
CPU time 1.64 seconds
Started Feb 09 01:35:12 PM UTC 25
Finished Feb 09 01:35:15 PM UTC 25
Peak memory 228320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615340102 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 18.edn_alert.1615340102
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/18.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/18.edn_alert_test.2524744437
Short name T243
Test name
Test status
Simulation time 92427918 ps
CPU time 1.23 seconds
Started Feb 09 01:35:19 PM UTC 25
Finished Feb 09 01:35:21 PM UTC 25
Peak memory 216012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524744437 -assert nopostproc +UVM_TESTNAME=edn_base_test +UV
M_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.2524744437
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/18.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/18.edn_disable_auto_req_mode.3218892627
Short name T216
Test name
Test status
Simulation time 115236877 ps
CPU time 1.67 seconds
Started Feb 09 01:35:18 PM UTC 25
Finished Feb 09 01:35:21 PM UTC 25
Peak memory 228124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218892627 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_r
eq_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable_auto_req_mode.3218892627
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/18.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/18.edn_err.2423783970
Short name T158
Test name
Test status
Simulation time 74085122 ps
CPU time 1.69 seconds
Started Feb 09 01:35:15 PM UTC 25
Finished Feb 09 01:35:18 PM UTC 25
Peak memory 242108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423783970 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 18.edn_err.2423783970
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/18.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/18.edn_genbits.1942717154
Short name T74
Test name
Test status
Simulation time 66320958 ps
CPU time 3.33 seconds
Started Feb 09 01:35:04 PM UTC 25
Finished Feb 09 01:35:09 PM UTC 25
Peak memory 229344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942717154 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.edn_genbits.1942717154
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/18.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/18.edn_intr.616094735
Short name T242
Test name
Test status
Simulation time 45492468 ps
CPU time 1.01 seconds
Started Feb 09 01:35:09 PM UTC 25
Finished Feb 09 01:35:11 PM UTC 25
Peak memory 228676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616094735 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 18.edn_intr.616094735
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/18.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/18.edn_smoke.572102406
Short name T113
Test name
Test status
Simulation time 39333404 ps
CPU time 1.06 seconds
Started Feb 09 01:35:01 PM UTC 25
Finished Feb 09 01:35:03 PM UTC 25
Peak memory 226140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572102406 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 18.edn_smoke.572102406
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/18.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/18.edn_stress_all.4024417851
Short name T241
Test name
Test status
Simulation time 56098184 ps
CPU time 1.45 seconds
Started Feb 09 01:35:06 PM UTC 25
Finished Feb 09 01:35:09 PM UTC 25
Peak memory 226156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024417851 -assert nopostproc +UVM_TESTNAME=edn_stress_all
_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.4024417851
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/18.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/18.edn_stress_all_with_rand_reset.1692552567
Short name T636
Test name
Test status
Simulation time 74667588185 ps
CPU time 1078.96 seconds
Started Feb 09 01:35:09 PM UTC 25
Finished Feb 09 01:53:20 PM UTC 25
Peak memory 233656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1692552567 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.1692552567
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/18.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/180.edn_alert.2230839812
Short name T842
Test name
Test status
Simulation time 106156657 ps
CPU time 1.88 seconds
Started Feb 09 01:55:05 PM UTC 25
Finished Feb 09 01:55:09 PM UTC 25
Peak memory 226252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230839812 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 180.edn_alert.2230839812
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/180.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/180.edn_genbits.1324775586
Short name T840
Test name
Test status
Simulation time 39347100 ps
CPU time 1.86 seconds
Started Feb 09 01:55:05 PM UTC 25
Finished Feb 09 01:55:08 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324775586 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 180.edn_genbits.1324775586
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/180.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/181.edn_alert.298984703
Short name T841
Test name
Test status
Simulation time 38455314 ps
CPU time 1.88 seconds
Started Feb 09 01:55:06 PM UTC 25
Finished Feb 09 01:55:09 PM UTC 25
Peak memory 226208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298984703 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 181.edn_alert.298984703
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/181.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/181.edn_genbits.2201661571
Short name T342
Test name
Test status
Simulation time 83255480 ps
CPU time 2.15 seconds
Started Feb 09 01:55:06 PM UTC 25
Finished Feb 09 01:55:09 PM UTC 25
Peak memory 231404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201661571 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 181.edn_genbits.2201661571
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/181.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/182.edn_alert.1167056535
Short name T843
Test name
Test status
Simulation time 29506748 ps
CPU time 1.85 seconds
Started Feb 09 01:55:07 PM UTC 25
Finished Feb 09 01:55:10 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167056535 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 182.edn_alert.1167056535
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/182.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/182.edn_genbits.2150005156
Short name T356
Test name
Test status
Simulation time 45186486 ps
CPU time 2.51 seconds
Started Feb 09 01:55:07 PM UTC 25
Finished Feb 09 01:55:10 PM UTC 25
Peak memory 229612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150005156 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 182.edn_genbits.2150005156
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/182.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/183.edn_alert.2380730649
Short name T272
Test name
Test status
Simulation time 57789974 ps
CPU time 1.9 seconds
Started Feb 09 01:55:08 PM UTC 25
Finished Feb 09 01:55:11 PM UTC 25
Peak memory 226252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380730649 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 183.edn_alert.2380730649
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/183.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/183.edn_genbits.3972858001
Short name T845
Test name
Test status
Simulation time 44545738 ps
CPU time 2.29 seconds
Started Feb 09 01:55:08 PM UTC 25
Finished Feb 09 01:55:11 PM UTC 25
Peak memory 231648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972858001 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 183.edn_genbits.3972858001
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/183.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/184.edn_alert.1300789178
Short name T848
Test name
Test status
Simulation time 42469213 ps
CPU time 1.67 seconds
Started Feb 09 01:55:09 PM UTC 25
Finished Feb 09 01:55:12 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300789178 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 184.edn_alert.1300789178
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/184.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/184.edn_genbits.2692644347
Short name T844
Test name
Test status
Simulation time 59498513 ps
CPU time 1.67 seconds
Started Feb 09 01:55:08 PM UTC 25
Finished Feb 09 01:55:11 PM UTC 25
Peak memory 230312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692644347 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 184.edn_genbits.2692644347
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/184.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/185.edn_alert.3242252534
Short name T849
Test name
Test status
Simulation time 27976629 ps
CPU time 1.91 seconds
Started Feb 09 01:55:09 PM UTC 25
Finished Feb 09 01:55:12 PM UTC 25
Peak memory 228320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242252534 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 185.edn_alert.3242252534
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/185.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/185.edn_genbits.378773226
Short name T847
Test name
Test status
Simulation time 60670599 ps
CPU time 1.51 seconds
Started Feb 09 01:55:09 PM UTC 25
Finished Feb 09 01:55:12 PM UTC 25
Peak memory 228256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378773226 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 185.edn_genbits.378773226
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/185.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/186.edn_alert.2853671775
Short name T851
Test name
Test status
Simulation time 171580710 ps
CPU time 1.91 seconds
Started Feb 09 01:55:10 PM UTC 25
Finished Feb 09 01:55:13 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853671775 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 186.edn_alert.2853671775
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/186.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/186.edn_genbits.558262344
Short name T855
Test name
Test status
Simulation time 142455337 ps
CPU time 3.73 seconds
Started Feb 09 01:55:10 PM UTC 25
Finished Feb 09 01:55:15 PM UTC 25
Peak memory 231448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558262344 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 186.edn_genbits.558262344
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/186.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/187.edn_alert.3814790870
Short name T854
Test name
Test status
Simulation time 198387731 ps
CPU time 1.96 seconds
Started Feb 09 01:55:11 PM UTC 25
Finished Feb 09 01:55:14 PM UTC 25
Peak memory 226252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814790870 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 187.edn_alert.3814790870
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/187.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/187.edn_genbits.3546243842
Short name T852
Test name
Test status
Simulation time 39957079 ps
CPU time 2.14 seconds
Started Feb 09 01:55:10 PM UTC 25
Finished Feb 09 01:55:13 PM UTC 25
Peak memory 229548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546243842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 187.edn_genbits.3546243842
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/187.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/188.edn_alert.1235585054
Short name T853
Test name
Test status
Simulation time 75144941 ps
CPU time 1.52 seconds
Started Feb 09 01:55:11 PM UTC 25
Finished Feb 09 01:55:14 PM UTC 25
Peak memory 230308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235585054 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 188.edn_alert.1235585054
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/188.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/188.edn_genbits.2160766112
Short name T862
Test name
Test status
Simulation time 147808757 ps
CPU time 5.22 seconds
Started Feb 09 01:55:11 PM UTC 25
Finished Feb 09 01:55:18 PM UTC 25
Peak memory 231464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160766112 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 188.edn_genbits.2160766112
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/188.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/189.edn_alert.1510474989
Short name T857
Test name
Test status
Simulation time 46453239 ps
CPU time 1.76 seconds
Started Feb 09 01:55:12 PM UTC 25
Finished Feb 09 01:55:15 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510474989 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 189.edn_alert.1510474989
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/189.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/189.edn_genbits.638399406
Short name T860
Test name
Test status
Simulation time 60488556 ps
CPU time 3.7 seconds
Started Feb 09 01:55:12 PM UTC 25
Finished Feb 09 01:55:17 PM UTC 25
Peak memory 230852 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638399406 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 189.edn_genbits.638399406
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/189.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/19.edn_alert.3713221032
Short name T126
Test name
Test status
Simulation time 22047166 ps
CPU time 1.69 seconds
Started Feb 09 01:35:29 PM UTC 25
Finished Feb 09 01:35:32 PM UTC 25
Peak memory 228256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713221032 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 19.edn_alert.3713221032
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/19.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/19.edn_alert_test.2730484969
Short name T400
Test name
Test status
Simulation time 28242144 ps
CPU time 1.33 seconds
Started Feb 09 01:35:37 PM UTC 25
Finished Feb 09 01:35:39 PM UTC 25
Peak memory 215704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730484969 -assert nopostproc +UVM_TESTNAME=edn_base_test +UV
M_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.2730484969
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/19.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/19.edn_disable.2224516518
Short name T83
Test name
Test status
Simulation time 12930951 ps
CPU time 1.36 seconds
Started Feb 09 01:35:33 PM UTC 25
Finished Feb 09 01:35:36 PM UTC 25
Peak memory 226020 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224516518 -assert nopostproc +UVM_TESTNAME=edn_disable_test +
UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.edn_disable.2224516518
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/19.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/19.edn_err.2207578976
Short name T399
Test name
Test status
Simulation time 30202385 ps
CPU time 1.27 seconds
Started Feb 09 01:35:32 PM UTC 25
Finished Feb 09 01:35:35 PM UTC 25
Peak memory 228376 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207578976 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 19.edn_err.2207578976
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/19.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/19.edn_genbits.3685530377
Short name T396
Test name
Test status
Simulation time 38720777 ps
CPU time 2.1 seconds
Started Feb 09 01:35:22 PM UTC 25
Finished Feb 09 01:35:25 PM UTC 25
Peak memory 229276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685530377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.edn_genbits.3685530377
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/19.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/19.edn_intr.470350536
Short name T398
Test name
Test status
Simulation time 22945991 ps
CPU time 1.79 seconds
Started Feb 09 01:35:28 PM UTC 25
Finished Feb 09 01:35:31 PM UTC 25
Peak memory 237060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470350536 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 19.edn_intr.470350536
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/19.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/19.edn_smoke.3658799557
Short name T395
Test name
Test status
Simulation time 50615729 ps
CPU time 1.41 seconds
Started Feb 09 01:35:22 PM UTC 25
Finished Feb 09 01:35:24 PM UTC 25
Peak memory 226152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658799557 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 19.edn_smoke.3658799557
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/19.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/19.edn_stress_all.2456917416
Short name T397
Test name
Test status
Simulation time 94850082 ps
CPU time 2.78 seconds
Started Feb 09 01:35:25 PM UTC 25
Finished Feb 09 01:35:29 PM UTC 25
Peak memory 229260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456917416 -assert nopostproc +UVM_TESTNAME=edn_stress_all
_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.2456917416
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/19.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/19.edn_stress_all_with_rand_reset.896151180
Short name T238
Test name
Test status
Simulation time 18704617527 ps
CPU time 561.44 seconds
Started Feb 09 01:35:26 PM UTC 25
Finished Feb 09 01:44:54 PM UTC 25
Peak memory 229476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=896151180 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.896151180
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/19.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/190.edn_alert.2636147829
Short name T856
Test name
Test status
Simulation time 75240102 ps
CPU time 1.67 seconds
Started Feb 09 01:55:12 PM UTC 25
Finished Feb 09 01:55:15 PM UTC 25
Peak memory 231672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636147829 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 190.edn_alert.2636147829
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/190.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/191.edn_alert.2197728465
Short name T858
Test name
Test status
Simulation time 53392243 ps
CPU time 1.84 seconds
Started Feb 09 01:55:13 PM UTC 25
Finished Feb 09 01:55:16 PM UTC 25
Peak memory 226252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197728465 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 191.edn_alert.2197728465
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/191.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/191.edn_genbits.461691200
Short name T859
Test name
Test status
Simulation time 292254957 ps
CPU time 2.8 seconds
Started Feb 09 01:55:12 PM UTC 25
Finished Feb 09 01:55:16 PM UTC 25
Peak memory 231308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=461691200 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 191.edn_genbits.461691200
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/191.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/192.edn_alert.80845962
Short name T861
Test name
Test status
Simulation time 32719619 ps
CPU time 1.72 seconds
Started Feb 09 01:55:15 PM UTC 25
Finished Feb 09 01:55:17 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80845962 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 192.edn_alert.80845962
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/192.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/192.edn_genbits.2360901174
Short name T863
Test name
Test status
Simulation time 83261335 ps
CPU time 2.35 seconds
Started Feb 09 01:55:15 PM UTC 25
Finished Feb 09 01:55:18 PM UTC 25
Peak memory 231644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360901174 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 192.edn_genbits.2360901174
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/192.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/193.edn_alert.377540601
Short name T866
Test name
Test status
Simulation time 28262867 ps
CPU time 1.8 seconds
Started Feb 09 01:55:16 PM UTC 25
Finished Feb 09 01:55:19 PM UTC 25
Peak memory 230032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377540601 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 193.edn_alert.377540601
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/193.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/193.edn_genbits.2337264368
Short name T864
Test name
Test status
Simulation time 58751524 ps
CPU time 1.48 seconds
Started Feb 09 01:55:16 PM UTC 25
Finished Feb 09 01:55:18 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337264368 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 193.edn_genbits.2337264368
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/193.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/194.edn_alert.1503780430
Short name T867
Test name
Test status
Simulation time 50878513 ps
CPU time 1.85 seconds
Started Feb 09 01:55:16 PM UTC 25
Finished Feb 09 01:55:19 PM UTC 25
Peak memory 226252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503780430 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 194.edn_alert.1503780430
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/194.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/194.edn_genbits.3186095907
Short name T865
Test name
Test status
Simulation time 80621321 ps
CPU time 1.66 seconds
Started Feb 09 01:55:16 PM UTC 25
Finished Feb 09 01:55:19 PM UTC 25
Peak memory 230084 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186095907 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 194.edn_genbits.3186095907
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/194.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/195.edn_alert.677454388
Short name T870
Test name
Test status
Simulation time 72231487 ps
CPU time 1.63 seconds
Started Feb 09 01:55:17 PM UTC 25
Finished Feb 09 01:55:20 PM UTC 25
Peak memory 230244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677454388 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 195.edn_alert.677454388
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/195.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/195.edn_genbits.1893408144
Short name T868
Test name
Test status
Simulation time 52033371 ps
CPU time 1.98 seconds
Started Feb 09 01:55:16 PM UTC 25
Finished Feb 09 01:55:19 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893408144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 195.edn_genbits.1893408144
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/195.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/196.edn_alert.1789130987
Short name T873
Test name
Test status
Simulation time 79468342 ps
CPU time 1.75 seconds
Started Feb 09 01:55:18 PM UTC 25
Finished Feb 09 01:55:21 PM UTC 25
Peak memory 226272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789130987 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 196.edn_alert.1789130987
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/196.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/196.edn_genbits.41316290
Short name T869
Test name
Test status
Simulation time 71391616 ps
CPU time 1.58 seconds
Started Feb 09 01:55:17 PM UTC 25
Finished Feb 09 01:55:20 PM UTC 25
Peak memory 228176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41316290 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 196.edn_genbits.41316290
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/196.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/197.edn_alert.1496677273
Short name T872
Test name
Test status
Simulation time 42774139 ps
CPU time 1.64 seconds
Started Feb 09 01:55:18 PM UTC 25
Finished Feb 09 01:55:21 PM UTC 25
Peak memory 228260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496677273 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 197.edn_alert.1496677273
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/197.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/197.edn_genbits.1599737691
Short name T871
Test name
Test status
Simulation time 42584696 ps
CPU time 1.32 seconds
Started Feb 09 01:55:18 PM UTC 25
Finished Feb 09 01:55:20 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599737691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 197.edn_genbits.1599737691
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/197.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/198.edn_alert.1962578332
Short name T874
Test name
Test status
Simulation time 55435026 ps
CPU time 1.69 seconds
Started Feb 09 01:55:19 PM UTC 25
Finished Feb 09 01:55:22 PM UTC 25
Peak memory 228320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962578332 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 198.edn_alert.1962578332
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/198.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/198.edn_genbits.2501022728
Short name T875
Test name
Test status
Simulation time 81584382 ps
CPU time 1.81 seconds
Started Feb 09 01:55:19 PM UTC 25
Finished Feb 09 01:55:22 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501022728 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 198.edn_genbits.2501022728
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/198.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/199.edn_alert.4065539117
Short name T876
Test name
Test status
Simulation time 29745612 ps
CPU time 1.79 seconds
Started Feb 09 01:55:19 PM UTC 25
Finished Feb 09 01:55:22 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065539117 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 199.edn_alert.4065539117
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/199.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/199.edn_genbits.429919213
Short name T343
Test name
Test status
Simulation time 45268524 ps
CPU time 2.6 seconds
Started Feb 09 01:55:19 PM UTC 25
Finished Feb 09 01:55:23 PM UTC 25
Peak memory 229272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429919213 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 199.edn_genbits.429919213
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/199.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/2.edn_alert.2058450928
Short name T29
Test name
Test status
Simulation time 45600587 ps
CPU time 1.8 seconds
Started Feb 09 01:28:32 PM UTC 25
Finished Feb 09 01:28:35 PM UTC 25
Peak memory 228320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058450928 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 2.edn_alert.2058450928
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/2.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/2.edn_disable_auto_req_mode.1392173619
Short name T19
Test name
Test status
Simulation time 55858509 ps
CPU time 1.76 seconds
Started Feb 09 01:28:35 PM UTC 25
Finished Feb 09 01:28:38 PM UTC 25
Peak memory 228128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392173619 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_r
eq_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable_auto_req_mode.1392173619
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/2.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/2.edn_err.1362490991
Short name T69
Test name
Test status
Simulation time 45145437 ps
CPU time 1.63 seconds
Started Feb 09 01:28:34 PM UTC 25
Finished Feb 09 01:28:37 PM UTC 25
Peak memory 230312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362490991 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 2.edn_err.1362490991
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/2.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/2.edn_genbits.2167211988
Short name T15
Test name
Test status
Simulation time 74151874 ps
CPU time 3.97 seconds
Started Feb 09 01:28:24 PM UTC 25
Finished Feb 09 01:28:29 PM UTC 25
Peak memory 231328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167211988 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.edn_genbits.2167211988
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/2.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/2.edn_intr.3108055797
Short name T68
Test name
Test status
Simulation time 25187307 ps
CPU time 1.37 seconds
Started Feb 09 01:28:31 PM UTC 25
Finished Feb 09 01:28:33 PM UTC 25
Peak memory 226212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108055797 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 2.edn_intr.3108055797
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/2.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/2.edn_regwen.2373326092
Short name T27
Test name
Test status
Simulation time 26519062 ps
CPU time 1.43 seconds
Started Feb 09 01:28:22 PM UTC 25
Finished Feb 09 01:28:25 PM UTC 25
Peak memory 215908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373326092 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 2.edn_regwen.2373326092
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/2.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/2.edn_smoke.3348803050
Short name T65
Test name
Test status
Simulation time 18170586 ps
CPU time 1.5 seconds
Started Feb 09 01:28:21 PM UTC 25
Finished Feb 09 01:28:24 PM UTC 25
Peak memory 226152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348803050 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 2.edn_smoke.3348803050
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/2.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/2.edn_stress_all_with_rand_reset.14191099
Short name T985
Test name
Test status
Simulation time 621573600372 ps
CPU time 2105.24 seconds
Started Feb 09 01:28:27 PM UTC 25
Finished Feb 09 02:03:57 PM UTC 25
Peak memory 234512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=14191099 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.14191099
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/2.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/20.edn_alert.861998759
Short name T97
Test name
Test status
Simulation time 85223495 ps
CPU time 1.94 seconds
Started Feb 09 01:35:45 PM UTC 25
Finished Feb 09 01:35:48 PM UTC 25
Peak memory 226252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861998759 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 20.edn_alert.861998759
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/20.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/20.edn_alert_test.1294815201
Short name T404
Test name
Test status
Simulation time 41732229 ps
CPU time 1.31 seconds
Started Feb 09 01:35:52 PM UTC 25
Finished Feb 09 01:35:55 PM UTC 25
Peak memory 215712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294815201 -assert nopostproc +UVM_TESTNAME=edn_base_test +UV
M_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.1294815201
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/20.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/20.edn_disable.2003833369
Short name T213
Test name
Test status
Simulation time 101393120 ps
CPU time 1.29 seconds
Started Feb 09 01:35:49 PM UTC 25
Finished Feb 09 01:35:51 PM UTC 25
Peak memory 226012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003833369 -assert nopostproc +UVM_TESTNAME=edn_disable_test +
UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.edn_disable.2003833369
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/20.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/20.edn_disable_auto_req_mode.3629380073
Short name T167
Test name
Test status
Simulation time 52958986 ps
CPU time 1.7 seconds
Started Feb 09 01:35:50 PM UTC 25
Finished Feb 09 01:35:53 PM UTC 25
Peak memory 228132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629380073 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_r
eq_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable_auto_req_mode.3629380073
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/20.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/20.edn_err.3887700405
Short name T182
Test name
Test status
Simulation time 36229647 ps
CPU time 1.92 seconds
Started Feb 09 01:35:46 PM UTC 25
Finished Feb 09 01:35:49 PM UTC 25
Peak memory 242204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887700405 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 20.edn_err.3887700405
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/20.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/20.edn_genbits.357249320
Short name T75
Test name
Test status
Simulation time 38224632 ps
CPU time 2.44 seconds
Started Feb 09 01:35:39 PM UTC 25
Finished Feb 09 01:35:42 PM UTC 25
Peak memory 231732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357249320 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.edn_genbits.357249320
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/20.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/20.edn_intr.3619248784
Short name T403
Test name
Test status
Simulation time 52115652 ps
CPU time 1.3 seconds
Started Feb 09 01:35:43 PM UTC 25
Finished Feb 09 01:35:45 PM UTC 25
Peak memory 226208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619248784 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 20.edn_intr.3619248784
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/20.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/20.edn_smoke.3787181479
Short name T401
Test name
Test status
Simulation time 51161319 ps
CPU time 1.39 seconds
Started Feb 09 01:35:37 PM UTC 25
Finished Feb 09 01:35:39 PM UTC 25
Peak memory 226148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787181479 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 20.edn_smoke.3787181479
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/20.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/20.edn_stress_all.2975682107
Short name T402
Test name
Test status
Simulation time 158448733 ps
CPU time 3.15 seconds
Started Feb 09 01:35:40 PM UTC 25
Finished Feb 09 01:35:44 PM UTC 25
Peak memory 227324 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975682107 -assert nopostproc +UVM_TESTNAME=edn_stress_all
_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.2975682107
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/20.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/20.edn_stress_all_with_rand_reset.4246352226
Short name T234
Test name
Test status
Simulation time 71604202439 ps
CPU time 385.91 seconds
Started Feb 09 01:35:40 PM UTC 25
Finished Feb 09 01:42:11 PM UTC 25
Peak memory 234284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4246352226 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.4246352226
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/20.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/200.edn_genbits.3045745523
Short name T877
Test name
Test status
Simulation time 71352948 ps
CPU time 1.85 seconds
Started Feb 09 01:55:19 PM UTC 25
Finished Feb 09 01:55:22 PM UTC 25
Peak memory 230312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045745523 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 200.edn_genbits.3045745523
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/200.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/201.edn_genbits.138678972
Short name T878
Test name
Test status
Simulation time 64948599 ps
CPU time 1.57 seconds
Started Feb 09 01:55:20 PM UTC 25
Finished Feb 09 01:55:23 PM UTC 25
Peak memory 228256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138678972 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 201.edn_genbits.138678972
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/201.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/202.edn_genbits.2886141825
Short name T879
Test name
Test status
Simulation time 208507348 ps
CPU time 1.72 seconds
Started Feb 09 01:55:20 PM UTC 25
Finished Feb 09 01:55:23 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886141825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 202.edn_genbits.2886141825
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/202.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/203.edn_genbits.722812740
Short name T880
Test name
Test status
Simulation time 30891828 ps
CPU time 1.78 seconds
Started Feb 09 01:55:20 PM UTC 25
Finished Feb 09 01:55:23 PM UTC 25
Peak memory 228256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722812740 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 203.edn_genbits.722812740
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/203.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/204.edn_genbits.2058218777
Short name T882
Test name
Test status
Simulation time 47937173 ps
CPU time 2.57 seconds
Started Feb 09 01:55:21 PM UTC 25
Finished Feb 09 01:55:25 PM UTC 25
Peak memory 229124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058218777 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 204.edn_genbits.2058218777
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/204.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/205.edn_genbits.3780232311
Short name T881
Test name
Test status
Simulation time 33099473 ps
CPU time 1.84 seconds
Started Feb 09 01:55:21 PM UTC 25
Finished Feb 09 01:55:24 PM UTC 25
Peak memory 227708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780232311 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 205.edn_genbits.3780232311
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/205.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/206.edn_genbits.23743392
Short name T345
Test name
Test status
Simulation time 122423687 ps
CPU time 1.64 seconds
Started Feb 09 01:55:22 PM UTC 25
Finished Feb 09 01:55:24 PM UTC 25
Peak memory 230312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23743392 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 206.edn_genbits.23743392
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/206.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/207.edn_genbits.970814061
Short name T884
Test name
Test status
Simulation time 95206769 ps
CPU time 1.73 seconds
Started Feb 09 01:55:23 PM UTC 25
Finished Feb 09 01:55:25 PM UTC 25
Peak memory 228256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970814061 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 207.edn_genbits.970814061
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/207.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/208.edn_genbits.927523041
Short name T885
Test name
Test status
Simulation time 53052847 ps
CPU time 2.29 seconds
Started Feb 09 01:55:23 PM UTC 25
Finished Feb 09 01:55:26 PM UTC 25
Peak memory 229588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927523041 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 208.edn_genbits.927523041
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/208.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/209.edn_genbits.3633300567
Short name T886
Test name
Test status
Simulation time 54168781 ps
CPU time 2.67 seconds
Started Feb 09 01:55:23 PM UTC 25
Finished Feb 09 01:55:26 PM UTC 25
Peak memory 231332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633300567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 209.edn_genbits.3633300567
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/209.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/21.edn_alert.907105950
Short name T147
Test name
Test status
Simulation time 41332185 ps
CPU time 1.8 seconds
Started Feb 09 01:36:03 PM UTC 25
Finished Feb 09 01:36:06 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907105950 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 21.edn_alert.907105950
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/21.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/21.edn_alert_test.3796724841
Short name T410
Test name
Test status
Simulation time 25604790 ps
CPU time 1.18 seconds
Started Feb 09 01:36:18 PM UTC 25
Finished Feb 09 01:36:20 PM UTC 25
Peak memory 216528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796724841 -assert nopostproc +UVM_TESTNAME=edn_base_test +UV
M_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.3796724841
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/21.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/21.edn_disable.2570060914
Short name T189
Test name
Test status
Simulation time 13959917 ps
CPU time 1.39 seconds
Started Feb 09 01:36:11 PM UTC 25
Finished Feb 09 01:36:13 PM UTC 25
Peak memory 226012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570060914 -assert nopostproc +UVM_TESTNAME=edn_disable_test +
UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.edn_disable.2570060914
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/21.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/21.edn_disable_auto_req_mode.294914001
Short name T409
Test name
Test status
Simulation time 29129525 ps
CPU time 1.65 seconds
Started Feb 09 01:36:14 PM UTC 25
Finished Feb 09 01:36:16 PM UTC 25
Peak memory 230172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294914001 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_re
q_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable_auto_req_mode.294914001
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/21.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/21.edn_err.2513467506
Short name T128
Test name
Test status
Simulation time 36374003 ps
CPU time 1.61 seconds
Started Feb 09 01:36:07 PM UTC 25
Finished Feb 09 01:36:10 PM UTC 25
Peak memory 232352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513467506 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 21.edn_err.2513467506
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/21.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/21.edn_genbits.2438888538
Short name T406
Test name
Test status
Simulation time 245736003 ps
CPU time 1.49 seconds
Started Feb 09 01:35:55 PM UTC 25
Finished Feb 09 01:35:58 PM UTC 25
Peak memory 226216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438888538 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.edn_genbits.2438888538
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/21.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/21.edn_intr.3721972038
Short name T408
Test name
Test status
Simulation time 24308338 ps
CPU time 1.35 seconds
Started Feb 09 01:36:00 PM UTC 25
Finished Feb 09 01:36:03 PM UTC 25
Peak memory 228672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721972038 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 21.edn_intr.3721972038
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/21.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/21.edn_smoke.2261553813
Short name T405
Test name
Test status
Simulation time 39890161 ps
CPU time 1.32 seconds
Started Feb 09 01:35:54 PM UTC 25
Finished Feb 09 01:35:57 PM UTC 25
Peak memory 226152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261553813 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 21.edn_smoke.2261553813
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/21.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/21.edn_stress_all.2069996414
Short name T407
Test name
Test status
Simulation time 16846676 ps
CPU time 1.43 seconds
Started Feb 09 01:35:57 PM UTC 25
Finished Feb 09 01:36:00 PM UTC 25
Peak memory 216720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069996414 -assert nopostproc +UVM_TESTNAME=edn_stress_all
_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.2069996414
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/21.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/21.edn_stress_all_with_rand_reset.216911416
Short name T509
Test name
Test status
Simulation time 23873797560 ps
CPU time 709.25 seconds
Started Feb 09 01:35:58 PM UTC 25
Finished Feb 09 01:47:57 PM UTC 25
Peak memory 234452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=216911416 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.216911416
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/21.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/210.edn_genbits.3201125271
Short name T883
Test name
Test status
Simulation time 75187834 ps
CPU time 1.63 seconds
Started Feb 09 01:55:23 PM UTC 25
Finished Feb 09 01:55:25 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201125271 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 210.edn_genbits.3201125271
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/210.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/211.edn_genbits.1596839553
Short name T889
Test name
Test status
Simulation time 150871789 ps
CPU time 2.17 seconds
Started Feb 09 01:55:24 PM UTC 25
Finished Feb 09 01:55:27 PM UTC 25
Peak memory 231448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596839553 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 211.edn_genbits.1596839553
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/211.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/212.edn_genbits.1454193423
Short name T890
Test name
Test status
Simulation time 41419606 ps
CPU time 2.54 seconds
Started Feb 09 01:55:24 PM UTC 25
Finished Feb 09 01:55:28 PM UTC 25
Peak memory 229292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454193423 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 212.edn_genbits.1454193423
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/212.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/213.edn_genbits.2018798221
Short name T888
Test name
Test status
Simulation time 32677598 ps
CPU time 1.83 seconds
Started Feb 09 01:55:24 PM UTC 25
Finished Feb 09 01:55:27 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018798221 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 213.edn_genbits.2018798221
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/213.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/214.edn_genbits.1080820730
Short name T887
Test name
Test status
Simulation time 35170310 ps
CPU time 1.66 seconds
Started Feb 09 01:55:24 PM UTC 25
Finished Feb 09 01:55:27 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080820730 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 214.edn_genbits.1080820730
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/214.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/215.edn_genbits.1812531467
Short name T891
Test name
Test status
Simulation time 64250462 ps
CPU time 1.66 seconds
Started Feb 09 01:55:25 PM UTC 25
Finished Feb 09 01:55:28 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812531467 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 215.edn_genbits.1812531467
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/215.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/216.edn_genbits.1936283502
Short name T892
Test name
Test status
Simulation time 98119858 ps
CPU time 1.9 seconds
Started Feb 09 01:55:25 PM UTC 25
Finished Feb 09 01:55:28 PM UTC 25
Peak memory 230312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936283502 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 216.edn_genbits.1936283502
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/216.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/217.edn_genbits.1403459094
Short name T893
Test name
Test status
Simulation time 46639255 ps
CPU time 1.69 seconds
Started Feb 09 01:55:26 PM UTC 25
Finished Feb 09 01:55:29 PM UTC 25
Peak memory 230212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403459094 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 217.edn_genbits.1403459094
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/217.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/218.edn_genbits.1455672713
Short name T894
Test name
Test status
Simulation time 31115191 ps
CPU time 1.95 seconds
Started Feb 09 01:55:26 PM UTC 25
Finished Feb 09 01:55:29 PM UTC 25
Peak memory 230224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455672713 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 218.edn_genbits.1455672713
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/218.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/219.edn_genbits.2521600391
Short name T895
Test name
Test status
Simulation time 67211229 ps
CPU time 2.05 seconds
Started Feb 09 01:55:26 PM UTC 25
Finished Feb 09 01:55:29 PM UTC 25
Peak memory 231404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521600391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 219.edn_genbits.2521600391
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/219.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/22.edn_alert.3823788743
Short name T156
Test name
Test status
Simulation time 39478574 ps
CPU time 1.87 seconds
Started Feb 09 01:38:47 PM UTC 25
Finished Feb 09 01:38:50 PM UTC 25
Peak memory 230308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823788743 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 22.edn_alert.3823788743
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/22.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/22.edn_alert_test.3165034581
Short name T415
Test name
Test status
Simulation time 123778938 ps
CPU time 1.27 seconds
Started Feb 09 01:39:01 PM UTC 25
Finished Feb 09 01:39:04 PM UTC 25
Peak memory 226316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165034581 -assert nopostproc +UVM_TESTNAME=edn_base_test +UV
M_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.3165034581
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/22.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/22.edn_disable.1933348737
Short name T199
Test name
Test status
Simulation time 15781953 ps
CPU time 1.43 seconds
Started Feb 09 01:38:54 PM UTC 25
Finished Feb 09 01:38:56 PM UTC 25
Peak memory 226020 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933348737 -assert nopostproc +UVM_TESTNAME=edn_disable_test +
UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.edn_disable.1933348737
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/22.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/22.edn_disable_auto_req_mode.2532260841
Short name T414
Test name
Test status
Simulation time 233566580 ps
CPU time 1.7 seconds
Started Feb 09 01:38:57 PM UTC 25
Finished Feb 09 01:39:00 PM UTC 25
Peak memory 230180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532260841 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_r
eq_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable_auto_req_mode.2532260841
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/22.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/22.edn_genbits.669107423
Short name T76
Test name
Test status
Simulation time 57106805 ps
CPU time 2.85 seconds
Started Feb 09 01:36:24 PM UTC 25
Finished Feb 09 01:36:28 PM UTC 25
Peak memory 229268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669107423 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.edn_genbits.669107423
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/22.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/22.edn_intr.1292642450
Short name T413
Test name
Test status
Simulation time 39834708 ps
CPU time 1.39 seconds
Started Feb 09 01:38:44 PM UTC 25
Finished Feb 09 01:38:46 PM UTC 25
Peak memory 226208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292642450 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 22.edn_intr.1292642450
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/22.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/22.edn_smoke.2942103737
Short name T411
Test name
Test status
Simulation time 33259372 ps
CPU time 1.27 seconds
Started Feb 09 01:36:21 PM UTC 25
Finished Feb 09 01:36:23 PM UTC 25
Peak memory 226152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942103737 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 22.edn_smoke.2942103737
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/22.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/22.edn_stress_all.1495045186
Short name T412
Test name
Test status
Simulation time 606908046 ps
CPU time 2.97 seconds
Started Feb 09 01:36:29 PM UTC 25
Finished Feb 09 01:36:33 PM UTC 25
Peak memory 227524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495045186 -assert nopostproc +UVM_TESTNAME=edn_stress_all
_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.1495045186
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/22.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/22.edn_stress_all_with_rand_reset.118010143
Short name T983
Test name
Test status
Simulation time 136679721670 ps
CPU time 1514.59 seconds
Started Feb 09 01:36:34 PM UTC 25
Finished Feb 09 02:02:05 PM UTC 25
Peak memory 236560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=118010143 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.118010143
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/22.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/220.edn_genbits.2438403795
Short name T896
Test name
Test status
Simulation time 24256383 ps
CPU time 1.71 seconds
Started Feb 09 01:55:27 PM UTC 25
Finished Feb 09 01:55:30 PM UTC 25
Peak memory 230312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438403795 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 220.edn_genbits.2438403795
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/220.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/221.edn_genbits.2278387760
Short name T897
Test name
Test status
Simulation time 47588554 ps
CPU time 1.74 seconds
Started Feb 09 01:55:27 PM UTC 25
Finished Feb 09 01:55:30 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278387760 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 221.edn_genbits.2278387760
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/221.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/222.edn_genbits.3011505286
Short name T898
Test name
Test status
Simulation time 81505944 ps
CPU time 1.7 seconds
Started Feb 09 01:55:27 PM UTC 25
Finished Feb 09 01:55:30 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011505286 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 222.edn_genbits.3011505286
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/222.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/223.edn_genbits.4269270222
Short name T899
Test name
Test status
Simulation time 42877785 ps
CPU time 1.63 seconds
Started Feb 09 01:55:27 PM UTC 25
Finished Feb 09 01:55:30 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269270222 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 223.edn_genbits.4269270222
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/223.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/224.edn_genbits.2420605670
Short name T901
Test name
Test status
Simulation time 46613144 ps
CPU time 1.73 seconds
Started Feb 09 01:55:28 PM UTC 25
Finished Feb 09 01:55:32 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420605670 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 224.edn_genbits.2420605670
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/224.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/225.edn_genbits.409027754
Short name T900
Test name
Test status
Simulation time 86591721 ps
CPU time 1.7 seconds
Started Feb 09 01:55:28 PM UTC 25
Finished Feb 09 01:55:31 PM UTC 25
Peak memory 228256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409027754 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 225.edn_genbits.409027754
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/225.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/226.edn_genbits.2458331473
Short name T905
Test name
Test status
Simulation time 51496935 ps
CPU time 2.84 seconds
Started Feb 09 01:55:28 PM UTC 25
Finished Feb 09 01:55:33 PM UTC 25
Peak memory 231408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458331473 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 226.edn_genbits.2458331473
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/226.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/227.edn_genbits.1535826123
Short name T902
Test name
Test status
Simulation time 90956773 ps
CPU time 1.9 seconds
Started Feb 09 01:55:28 PM UTC 25
Finished Feb 09 01:55:32 PM UTC 25
Peak memory 230312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535826123 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 227.edn_genbits.1535826123
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/227.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/228.edn_genbits.3153452849
Short name T904
Test name
Test status
Simulation time 81870923 ps
CPU time 1.88 seconds
Started Feb 09 01:55:30 PM UTC 25
Finished Feb 09 01:55:33 PM UTC 25
Peak memory 228240 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153452849 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 228.edn_genbits.3153452849
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/228.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/229.edn_genbits.2476244885
Short name T903
Test name
Test status
Simulation time 32979812 ps
CPU time 1.59 seconds
Started Feb 09 01:55:30 PM UTC 25
Finished Feb 09 01:55:32 PM UTC 25
Peak memory 230500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476244885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 229.edn_genbits.2476244885
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/229.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/23.edn_alert.154889744
Short name T419
Test name
Test status
Simulation time 47995662 ps
CPU time 1.63 seconds
Started Feb 09 01:39:23 PM UTC 25
Finished Feb 09 01:39:25 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154889744 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 23.edn_alert.154889744
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/23.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/23.edn_alert_test.1495154929
Short name T422
Test name
Test status
Simulation time 25233865 ps
CPU time 1.31 seconds
Started Feb 09 01:39:35 PM UTC 25
Finished Feb 09 01:39:37 PM UTC 25
Peak memory 215712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495154929 -assert nopostproc +UVM_TESTNAME=edn_base_test +UV
M_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.1495154929
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/23.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/23.edn_disable.3374795882
Short name T421
Test name
Test status
Simulation time 18886571 ps
CPU time 1.26 seconds
Started Feb 09 01:39:29 PM UTC 25
Finished Feb 09 01:39:31 PM UTC 25
Peak memory 230116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374795882 -assert nopostproc +UVM_TESTNAME=edn_disable_test +
UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.edn_disable.3374795882
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/23.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/23.edn_disable_auto_req_mode.1585682807
Short name T146
Test name
Test status
Simulation time 90227364 ps
CPU time 1.7 seconds
Started Feb 09 01:39:32 PM UTC 25
Finished Feb 09 01:39:34 PM UTC 25
Peak memory 228124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585682807 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_r
eq_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable_auto_req_mode.1585682807
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/23.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/23.edn_err.4083319542
Short name T420
Test name
Test status
Simulation time 23921156 ps
CPU time 1.36 seconds
Started Feb 09 01:39:26 PM UTC 25
Finished Feb 09 01:39:28 PM UTC 25
Peak memory 230304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083319542 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 23.edn_err.4083319542
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/23.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/23.edn_genbits.907608354
Short name T332
Test name
Test status
Simulation time 44627580 ps
CPU time 2.28 seconds
Started Feb 09 01:39:08 PM UTC 25
Finished Feb 09 01:39:11 PM UTC 25
Peak memory 231412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907608354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.edn_genbits.907608354
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/23.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/23.edn_intr.2274096845
Short name T418
Test name
Test status
Simulation time 50045572 ps
CPU time 1.25 seconds
Started Feb 09 01:39:19 PM UTC 25
Finished Feb 09 01:39:22 PM UTC 25
Peak memory 228256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274096845 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 23.edn_intr.2274096845
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/23.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/23.edn_smoke.144718284
Short name T416
Test name
Test status
Simulation time 19620693 ps
CPU time 1.52 seconds
Started Feb 09 01:39:04 PM UTC 25
Finished Feb 09 01:39:07 PM UTC 25
Peak memory 226140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144718284 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 23.edn_smoke.144718284
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/23.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/23.edn_stress_all.3331960751
Short name T417
Test name
Test status
Simulation time 543478747 ps
CPU time 6.94 seconds
Started Feb 09 01:39:10 PM UTC 25
Finished Feb 09 01:39:18 PM UTC 25
Peak memory 229332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331960751 -assert nopostproc +UVM_TESTNAME=edn_stress_all
_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.3331960751
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/23.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/23.edn_stress_all_with_rand_reset.2678350827
Short name T244
Test name
Test status
Simulation time 115304451446 ps
CPU time 611.4 seconds
Started Feb 09 01:39:12 PM UTC 25
Finished Feb 09 01:49:32 PM UTC 25
Peak memory 234468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2678350827 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.2678350827
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/23.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/230.edn_genbits.1580004203
Short name T907
Test name
Test status
Simulation time 71094849 ps
CPU time 2.05 seconds
Started Feb 09 01:55:31 PM UTC 25
Finished Feb 09 01:55:34 PM UTC 25
Peak memory 229404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580004203 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 230.edn_genbits.1580004203
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/230.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/231.edn_genbits.2894062501
Short name T908
Test name
Test status
Simulation time 40710580 ps
CPU time 2.09 seconds
Started Feb 09 01:55:31 PM UTC 25
Finished Feb 09 01:55:34 PM UTC 25
Peak memory 229604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894062501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 231.edn_genbits.2894062501
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/231.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/232.edn_genbits.1057937328
Short name T909
Test name
Test status
Simulation time 70176220 ps
CPU time 2.04 seconds
Started Feb 09 01:55:31 PM UTC 25
Finished Feb 09 01:55:34 PM UTC 25
Peak memory 231796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057937328 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 232.edn_genbits.1057937328
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/232.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/233.edn_genbits.477151259
Short name T910
Test name
Test status
Simulation time 85185007 ps
CPU time 2.35 seconds
Started Feb 09 01:55:31 PM UTC 25
Finished Feb 09 01:55:34 PM UTC 25
Peak memory 231648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477151259 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 233.edn_genbits.477151259
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/233.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/234.edn_genbits.2055068041
Short name T906
Test name
Test status
Simulation time 47318192 ps
CPU time 1.7 seconds
Started Feb 09 01:55:31 PM UTC 25
Finished Feb 09 01:55:34 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055068041 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 234.edn_genbits.2055068041
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/234.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/235.edn_genbits.597095786
Short name T911
Test name
Test status
Simulation time 83434636 ps
CPU time 1.62 seconds
Started Feb 09 01:55:32 PM UTC 25
Finished Feb 09 01:55:35 PM UTC 25
Peak memory 228256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597095786 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 235.edn_genbits.597095786
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/235.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/236.edn_genbits.1500816409
Short name T914
Test name
Test status
Simulation time 53451476 ps
CPU time 1.95 seconds
Started Feb 09 01:55:33 PM UTC 25
Finished Feb 09 01:55:36 PM UTC 25
Peak memory 230292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500816409 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 236.edn_genbits.1500816409
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/236.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/237.edn_genbits.3730937517
Short name T912
Test name
Test status
Simulation time 105149827 ps
CPU time 1.59 seconds
Started Feb 09 01:55:33 PM UTC 25
Finished Feb 09 01:55:36 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730937517 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 237.edn_genbits.3730937517
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/237.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/238.edn_genbits.3823199764
Short name T913
Test name
Test status
Simulation time 54766365 ps
CPU time 1.69 seconds
Started Feb 09 01:55:33 PM UTC 25
Finished Feb 09 01:55:36 PM UTC 25
Peak memory 230312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823199764 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 238.edn_genbits.3823199764
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/238.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/239.edn_genbits.942358422
Short name T915
Test name
Test status
Simulation time 36426082 ps
CPU time 2.59 seconds
Started Feb 09 01:55:33 PM UTC 25
Finished Feb 09 01:55:37 PM UTC 25
Peak memory 229612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942358422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 239.edn_genbits.942358422
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/239.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/24.edn_alert.3775259970
Short name T163
Test name
Test status
Simulation time 89131495 ps
CPU time 1.79 seconds
Started Feb 09 01:40:15 PM UTC 25
Finished Feb 09 01:40:18 PM UTC 25
Peak memory 228320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775259970 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 24.edn_alert.3775259970
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/24.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/24.edn_alert_test.496535238
Short name T426
Test name
Test status
Simulation time 209349707 ps
CPU time 1.42 seconds
Started Feb 09 01:40:30 PM UTC 25
Finished Feb 09 01:40:33 PM UTC 25
Peak memory 216096 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496535238 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM
_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.496535238
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/24.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/24.edn_disable.1279768577
Short name T190
Test name
Test status
Simulation time 23109895 ps
CPU time 1.17 seconds
Started Feb 09 01:40:23 PM UTC 25
Finished Feb 09 01:40:26 PM UTC 25
Peak memory 230116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279768577 -assert nopostproc +UVM_TESTNAME=edn_disable_test +
UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.edn_disable.1279768577
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/24.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/24.edn_disable_auto_req_mode.2916621080
Short name T231
Test name
Test status
Simulation time 124824650 ps
CPU time 1.47 seconds
Started Feb 09 01:40:26 PM UTC 25
Finished Feb 09 01:40:29 PM UTC 25
Peak memory 230168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916621080 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_r
eq_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable_auto_req_mode.2916621080
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/24.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/24.edn_err.3204284877
Short name T425
Test name
Test status
Simulation time 23649355 ps
CPU time 1.41 seconds
Started Feb 09 01:40:19 PM UTC 25
Finished Feb 09 01:40:22 PM UTC 25
Peak memory 228256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204284877 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 24.edn_err.3204284877
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/24.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/24.edn_intr.2738585257
Short name T424
Test name
Test status
Simulation time 40423762 ps
CPU time 1.26 seconds
Started Feb 09 01:40:12 PM UTC 25
Finished Feb 09 01:40:15 PM UTC 25
Peak memory 226268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738585257 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 24.edn_intr.2738585257
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/24.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/24.edn_smoke.1681901308
Short name T423
Test name
Test status
Simulation time 18378939 ps
CPU time 1.56 seconds
Started Feb 09 01:39:38 PM UTC 25
Finished Feb 09 01:39:41 PM UTC 25
Peak memory 226148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681901308 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 24.edn_smoke.1681901308
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/24.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/24.edn_stress_all.1417841107
Short name T252
Test name
Test status
Simulation time 1665753968 ps
CPU time 8.5 seconds
Started Feb 09 01:39:46 PM UTC 25
Finished Feb 09 01:39:56 PM UTC 25
Peak memory 229356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417841107 -assert nopostproc +UVM_TESTNAME=edn_stress_all
_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.1417841107
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/24.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/24.edn_stress_all_with_rand_reset.961975167
Short name T984
Test name
Test status
Simulation time 52549956380 ps
CPU time 1357.16 seconds
Started Feb 09 01:39:57 PM UTC 25
Finished Feb 09 02:02:49 PM UTC 25
Peak memory 234192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=961975167 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.961975167
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/24.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/240.edn_genbits.2598243797
Short name T349
Test name
Test status
Simulation time 31202516 ps
CPU time 1.69 seconds
Started Feb 09 01:55:33 PM UTC 25
Finished Feb 09 01:55:36 PM UTC 25
Peak memory 230312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598243797 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 240.edn_genbits.2598243797
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/240.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/241.edn_genbits.1570744302
Short name T916
Test name
Test status
Simulation time 41766324 ps
CPU time 1.63 seconds
Started Feb 09 01:55:34 PM UTC 25
Finished Feb 09 01:55:37 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570744302 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 241.edn_genbits.1570744302
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/241.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/242.edn_genbits.2323825380
Short name T917
Test name
Test status
Simulation time 35107892 ps
CPU time 1.99 seconds
Started Feb 09 01:55:35 PM UTC 25
Finished Feb 09 01:55:38 PM UTC 25
Peak memory 228192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323825380 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 242.edn_genbits.2323825380
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/242.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/243.edn_genbits.1470759583
Short name T850
Test name
Test status
Simulation time 42756011 ps
CPU time 1.79 seconds
Started Feb 09 01:55:35 PM UTC 25
Finished Feb 09 01:55:38 PM UTC 25
Peak memory 230516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470759583 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 243.edn_genbits.1470759583
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/243.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/244.edn_genbits.3033700665
Short name T919
Test name
Test status
Simulation time 180416588 ps
CPU time 2.07 seconds
Started Feb 09 01:55:35 PM UTC 25
Finished Feb 09 01:55:39 PM UTC 25
Peak memory 229712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033700665 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 244.edn_genbits.3033700665
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/244.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/245.edn_genbits.598536679
Short name T926
Test name
Test status
Simulation time 134278295 ps
CPU time 4.42 seconds
Started Feb 09 01:55:35 PM UTC 25
Finished Feb 09 01:55:41 PM UTC 25
Peak memory 231656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598536679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 245.edn_genbits.598536679
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/245.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/246.edn_genbits.3415613707
Short name T918
Test name
Test status
Simulation time 35976245 ps
CPU time 1.82 seconds
Started Feb 09 01:55:35 PM UTC 25
Finished Feb 09 01:55:38 PM UTC 25
Peak memory 230312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415613707 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 246.edn_genbits.3415613707
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/246.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/247.edn_genbits.4152960997
Short name T925
Test name
Test status
Simulation time 123055711 ps
CPU time 3.27 seconds
Started Feb 09 01:55:36 PM UTC 25
Finished Feb 09 01:55:41 PM UTC 25
Peak memory 229428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152960997 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 247.edn_genbits.4152960997
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/247.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/248.edn_genbits.626694703
Short name T920
Test name
Test status
Simulation time 56741674 ps
CPU time 1.85 seconds
Started Feb 09 01:55:36 PM UTC 25
Finished Feb 09 01:55:39 PM UTC 25
Peak memory 230296 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626694703 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 248.edn_genbits.626694703
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/248.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/249.edn_genbits.4097420803
Short name T921
Test name
Test status
Simulation time 35966709 ps
CPU time 1.94 seconds
Started Feb 09 01:55:36 PM UTC 25
Finished Feb 09 01:55:39 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097420803 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 249.edn_genbits.4097420803
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/249.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/25.edn_alert.3466974099
Short name T103
Test name
Test status
Simulation time 134831883 ps
CPU time 1.7 seconds
Started Feb 09 01:41:18 PM UTC 25
Finished Feb 09 01:41:21 PM UTC 25
Peak memory 228260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466974099 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 25.edn_alert.3466974099
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/25.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/25.edn_alert_test.2318661699
Short name T431
Test name
Test status
Simulation time 62104204 ps
CPU time 1.42 seconds
Started Feb 09 01:41:32 PM UTC 25
Finished Feb 09 01:41:35 PM UTC 25
Peak memory 217252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318661699 -assert nopostproc +UVM_TESTNAME=edn_base_test +UV
M_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.2318661699
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/25.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/25.edn_disable.743317154
Short name T430
Test name
Test status
Simulation time 73730326 ps
CPU time 1.26 seconds
Started Feb 09 01:41:25 PM UTC 25
Finished Feb 09 01:41:28 PM UTC 25
Peak memory 226020 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743317154 -assert nopostproc +UVM_TESTNAME=edn_disable_test +U
VM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.edn_disable.743317154
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/25.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/25.edn_disable_auto_req_mode.1331075773
Short name T217
Test name
Test status
Simulation time 70440815 ps
CPU time 1.87 seconds
Started Feb 09 01:41:28 PM UTC 25
Finished Feb 09 01:41:32 PM UTC 25
Peak memory 228124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331075773 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_r
eq_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable_auto_req_mode.1331075773
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/25.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/25.edn_err.69286133
Short name T429
Test name
Test status
Simulation time 42308029 ps
CPU time 1.29 seconds
Started Feb 09 01:41:22 PM UTC 25
Finished Feb 09 01:41:25 PM UTC 25
Peak memory 228196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69286133 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 25.edn_err.69286133
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/25.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/25.edn_genbits.189714025
Short name T98
Test name
Test status
Simulation time 100647901 ps
CPU time 1.8 seconds
Started Feb 09 01:40:36 PM UTC 25
Finished Feb 09 01:40:39 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189714025 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.edn_genbits.189714025
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/25.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/25.edn_intr.3958267159
Short name T428
Test name
Test status
Simulation time 40982619 ps
CPU time 1.54 seconds
Started Feb 09 01:41:15 PM UTC 25
Finished Feb 09 01:41:18 PM UTC 25
Peak memory 236592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958267159 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 25.edn_intr.3958267159
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/25.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/25.edn_smoke.3690132705
Short name T427
Test name
Test status
Simulation time 17616704 ps
CPU time 1.54 seconds
Started Feb 09 01:40:33 PM UTC 25
Finished Feb 09 01:40:36 PM UTC 25
Peak memory 226148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690132705 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 25.edn_smoke.3690132705
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/25.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/25.edn_stress_all.638722375
Short name T310
Test name
Test status
Simulation time 904175201 ps
CPU time 7.23 seconds
Started Feb 09 01:40:40 PM UTC 25
Finished Feb 09 01:40:49 PM UTC 25
Peak memory 229264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638722375 -assert nopostproc +UVM_TESTNAME=edn_stress_all_
test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.638722375
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/25.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/25.edn_stress_all_with_rand_reset.2078090659
Short name T982
Test name
Test status
Simulation time 100841485895 ps
CPU time 1253.81 seconds
Started Feb 09 01:40:50 PM UTC 25
Finished Feb 09 02:01:58 PM UTC 25
Peak memory 234344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2078090659 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.2078090659
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/25.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/250.edn_genbits.1378978305
Short name T922
Test name
Test status
Simulation time 41791712 ps
CPU time 2.1 seconds
Started Feb 09 01:55:36 PM UTC 25
Finished Feb 09 01:55:40 PM UTC 25
Peak memory 229276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378978305 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 250.edn_genbits.1378978305
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/250.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/251.edn_genbits.3112251988
Short name T923
Test name
Test status
Simulation time 76689660 ps
CPU time 1.75 seconds
Started Feb 09 01:55:38 PM UTC 25
Finished Feb 09 01:55:41 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112251988 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 251.edn_genbits.3112251988
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/251.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/252.edn_genbits.3729758234
Short name T924
Test name
Test status
Simulation time 77670653 ps
CPU time 1.96 seconds
Started Feb 09 01:55:38 PM UTC 25
Finished Feb 09 01:55:41 PM UTC 25
Peak memory 230312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729758234 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 252.edn_genbits.3729758234
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/252.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/253.edn_genbits.1018057739
Short name T927
Test name
Test status
Simulation time 41853817 ps
CPU time 1.86 seconds
Started Feb 09 01:55:39 PM UTC 25
Finished Feb 09 01:55:42 PM UTC 25
Peak memory 230516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018057739 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 253.edn_genbits.1018057739
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/253.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/254.edn_genbits.4192561892
Short name T928
Test name
Test status
Simulation time 120438743 ps
CPU time 2.37 seconds
Started Feb 09 01:55:39 PM UTC 25
Finished Feb 09 01:55:42 PM UTC 25
Peak memory 231408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192561892 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 254.edn_genbits.4192561892
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/254.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/255.edn_genbits.3339625093
Short name T930
Test name
Test status
Simulation time 55010686 ps
CPU time 2.21 seconds
Started Feb 09 01:55:40 PM UTC 25
Finished Feb 09 01:55:43 PM UTC 25
Peak memory 231608 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339625093 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 255.edn_genbits.3339625093
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/255.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/256.edn_genbits.2201016430
Short name T929
Test name
Test status
Simulation time 66048014 ps
CPU time 1.87 seconds
Started Feb 09 01:55:40 PM UTC 25
Finished Feb 09 01:55:43 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201016430 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 256.edn_genbits.2201016430
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/256.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/257.edn_genbits.739287239
Short name T931
Test name
Test status
Simulation time 89005188 ps
CPU time 2.36 seconds
Started Feb 09 01:55:40 PM UTC 25
Finished Feb 09 01:55:43 PM UTC 25
Peak memory 231324 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739287239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 257.edn_genbits.739287239
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/257.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/258.edn_genbits.1262797630
Short name T933
Test name
Test status
Simulation time 59718755 ps
CPU time 1.95 seconds
Started Feb 09 01:55:41 PM UTC 25
Finished Feb 09 01:55:44 PM UTC 25
Peak memory 230312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262797630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 258.edn_genbits.1262797630
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/258.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/259.edn_genbits.3186009136
Short name T932
Test name
Test status
Simulation time 76217375 ps
CPU time 1.71 seconds
Started Feb 09 01:55:41 PM UTC 25
Finished Feb 09 01:55:44 PM UTC 25
Peak memory 230312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186009136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 259.edn_genbits.3186009136
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/259.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/26.edn_alert.2934149595
Short name T164
Test name
Test status
Simulation time 52769033 ps
CPU time 1.86 seconds
Started Feb 09 01:42:11 PM UTC 25
Finished Feb 09 01:42:14 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934149595 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 26.edn_alert.2934149595
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/26.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/26.edn_alert_test.475291559
Short name T436
Test name
Test status
Simulation time 19348771 ps
CPU time 1.5 seconds
Started Feb 09 01:42:17 PM UTC 25
Finished Feb 09 01:42:20 PM UTC 25
Peak memory 216900 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475291559 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM
_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.475291559
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/26.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/26.edn_disable.788212548
Short name T200
Test name
Test status
Simulation time 13804692 ps
CPU time 1.4 seconds
Started Feb 09 01:42:15 PM UTC 25
Finished Feb 09 01:42:18 PM UTC 25
Peak memory 226012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788212548 -assert nopostproc +UVM_TESTNAME=edn_disable_test +U
VM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.edn_disable.788212548
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/26.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/26.edn_disable_auto_req_mode.649355873
Short name T435
Test name
Test status
Simulation time 46645365 ps
CPU time 1.59 seconds
Started Feb 09 01:42:15 PM UTC 25
Finished Feb 09 01:42:18 PM UTC 25
Peak memory 230172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649355873 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_re
q_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable_auto_req_mode.649355873
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/26.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/26.edn_err.3520337354
Short name T144
Test name
Test status
Simulation time 47253080 ps
CPU time 1.2 seconds
Started Feb 09 01:42:12 PM UTC 25
Finished Feb 09 01:42:15 PM UTC 25
Peak memory 230284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520337354 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 26.edn_err.3520337354
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/26.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/26.edn_genbits.3866391152
Short name T433
Test name
Test status
Simulation time 32242966 ps
CPU time 1.88 seconds
Started Feb 09 01:41:39 PM UTC 25
Finished Feb 09 01:41:42 PM UTC 25
Peak memory 230304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866391152 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.edn_genbits.3866391152
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/26.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/26.edn_smoke.1239023758
Short name T432
Test name
Test status
Simulation time 37485057 ps
CPU time 1.31 seconds
Started Feb 09 01:41:36 PM UTC 25
Finished Feb 09 01:41:38 PM UTC 25
Peak memory 226152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239023758 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 26.edn_smoke.1239023758
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/26.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/26.edn_stress_all.3118438740
Short name T434
Test name
Test status
Simulation time 370774621 ps
CPU time 10.25 seconds
Started Feb 09 01:41:43 PM UTC 25
Finished Feb 09 01:41:54 PM UTC 25
Peak memory 227552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118438740 -assert nopostproc +UVM_TESTNAME=edn_stress_all
_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.3118438740
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/26.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/26.edn_stress_all_with_rand_reset.2845512407
Short name T980
Test name
Test status
Simulation time 77950336325 ps
CPU time 1159.13 seconds
Started Feb 09 01:41:55 PM UTC 25
Finished Feb 09 02:01:27 PM UTC 25
Peak memory 234084 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2845512407 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.2845512407
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/26.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/260.edn_genbits.442514883
Short name T935
Test name
Test status
Simulation time 115868753 ps
CPU time 2.61 seconds
Started Feb 09 01:55:41 PM UTC 25
Finished Feb 09 01:55:45 PM UTC 25
Peak memory 229344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442514883 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 260.edn_genbits.442514883
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/260.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/261.edn_genbits.1246269266
Short name T934
Test name
Test status
Simulation time 83985250 ps
CPU time 1.49 seconds
Started Feb 09 01:55:42 PM UTC 25
Finished Feb 09 01:55:45 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246269266 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 261.edn_genbits.1246269266
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/261.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/262.edn_genbits.407033618
Short name T938
Test name
Test status
Simulation time 57271393 ps
CPU time 1.91 seconds
Started Feb 09 01:55:42 PM UTC 25
Finished Feb 09 01:55:45 PM UTC 25
Peak memory 228236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407033618 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 262.edn_genbits.407033618
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/262.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/263.edn_genbits.104066845
Short name T937
Test name
Test status
Simulation time 22483366 ps
CPU time 1.84 seconds
Started Feb 09 01:55:42 PM UTC 25
Finished Feb 09 01:55:45 PM UTC 25
Peak memory 228280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104066845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 263.edn_genbits.104066845
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/263.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/264.edn_genbits.3793959571
Short name T936
Test name
Test status
Simulation time 58635621 ps
CPU time 1.5 seconds
Started Feb 09 01:55:42 PM UTC 25
Finished Feb 09 01:55:45 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793959571 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 264.edn_genbits.3793959571
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/264.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/265.edn_genbits.1716840179
Short name T939
Test name
Test status
Simulation time 60682407 ps
CPU time 1.82 seconds
Started Feb 09 01:55:43 PM UTC 25
Finished Feb 09 01:55:46 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716840179 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 265.edn_genbits.1716840179
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/265.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/266.edn_genbits.2301626853
Short name T940
Test name
Test status
Simulation time 77305535 ps
CPU time 2.14 seconds
Started Feb 09 01:55:43 PM UTC 25
Finished Feb 09 01:55:46 PM UTC 25
Peak memory 229344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301626853 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 266.edn_genbits.2301626853
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/266.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/267.edn_genbits.1099472443
Short name T944
Test name
Test status
Simulation time 34962273 ps
CPU time 1.88 seconds
Started Feb 09 01:55:44 PM UTC 25
Finished Feb 09 01:55:47 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099472443 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 267.edn_genbits.1099472443
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/267.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/268.edn_genbits.3858272109
Short name T943
Test name
Test status
Simulation time 50660660 ps
CPU time 1.66 seconds
Started Feb 09 01:55:44 PM UTC 25
Finished Feb 09 01:55:47 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858272109 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 268.edn_genbits.3858272109
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/268.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/269.edn_genbits.1120723308
Short name T941
Test name
Test status
Simulation time 124341869 ps
CPU time 1.27 seconds
Started Feb 09 01:55:44 PM UTC 25
Finished Feb 09 01:55:47 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120723308 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 269.edn_genbits.1120723308
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/269.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/27.edn_alert.1133981975
Short name T441
Test name
Test status
Simulation time 36928861 ps
CPU time 1.81 seconds
Started Feb 09 01:42:23 PM UTC 25
Finished Feb 09 01:42:27 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133981975 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 27.edn_alert.1133981975
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/27.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/27.edn_alert_test.727329077
Short name T442
Test name
Test status
Simulation time 10679862 ps
CPU time 1.26 seconds
Started Feb 09 01:42:28 PM UTC 25
Finished Feb 09 01:42:30 PM UTC 25
Peak memory 216468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727329077 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM
_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.727329077
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/27.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/27.edn_disable.1781563062
Short name T232
Test name
Test status
Simulation time 17028970 ps
CPU time 1.25 seconds
Started Feb 09 01:42:24 PM UTC 25
Finished Feb 09 01:42:27 PM UTC 25
Peak memory 226012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781563062 -assert nopostproc +UVM_TESTNAME=edn_disable_test +
UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.edn_disable.1781563062
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/27.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/27.edn_disable_auto_req_mode.141879912
Short name T444
Test name
Test status
Simulation time 54376300 ps
CPU time 1.73 seconds
Started Feb 09 01:42:27 PM UTC 25
Finished Feb 09 01:42:31 PM UTC 25
Peak memory 228124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141879912 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_re
q_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable_auto_req_mode.141879912
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/27.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/27.edn_err.3551230315
Short name T440
Test name
Test status
Simulation time 45915587 ps
CPU time 1.42 seconds
Started Feb 09 01:42:23 PM UTC 25
Finished Feb 09 01:42:26 PM UTC 25
Peak memory 236856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551230315 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 27.edn_err.3551230315
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/27.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/27.edn_genbits.3227717819
Short name T84
Test name
Test status
Simulation time 59396858 ps
CPU time 2.43 seconds
Started Feb 09 01:42:19 PM UTC 25
Finished Feb 09 01:42:23 PM UTC 25
Peak memory 229620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227717819 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.edn_genbits.3227717819
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/27.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/27.edn_intr.3170477366
Short name T439
Test name
Test status
Simulation time 21326209 ps
CPU time 1.62 seconds
Started Feb 09 01:42:20 PM UTC 25
Finished Feb 09 01:42:23 PM UTC 25
Peak memory 228256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170477366 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 27.edn_intr.3170477366
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/27.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/27.edn_smoke.3930024941
Short name T437
Test name
Test status
Simulation time 28168377 ps
CPU time 1.47 seconds
Started Feb 09 01:42:17 PM UTC 25
Finished Feb 09 01:42:20 PM UTC 25
Peak memory 215972 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930024941 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 27.edn_smoke.3930024941
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/27.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/27.edn_stress_all.893367325
Short name T438
Test name
Test status
Simulation time 262004584 ps
CPU time 1.61 seconds
Started Feb 09 01:42:19 PM UTC 25
Finished Feb 09 01:42:22 PM UTC 25
Peak memory 216712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893367325 -assert nopostproc +UVM_TESTNAME=edn_stress_all_
test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.893367325
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/27.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/27.edn_stress_all_with_rand_reset.3100018091
Short name T994
Test name
Test status
Simulation time 414573131127 ps
CPU time 2199.89 seconds
Started Feb 09 01:42:20 PM UTC 25
Finished Feb 09 02:19:25 PM UTC 25
Peak memory 238440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3100018091 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.3100018091
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/27.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/270.edn_genbits.325054881
Short name T942
Test name
Test status
Simulation time 57789192 ps
CPU time 1.49 seconds
Started Feb 09 01:55:44 PM UTC 25
Finished Feb 09 01:55:47 PM UTC 25
Peak memory 228256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325054881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 270.edn_genbits.325054881
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/270.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/271.edn_genbits.3693579056
Short name T947
Test name
Test status
Simulation time 31846663 ps
CPU time 2.04 seconds
Started Feb 09 01:55:45 PM UTC 25
Finished Feb 09 01:55:49 PM UTC 25
Peak memory 229288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693579056 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 271.edn_genbits.3693579056
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/271.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/272.edn_genbits.2454802400
Short name T945
Test name
Test status
Simulation time 90302901 ps
CPU time 1.81 seconds
Started Feb 09 01:55:45 PM UTC 25
Finished Feb 09 01:55:49 PM UTC 25
Peak memory 230152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454802400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 272.edn_genbits.2454802400
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/272.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/273.edn_genbits.3120320491
Short name T948
Test name
Test status
Simulation time 98911956 ps
CPU time 2.21 seconds
Started Feb 09 01:55:46 PM UTC 25
Finished Feb 09 01:55:49 PM UTC 25
Peak memory 229344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120320491 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 273.edn_genbits.3120320491
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/273.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/274.edn_genbits.3429478279
Short name T946
Test name
Test status
Simulation time 44415514 ps
CPU time 1.84 seconds
Started Feb 09 01:55:46 PM UTC 25
Finished Feb 09 01:55:49 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429478279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 274.edn_genbits.3429478279
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/274.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/275.edn_genbits.1677875649
Short name T949
Test name
Test status
Simulation time 53639462 ps
CPU time 2.97 seconds
Started Feb 09 01:55:46 PM UTC 25
Finished Feb 09 01:55:50 PM UTC 25
Peak memory 231668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677875649 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 275.edn_genbits.1677875649
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/275.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/276.edn_genbits.3552146773
Short name T950
Test name
Test status
Simulation time 100837981 ps
CPU time 2.43 seconds
Started Feb 09 01:55:47 PM UTC 25
Finished Feb 09 01:55:50 PM UTC 25
Peak memory 229368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552146773 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 276.edn_genbits.3552146773
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/276.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/277.edn_genbits.1135610164
Short name T952
Test name
Test status
Simulation time 140077041 ps
CPU time 1.57 seconds
Started Feb 09 01:55:48 PM UTC 25
Finished Feb 09 01:55:51 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135610164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 277.edn_genbits.1135610164
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/277.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/278.edn_genbits.315720286
Short name T953
Test name
Test status
Simulation time 52435576 ps
CPU time 1.73 seconds
Started Feb 09 01:55:48 PM UTC 25
Finished Feb 09 01:55:51 PM UTC 25
Peak memory 230304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315720286 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 278.edn_genbits.315720286
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/278.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/279.edn_genbits.2278846139
Short name T951
Test name
Test status
Simulation time 62303477 ps
CPU time 1.48 seconds
Started Feb 09 01:55:48 PM UTC 25
Finished Feb 09 01:55:51 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278846139 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 279.edn_genbits.2278846139
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/279.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/28.edn_alert_test.2436769723
Short name T448
Test name
Test status
Simulation time 90743884 ps
CPU time 1.25 seconds
Started Feb 09 01:42:47 PM UTC 25
Finished Feb 09 01:42:50 PM UTC 25
Peak memory 216132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436769723 -assert nopostproc +UVM_TESTNAME=edn_base_test +UV
M_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.2436769723
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/28.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/28.edn_disable.1564821140
Short name T233
Test name
Test status
Simulation time 18818995 ps
CPU time 1.25 seconds
Started Feb 09 01:42:44 PM UTC 25
Finished Feb 09 01:42:46 PM UTC 25
Peak memory 226012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564821140 -assert nopostproc +UVM_TESTNAME=edn_disable_test +
UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.edn_disable.1564821140
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/28.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/28.edn_disable_auto_req_mode.3419039574
Short name T218
Test name
Test status
Simulation time 143015700 ps
CPU time 1.28 seconds
Started Feb 09 01:42:44 PM UTC 25
Finished Feb 09 01:42:46 PM UTC 25
Peak memory 228132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419039574 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_r
eq_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable_auto_req_mode.3419039574
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/28.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/28.edn_err.1627880167
Short name T171
Test name
Test status
Simulation time 72625285 ps
CPU time 1.24 seconds
Started Feb 09 01:42:40 PM UTC 25
Finished Feb 09 01:42:43 PM UTC 25
Peak memory 230304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627880167 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 28.edn_err.1627880167
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/28.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/28.edn_genbits.2624975217
Short name T445
Test name
Test status
Simulation time 52759220 ps
CPU time 2 seconds
Started Feb 09 01:42:31 PM UTC 25
Finished Feb 09 01:42:34 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624975217 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.edn_genbits.2624975217
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/28.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/28.edn_intr.4219520516
Short name T446
Test name
Test status
Simulation time 21951029 ps
CPU time 1.64 seconds
Started Feb 09 01:42:35 PM UTC 25
Finished Feb 09 01:42:38 PM UTC 25
Peak memory 226208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219520516 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 28.edn_intr.4219520516
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/28.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/28.edn_smoke.4014196231
Short name T443
Test name
Test status
Simulation time 26745897 ps
CPU time 1.32 seconds
Started Feb 09 01:42:28 PM UTC 25
Finished Feb 09 01:42:30 PM UTC 25
Peak memory 226148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014196231 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 28.edn_smoke.4014196231
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/28.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/28.edn_stress_all.2537844412
Short name T447
Test name
Test status
Simulation time 257128090 ps
CPU time 7.53 seconds
Started Feb 09 01:42:31 PM UTC 25
Finished Feb 09 01:42:39 PM UTC 25
Peak memory 229348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537844412 -assert nopostproc +UVM_TESTNAME=edn_stress_all
_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.2537844412
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/28.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/28.edn_stress_all_with_rand_reset.1380484142
Short name T846
Test name
Test status
Simulation time 29845872144 ps
CPU time 750.97 seconds
Started Feb 09 01:42:32 PM UTC 25
Finished Feb 09 01:55:11 PM UTC 25
Peak memory 229476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1380484142 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.1380484142
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/28.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/280.edn_genbits.3863538505
Short name T954
Test name
Test status
Simulation time 84882760 ps
CPU time 1.67 seconds
Started Feb 09 01:55:48 PM UTC 25
Finished Feb 09 01:55:51 PM UTC 25
Peak memory 226216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863538505 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 280.edn_genbits.3863538505
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/280.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/281.edn_genbits.818203371
Short name T955
Test name
Test status
Simulation time 83898763 ps
CPU time 1.98 seconds
Started Feb 09 01:55:48 PM UTC 25
Finished Feb 09 01:55:51 PM UTC 25
Peak memory 230304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818203371 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 281.edn_genbits.818203371
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/281.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/282.edn_genbits.4236235367
Short name T339
Test name
Test status
Simulation time 63946874 ps
CPU time 3.25 seconds
Started Feb 09 01:55:49 PM UTC 25
Finished Feb 09 01:55:53 PM UTC 25
Peak memory 231648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236235367 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 282.edn_genbits.4236235367
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/282.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/283.edn_genbits.4191803074
Short name T958
Test name
Test status
Simulation time 122887273 ps
CPU time 2.01 seconds
Started Feb 09 01:55:50 PM UTC 25
Finished Feb 09 01:55:53 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191803074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 283.edn_genbits.4191803074
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/283.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/284.edn_genbits.2820711650
Short name T957
Test name
Test status
Simulation time 56209291 ps
CPU time 1.8 seconds
Started Feb 09 01:55:50 PM UTC 25
Finished Feb 09 01:55:53 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820711650 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 284.edn_genbits.2820711650
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/284.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/285.edn_genbits.227347149
Short name T956
Test name
Test status
Simulation time 34644667 ps
CPU time 1.61 seconds
Started Feb 09 01:55:50 PM UTC 25
Finished Feb 09 01:55:53 PM UTC 25
Peak memory 228256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227347149 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 285.edn_genbits.227347149
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/285.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/286.edn_genbits.4134131291
Short name T961
Test name
Test status
Simulation time 111682428 ps
CPU time 1.89 seconds
Started Feb 09 01:55:51 PM UTC 25
Finished Feb 09 01:55:54 PM UTC 25
Peak memory 226216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134131291 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 286.edn_genbits.4134131291
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/286.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/287.edn_genbits.986600392
Short name T959
Test name
Test status
Simulation time 56541488 ps
CPU time 1.7 seconds
Started Feb 09 01:55:51 PM UTC 25
Finished Feb 09 01:55:54 PM UTC 25
Peak memory 228256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986600392 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 287.edn_genbits.986600392
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/287.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/288.edn_genbits.2922146845
Short name T967
Test name
Test status
Simulation time 188364188 ps
CPU time 5.18 seconds
Started Feb 09 01:55:51 PM UTC 25
Finished Feb 09 01:55:58 PM UTC 25
Peak memory 231796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922146845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 288.edn_genbits.2922146845
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/288.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/289.edn_genbits.1120107676
Short name T960
Test name
Test status
Simulation time 73521951 ps
CPU time 1.76 seconds
Started Feb 09 01:55:51 PM UTC 25
Finished Feb 09 01:55:54 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120107676 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 289.edn_genbits.1120107676
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/289.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/29.edn_alert.4285696689
Short name T160
Test name
Test status
Simulation time 46434485 ps
CPU time 1.72 seconds
Started Feb 09 01:43:01 PM UTC 25
Finished Feb 09 01:43:04 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285696689 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 29.edn_alert.4285696689
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/29.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/29.edn_alert_test.1355336297
Short name T455
Test name
Test status
Simulation time 18716767 ps
CPU time 1.26 seconds
Started Feb 09 01:43:08 PM UTC 25
Finished Feb 09 01:43:10 PM UTC 25
Peak memory 226700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355336297 -assert nopostproc +UVM_TESTNAME=edn_base_test +UV
M_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.1355336297
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/29.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/29.edn_disable.460100680
Short name T454
Test name
Test status
Simulation time 19774395 ps
CPU time 1.31 seconds
Started Feb 09 01:43:05 PM UTC 25
Finished Feb 09 01:43:08 PM UTC 25
Peak memory 226012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460100680 -assert nopostproc +UVM_TESTNAME=edn_disable_test +U
VM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.edn_disable.460100680
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/29.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/29.edn_disable_auto_req_mode.1347206288
Short name T168
Test name
Test status
Simulation time 35146253 ps
CPU time 1.54 seconds
Started Feb 09 01:43:07 PM UTC 25
Finished Feb 09 01:43:09 PM UTC 25
Peak memory 230180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347206288 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_r
eq_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable_auto_req_mode.1347206288
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/29.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/29.edn_err.1855914724
Short name T453
Test name
Test status
Simulation time 65521315 ps
CPU time 1.49 seconds
Started Feb 09 01:43:03 PM UTC 25
Finished Feb 09 01:43:06 PM UTC 25
Peak memory 230292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855914724 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 29.edn_err.1855914724
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/29.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/29.edn_genbits.3393453240
Short name T450
Test name
Test status
Simulation time 35871306 ps
CPU time 2.15 seconds
Started Feb 09 01:42:50 PM UTC 25
Finished Feb 09 01:42:53 PM UTC 25
Peak memory 229340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393453240 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.edn_genbits.3393453240
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/29.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/29.edn_intr.1916744945
Short name T452
Test name
Test status
Simulation time 39110311 ps
CPU time 1.39 seconds
Started Feb 09 01:42:58 PM UTC 25
Finished Feb 09 01:43:01 PM UTC 25
Peak memory 226208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916744945 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 29.edn_intr.1916744945
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/29.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/29.edn_smoke.1206589276
Short name T449
Test name
Test status
Simulation time 18946958 ps
CPU time 1.52 seconds
Started Feb 09 01:42:47 PM UTC 25
Finished Feb 09 01:42:50 PM UTC 25
Peak memory 226148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206589276 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 29.edn_smoke.1206589276
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/29.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/29.edn_stress_all.1226531487
Short name T451
Test name
Test status
Simulation time 360763785 ps
CPU time 5.59 seconds
Started Feb 09 01:42:51 PM UTC 25
Finished Feb 09 01:42:58 PM UTC 25
Peak memory 229280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226531487 -assert nopostproc +UVM_TESTNAME=edn_stress_all
_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.1226531487
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/29.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/29.edn_stress_all_with_rand_reset.3544607097
Short name T250
Test name
Test status
Simulation time 406136662505 ps
CPU time 1781.58 seconds
Started Feb 09 01:42:54 PM UTC 25
Finished Feb 09 02:12:56 PM UTC 25
Peak memory 234196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3544607097 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.3544607097
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/29.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/290.edn_genbits.2772435746
Short name T964
Test name
Test status
Simulation time 97242958 ps
CPU time 2.5 seconds
Started Feb 09 01:55:52 PM UTC 25
Finished Feb 09 01:55:56 PM UTC 25
Peak memory 231316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772435746 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 290.edn_genbits.2772435746
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/290.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/291.edn_genbits.1004104225
Short name T962
Test name
Test status
Simulation time 32553878 ps
CPU time 1.76 seconds
Started Feb 09 01:55:52 PM UTC 25
Finished Feb 09 01:55:55 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004104225 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 291.edn_genbits.1004104225
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/291.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/292.edn_genbits.312308295
Short name T963
Test name
Test status
Simulation time 88913129 ps
CPU time 1.69 seconds
Started Feb 09 01:55:52 PM UTC 25
Finished Feb 09 01:55:55 PM UTC 25
Peak memory 228256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312308295 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 292.edn_genbits.312308295
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/292.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/293.edn_genbits.3479849695
Short name T966
Test name
Test status
Simulation time 52301278 ps
CPU time 2.36 seconds
Started Feb 09 01:55:53 PM UTC 25
Finished Feb 09 01:55:57 PM UTC 25
Peak memory 229540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479849695 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 293.edn_genbits.3479849695
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/293.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/294.edn_genbits.3333838057
Short name T972
Test name
Test status
Simulation time 272523536 ps
CPU time 3.41 seconds
Started Feb 09 01:55:54 PM UTC 25
Finished Feb 09 01:55:59 PM UTC 25
Peak memory 231336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333838057 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 294.edn_genbits.3333838057
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/294.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/295.edn_genbits.3252403026
Short name T970
Test name
Test status
Simulation time 48472749 ps
CPU time 2.29 seconds
Started Feb 09 01:55:55 PM UTC 25
Finished Feb 09 01:55:58 PM UTC 25
Peak memory 229336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252403026 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 295.edn_genbits.3252403026
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/295.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/296.edn_genbits.1157612923
Short name T968
Test name
Test status
Simulation time 26239305 ps
CPU time 1.72 seconds
Started Feb 09 01:55:55 PM UTC 25
Finished Feb 09 01:55:58 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157612923 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 296.edn_genbits.1157612923
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/296.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/297.edn_genbits.3099135630
Short name T969
Test name
Test status
Simulation time 53220210 ps
CPU time 2 seconds
Started Feb 09 01:55:55 PM UTC 25
Finished Feb 09 01:55:58 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099135630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 297.edn_genbits.3099135630
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/297.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/298.edn_genbits.174041293
Short name T971
Test name
Test status
Simulation time 55519446 ps
CPU time 1.73 seconds
Started Feb 09 01:55:56 PM UTC 25
Finished Feb 09 01:55:59 PM UTC 25
Peak memory 230296 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174041293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 298.edn_genbits.174041293
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/298.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/299.edn_genbits.1173781544
Short name T973
Test name
Test status
Simulation time 1091404632 ps
CPU time 7.73 seconds
Started Feb 09 01:55:56 PM UTC 25
Finished Feb 09 01:56:05 PM UTC 25
Peak memory 231408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173781544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 299.edn_genbits.1173781544
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/299.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/3.edn_alert.2906772434
Short name T55
Test name
Test status
Simulation time 40464558 ps
CPU time 1.66 seconds
Started Feb 09 01:28:50 PM UTC 25
Finished Feb 09 01:28:52 PM UTC 25
Peak memory 228320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906772434 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 3.edn_alert.2906772434
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/3.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/3.edn_alert_test.462829810
Short name T362
Test name
Test status
Simulation time 28958998 ps
CPU time 1.19 seconds
Started Feb 09 01:28:59 PM UTC 25
Finished Feb 09 01:29:01 PM UTC 25
Peak memory 216004 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462829810 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM
_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.462829810
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/3.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/3.edn_disable.2967102006
Short name T48
Test name
Test status
Simulation time 39193906 ps
CPU time 1.33 seconds
Started Feb 09 01:28:54 PM UTC 25
Finished Feb 09 01:28:56 PM UTC 25
Peak memory 226012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967102006 -assert nopostproc +UVM_TESTNAME=edn_disable_test +
UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.edn_disable.2967102006
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/3.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/3.edn_disable_auto_req_mode.4004111864
Short name T77
Test name
Test status
Simulation time 118312548 ps
CPU time 1.97 seconds
Started Feb 09 01:28:55 PM UTC 25
Finished Feb 09 01:28:58 PM UTC 25
Peak memory 228124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004111864 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_r
eq_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable_auto_req_mode.4004111864
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/3.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/3.edn_err.124860078
Short name T209
Test name
Test status
Simulation time 18013747 ps
CPU time 1.52 seconds
Started Feb 09 01:28:51 PM UTC 25
Finished Feb 09 01:28:53 PM UTC 25
Peak memory 228260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124860078 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na
me 3.edn_err.124860078
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/3.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/3.edn_genbits.32712932
Short name T89
Test name
Test status
Simulation time 41185925 ps
CPU time 2.25 seconds
Started Feb 09 01:28:42 PM UTC 25
Finished Feb 09 01:28:46 PM UTC 25
Peak memory 229788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32712932 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 3.edn_genbits.32712932
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/3.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/3.edn_intr.3195184065
Short name T70
Test name
Test status
Simulation time 26718438 ps
CPU time 1.39 seconds
Started Feb 09 01:28:46 PM UTC 25
Finished Feb 09 01:28:49 PM UTC 25
Peak memory 226212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195184065 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 3.edn_intr.3195184065
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/3.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/3.edn_regwen.3489628460
Short name T88
Test name
Test status
Simulation time 53965428 ps
CPU time 1.42 seconds
Started Feb 09 01:28:41 PM UTC 25
Finished Feb 09 01:28:44 PM UTC 25
Peak memory 215908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489628460 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 3.edn_regwen.3489628460
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/3.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/3.edn_sec_cm.2724273532
Short name T58
Test name
Test status
Simulation time 894971630 ps
CPU time 6.57 seconds
Started Feb 09 01:28:57 PM UTC 25
Finished Feb 09 01:29:04 PM UTC 25
Peak memory 260308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724273532 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM
_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.2724273532
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/3.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/3.edn_smoke.1195164332
Short name T87
Test name
Test status
Simulation time 14767989 ps
CPU time 1.46 seconds
Started Feb 09 01:28:39 PM UTC 25
Finished Feb 09 01:28:42 PM UTC 25
Peak memory 226152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195164332 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 3.edn_smoke.1195164332
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/3.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/3.edn_stress_all.2102295208
Short name T90
Test name
Test status
Simulation time 412303760 ps
CPU time 4.01 seconds
Started Feb 09 01:28:44 PM UTC 25
Finished Feb 09 01:28:50 PM UTC 25
Peak memory 229676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102295208 -assert nopostproc +UVM_TESTNAME=edn_stress_all
_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.2102295208
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/3.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/3.edn_stress_all_with_rand_reset.3268841951
Short name T236
Test name
Test status
Simulation time 117629862315 ps
CPU time 851.22 seconds
Started Feb 09 01:28:44 PM UTC 25
Finished Feb 09 01:43:06 PM UTC 25
Peak memory 232056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3268841951 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.3268841951
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/3.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/30.edn_alert.723028830
Short name T457
Test name
Test status
Simulation time 75114232 ps
CPU time 1.76 seconds
Started Feb 09 01:43:17 PM UTC 25
Finished Feb 09 01:43:20 PM UTC 25
Peak memory 228320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723028830 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 30.edn_alert.723028830
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/30.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/30.edn_alert_test.3622905538
Short name T460
Test name
Test status
Simulation time 45749613 ps
CPU time 1.41 seconds
Started Feb 09 01:43:24 PM UTC 25
Finished Feb 09 01:43:27 PM UTC 25
Peak memory 217080 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622905538 -assert nopostproc +UVM_TESTNAME=edn_base_test +UV
M_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.3622905538
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/30.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/30.edn_disable.947030181
Short name T458
Test name
Test status
Simulation time 37562613 ps
CPU time 1.26 seconds
Started Feb 09 01:43:21 PM UTC 25
Finished Feb 09 01:43:23 PM UTC 25
Peak memory 226268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947030181 -assert nopostproc +UVM_TESTNAME=edn_disable_test +U
VM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.edn_disable.947030181
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/30.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/30.edn_disable_auto_req_mode.3423890375
Short name T459
Test name
Test status
Simulation time 105136988 ps
CPU time 1.69 seconds
Started Feb 09 01:43:23 PM UTC 25
Finished Feb 09 01:43:26 PM UTC 25
Peak memory 230168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423890375 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_r
eq_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable_auto_req_mode.3423890375
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/30.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/30.edn_err.3019762231
Short name T134
Test name
Test status
Simulation time 31016066 ps
CPU time 1.89 seconds
Started Feb 09 01:43:19 PM UTC 25
Finished Feb 09 01:43:22 PM UTC 25
Peak memory 232352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019762231 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 30.edn_err.3019762231
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/30.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/30.edn_genbits.2872724737
Short name T360
Test name
Test status
Simulation time 71362210 ps
CPU time 3.89 seconds
Started Feb 09 01:43:10 PM UTC 25
Finished Feb 09 01:43:15 PM UTC 25
Peak memory 231408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872724737 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.edn_genbits.2872724737
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/30.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/30.edn_intr.2950666817
Short name T106
Test name
Test status
Simulation time 19878803 ps
CPU time 1.61 seconds
Started Feb 09 01:43:16 PM UTC 25
Finished Feb 09 01:43:19 PM UTC 25
Peak memory 228436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950666817 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 30.edn_intr.2950666817
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/30.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/30.edn_smoke.257009164
Short name T456
Test name
Test status
Simulation time 20410768 ps
CPU time 1.47 seconds
Started Feb 09 01:43:09 PM UTC 25
Finished Feb 09 01:43:11 PM UTC 25
Peak memory 226140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257009164 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 30.edn_smoke.257009164
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/30.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/30.edn_stress_all.3502477418
Short name T253
Test name
Test status
Simulation time 146313929 ps
CPU time 4.48 seconds
Started Feb 09 01:43:11 PM UTC 25
Finished Feb 09 01:43:16 PM UTC 25
Peak memory 229332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502477418 -assert nopostproc +UVM_TESTNAME=edn_stress_all
_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.3502477418
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/30.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/30.edn_stress_all_with_rand_reset.239771953
Short name T535
Test name
Test status
Simulation time 78726595537 ps
CPU time 405.38 seconds
Started Feb 09 01:43:12 PM UTC 25
Finished Feb 09 01:50:03 PM UTC 25
Peak memory 234536 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=239771953 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.239771953
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/30.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/31.edn_alert_test.929564640
Short name T466
Test name
Test status
Simulation time 22899646 ps
CPU time 1.25 seconds
Started Feb 09 01:43:50 PM UTC 25
Finished Feb 09 01:43:52 PM UTC 25
Peak memory 226700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929564640 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM
_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.929564640
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/31.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/31.edn_disable.1299446319
Short name T464
Test name
Test status
Simulation time 11605435 ps
CPU time 1.06 seconds
Started Feb 09 01:43:44 PM UTC 25
Finished Feb 09 01:43:46 PM UTC 25
Peak memory 226272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299446319 -assert nopostproc +UVM_TESTNAME=edn_disable_test +
UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.edn_disable.1299446319
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/31.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/31.edn_disable_auto_req_mode.1353358848
Short name T465
Test name
Test status
Simulation time 88763139 ps
CPU time 1.61 seconds
Started Feb 09 01:43:47 PM UTC 25
Finished Feb 09 01:43:49 PM UTC 25
Peak memory 230176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353358848 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_r
eq_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable_auto_req_mode.1353358848
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/31.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/31.edn_err.3647743051
Short name T135
Test name
Test status
Simulation time 27002831 ps
CPU time 1.43 seconds
Started Feb 09 01:43:40 PM UTC 25
Finished Feb 09 01:43:43 PM UTC 25
Peak memory 230304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647743051 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 31.edn_err.3647743051
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/31.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/31.edn_genbits.1080423978
Short name T335
Test name
Test status
Simulation time 54407900 ps
CPU time 1.64 seconds
Started Feb 09 01:43:27 PM UTC 25
Finished Feb 09 01:43:30 PM UTC 25
Peak memory 230312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080423978 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.edn_genbits.1080423978
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/31.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/31.edn_intr.11629089
Short name T463
Test name
Test status
Simulation time 22116918 ps
CPU time 1.62 seconds
Started Feb 09 01:43:33 PM UTC 25
Finished Feb 09 01:43:36 PM UTC 25
Peak memory 228320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11629089 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 31.edn_intr.11629089
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/31.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/31.edn_smoke.4077212971
Short name T461
Test name
Test status
Simulation time 15295795 ps
CPU time 1.44 seconds
Started Feb 09 01:43:26 PM UTC 25
Finished Feb 09 01:43:29 PM UTC 25
Peak memory 226152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077212971 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 31.edn_smoke.4077212971
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/31.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/31.edn_stress_all.1127820507
Short name T462
Test name
Test status
Simulation time 181470796 ps
CPU time 2.09 seconds
Started Feb 09 01:43:29 PM UTC 25
Finished Feb 09 01:43:33 PM UTC 25
Peak memory 231476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127820507 -assert nopostproc +UVM_TESTNAME=edn_stress_all
_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.1127820507
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/31.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/31.edn_stress_all_with_rand_reset.2775925321
Short name T976
Test name
Test status
Simulation time 209719076452 ps
CPU time 860.23 seconds
Started Feb 09 01:43:30 PM UTC 25
Finished Feb 09 01:58:01 PM UTC 25
Peak memory 234344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2775925321 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.2775925321
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/31.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/32.edn_alert.1732036021
Short name T319
Test name
Test status
Simulation time 24909580 ps
CPU time 1.8 seconds
Started Feb 09 01:44:11 PM UTC 25
Finished Feb 09 01:44:14 PM UTC 25
Peak memory 228320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732036021 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 32.edn_alert.1732036021
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/32.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/32.edn_alert_test.3605587510
Short name T471
Test name
Test status
Simulation time 37096121 ps
CPU time 1.26 seconds
Started Feb 09 01:44:25 PM UTC 25
Finished Feb 09 01:44:28 PM UTC 25
Peak memory 216516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605587510 -assert nopostproc +UVM_TESTNAME=edn_base_test +UV
M_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.3605587510
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/32.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/32.edn_disable.883663793
Short name T224
Test name
Test status
Simulation time 24585113 ps
CPU time 1.27 seconds
Started Feb 09 01:44:18 PM UTC 25
Finished Feb 09 01:44:21 PM UTC 25
Peak memory 226012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883663793 -assert nopostproc +UVM_TESTNAME=edn_disable_test +U
VM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.edn_disable.883663793
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/32.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/32.edn_disable_auto_req_mode.3173176043
Short name T225
Test name
Test status
Simulation time 64992599 ps
CPU time 1.89 seconds
Started Feb 09 01:44:21 PM UTC 25
Finished Feb 09 01:44:24 PM UTC 25
Peak memory 228128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173176043 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_r
eq_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable_auto_req_mode.3173176043
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/32.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/32.edn_err.3523592328
Short name T470
Test name
Test status
Simulation time 20561592 ps
CPU time 1.56 seconds
Started Feb 09 01:44:15 PM UTC 25
Finished Feb 09 01:44:18 PM UTC 25
Peak memory 228256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523592328 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 32.edn_err.3523592328
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/32.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/32.edn_genbits.4026321346
Short name T468
Test name
Test status
Simulation time 60521711 ps
CPU time 1.49 seconds
Started Feb 09 01:43:56 PM UTC 25
Finished Feb 09 01:43:58 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026321346 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.edn_genbits.4026321346
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/32.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/32.edn_intr.474268667
Short name T469
Test name
Test status
Simulation time 32035785 ps
CPU time 1.3 seconds
Started Feb 09 01:44:07 PM UTC 25
Finished Feb 09 01:44:10 PM UTC 25
Peak memory 226208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474268667 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 32.edn_intr.474268667
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/32.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/32.edn_smoke.1666623304
Short name T467
Test name
Test status
Simulation time 51281531 ps
CPU time 1.38 seconds
Started Feb 09 01:43:53 PM UTC 25
Finished Feb 09 01:43:55 PM UTC 25
Peak memory 226152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666623304 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 32.edn_smoke.1666623304
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/32.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/32.edn_stress_all.3164300088
Short name T254
Test name
Test status
Simulation time 657379618 ps
CPU time 5.81 seconds
Started Feb 09 01:43:59 PM UTC 25
Finished Feb 09 01:44:06 PM UTC 25
Peak memory 229436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164300088 -assert nopostproc +UVM_TESTNAME=edn_stress_all
_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.3164300088
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/32.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/32.edn_stress_all_with_rand_reset.2440610858
Short name T246
Test name
Test status
Simulation time 293781049431 ps
CPU time 700.56 seconds
Started Feb 09 01:44:06 PM UTC 25
Finished Feb 09 01:55:55 PM UTC 25
Peak memory 234344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2440610858 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.2440610858
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/32.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/33.edn_alert.1629739588
Short name T169
Test name
Test status
Simulation time 136095257 ps
CPU time 1.82 seconds
Started Feb 09 01:44:42 PM UTC 25
Finished Feb 09 01:44:45 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629739588 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 33.edn_alert.1629739588
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/33.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/33.edn_alert_test.1679924817
Short name T475
Test name
Test status
Simulation time 63932766 ps
CPU time 1.36 seconds
Started Feb 09 01:44:49 PM UTC 25
Finished Feb 09 01:44:52 PM UTC 25
Peak memory 226692 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679924817 -assert nopostproc +UVM_TESTNAME=edn_base_test +UV
M_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.1679924817
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/33.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/33.edn_disable.355074139
Short name T230
Test name
Test status
Simulation time 68590912 ps
CPU time 1.28 seconds
Started Feb 09 01:44:46 PM UTC 25
Finished Feb 09 01:44:49 PM UTC 25
Peak memory 226008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355074139 -assert nopostproc +UVM_TESTNAME=edn_disable_test +U
VM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.edn_disable.355074139
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/33.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/33.edn_disable_auto_req_mode.4067711296
Short name T139
Test name
Test status
Simulation time 22393579 ps
CPU time 1.55 seconds
Started Feb 09 01:44:48 PM UTC 25
Finished Feb 09 01:44:51 PM UTC 25
Peak memory 230176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067711296 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_r
eq_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable_auto_req_mode.4067711296
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/33.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/33.edn_err.1864751167
Short name T474
Test name
Test status
Simulation time 18403095 ps
CPU time 1.59 seconds
Started Feb 09 01:44:45 PM UTC 25
Finished Feb 09 01:44:48 PM UTC 25
Peak memory 228436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864751167 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 33.edn_err.1864751167
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/33.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/33.edn_genbits.1450932370
Short name T350
Test name
Test status
Simulation time 29991070 ps
CPU time 2.12 seconds
Started Feb 09 01:44:33 PM UTC 25
Finished Feb 09 01:44:37 PM UTC 25
Peak memory 229560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450932370 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.edn_genbits.1450932370
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/33.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/33.edn_intr.2391106936
Short name T473
Test name
Test status
Simulation time 32196186 ps
CPU time 1.31 seconds
Started Feb 09 01:44:39 PM UTC 25
Finished Feb 09 01:44:41 PM UTC 25
Peak memory 228256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391106936 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 33.edn_intr.2391106936
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/33.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/33.edn_smoke.482679948
Short name T472
Test name
Test status
Simulation time 36065269 ps
CPU time 1.41 seconds
Started Feb 09 01:44:29 PM UTC 25
Finished Feb 09 01:44:32 PM UTC 25
Peak memory 226140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482679948 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 33.edn_smoke.482679948
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/33.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/33.edn_stress_all.1153350999
Short name T255
Test name
Test status
Simulation time 171149430 ps
CPU time 5.26 seconds
Started Feb 09 01:44:38 PM UTC 25
Finished Feb 09 01:44:44 PM UTC 25
Peak memory 229256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153350999 -assert nopostproc +UVM_TESTNAME=edn_stress_all
_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.1153350999
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/33.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/33.edn_stress_all_with_rand_reset.4237505736
Short name T825
Test name
Test status
Simulation time 60107357839 ps
CPU time 615.45 seconds
Started Feb 09 01:44:38 PM UTC 25
Finished Feb 09 01:55:00 PM UTC 25
Peak memory 229540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4237505736 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.4237505736
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/33.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/34.edn_alert.2502529612
Short name T175
Test name
Test status
Simulation time 77656374 ps
CPU time 1.66 seconds
Started Feb 09 01:45:00 PM UTC 25
Finished Feb 09 01:45:02 PM UTC 25
Peak memory 232416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502529612 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 34.edn_alert.2502529612
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/34.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/34.edn_alert_test.3244548206
Short name T480
Test name
Test status
Simulation time 16327421 ps
CPU time 1.39 seconds
Started Feb 09 01:45:07 PM UTC 25
Finished Feb 09 01:45:09 PM UTC 25
Peak memory 215712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244548206 -assert nopostproc +UVM_TESTNAME=edn_base_test +UV
M_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.3244548206
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/34.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/34.edn_disable.3119855983
Short name T479
Test name
Test status
Simulation time 11035519 ps
CPU time 1.28 seconds
Started Feb 09 01:45:04 PM UTC 25
Finished Feb 09 01:45:06 PM UTC 25
Peak memory 226012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119855983 -assert nopostproc +UVM_TESTNAME=edn_disable_test +
UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.edn_disable.3119855983
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/34.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/34.edn_disable_auto_req_mode.1138274811
Short name T214
Test name
Test status
Simulation time 44626144 ps
CPU time 1.62 seconds
Started Feb 09 01:45:05 PM UTC 25
Finished Feb 09 01:45:08 PM UTC 25
Peak memory 230176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138274811 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_r
eq_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable_auto_req_mode.1138274811
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/34.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/34.edn_err.655226828
Short name T478
Test name
Test status
Simulation time 37735327 ps
CPU time 1.62 seconds
Started Feb 09 01:45:02 PM UTC 25
Finished Feb 09 01:45:04 PM UTC 25
Peak memory 228196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655226828 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na
me 34.edn_err.655226828
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/34.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/34.edn_genbits.816743974
Short name T477
Test name
Test status
Simulation time 26944833 ps
CPU time 1.94 seconds
Started Feb 09 01:44:52 PM UTC 25
Finished Feb 09 01:44:55 PM UTC 25
Peak memory 230312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816743974 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.edn_genbits.816743974
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/34.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/34.edn_smoke.1403347324
Short name T476
Test name
Test status
Simulation time 15993448 ps
CPU time 1.47 seconds
Started Feb 09 01:44:51 PM UTC 25
Finished Feb 09 01:44:54 PM UTC 25
Peak memory 226152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403347324 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 34.edn_smoke.1403347324
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/34.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/34.edn_stress_all.3937023357
Short name T346
Test name
Test status
Simulation time 922173278 ps
CPU time 5.41 seconds
Started Feb 09 01:44:54 PM UTC 25
Finished Feb 09 01:45:01 PM UTC 25
Peak memory 229332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937023357 -assert nopostproc +UVM_TESTNAME=edn_stress_all
_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.3937023357
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/34.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/34.edn_stress_all_with_rand_reset.2296688723
Short name T245
Test name
Test status
Simulation time 22347066949 ps
CPU time 475.41 seconds
Started Feb 09 01:44:56 PM UTC 25
Finished Feb 09 01:52:57 PM UTC 25
Peak memory 229536 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2296688723 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.2296688723
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/34.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/35.edn_alert.1864599519
Short name T179
Test name
Test status
Simulation time 39850756 ps
CPU time 1.69 seconds
Started Feb 09 01:45:24 PM UTC 25
Finished Feb 09 01:45:27 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864599519 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 35.edn_alert.1864599519
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/35.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/35.edn_alert_test.2290208242
Short name T485
Test name
Test status
Simulation time 12993426 ps
CPU time 1.32 seconds
Started Feb 09 01:45:33 PM UTC 25
Finished Feb 09 01:45:35 PM UTC 25
Peak memory 216600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290208242 -assert nopostproc +UVM_TESTNAME=edn_base_test +UV
M_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.2290208242
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/35.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/35.edn_disable_auto_req_mode.4191890951
Short name T484
Test name
Test status
Simulation time 27839008 ps
CPU time 1.58 seconds
Started Feb 09 01:45:32 PM UTC 25
Finished Feb 09 01:45:35 PM UTC 25
Peak memory 230172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191890951 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_r
eq_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable_auto_req_mode.4191890951
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/35.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/35.edn_err.1390447686
Short name T483
Test name
Test status
Simulation time 19257960 ps
CPU time 1.75 seconds
Started Feb 09 01:45:29 PM UTC 25
Finished Feb 09 01:45:32 PM UTC 25
Peak memory 237060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390447686 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 35.edn_err.1390447686
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/35.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/35.edn_genbits.2928253851
Short name T334
Test name
Test status
Simulation time 89984129 ps
CPU time 2.07 seconds
Started Feb 09 01:45:10 PM UTC 25
Finished Feb 09 01:45:13 PM UTC 25
Peak memory 231716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928253851 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.edn_genbits.2928253851
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/35.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/35.edn_intr.3992686650
Short name T482
Test name
Test status
Simulation time 28065350 ps
CPU time 1.3 seconds
Started Feb 09 01:45:21 PM UTC 25
Finished Feb 09 01:45:24 PM UTC 25
Peak memory 228252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992686650 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 35.edn_intr.3992686650
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/35.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/35.edn_smoke.605966732
Short name T481
Test name
Test status
Simulation time 14459635 ps
CPU time 1.45 seconds
Started Feb 09 01:45:08 PM UTC 25
Finished Feb 09 01:45:10 PM UTC 25
Peak memory 226140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605966732 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 35.edn_smoke.605966732
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/35.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/35.edn_stress_all_with_rand_reset.629097200
Short name T965
Test name
Test status
Simulation time 27443385738 ps
CPU time 634.48 seconds
Started Feb 09 01:45:14 PM UTC 25
Finished Feb 09 01:55:56 PM UTC 25
Peak memory 229952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=629097200 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.629097200
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/35.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/36.edn_alert.3739755784
Short name T489
Test name
Test status
Simulation time 27676569 ps
CPU time 1.86 seconds
Started Feb 09 01:45:48 PM UTC 25
Finished Feb 09 01:45:51 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739755784 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 36.edn_alert.3739755784
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/36.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/36.edn_alert_test.1543872830
Short name T491
Test name
Test status
Simulation time 21026691 ps
CPU time 1.16 seconds
Started Feb 09 01:45:56 PM UTC 25
Finished Feb 09 01:45:59 PM UTC 25
Peak memory 216096 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543872830 -assert nopostproc +UVM_TESTNAME=edn_base_test +UV
M_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.1543872830
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/36.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/36.edn_disable_auto_req_mode.3931800095
Short name T490
Test name
Test status
Simulation time 136903245 ps
CPU time 1.52 seconds
Started Feb 09 01:45:55 PM UTC 25
Finished Feb 09 01:45:58 PM UTC 25
Peak memory 230168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931800095 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_r
eq_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable_auto_req_mode.3931800095
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/36.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/36.edn_err.1195012663
Short name T145
Test name
Test status
Simulation time 28571876 ps
CPU time 1.48 seconds
Started Feb 09 01:45:52 PM UTC 25
Finished Feb 09 01:45:55 PM UTC 25
Peak memory 230284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195012663 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 36.edn_err.1195012663
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/36.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/36.edn_genbits.1758421147
Short name T487
Test name
Test status
Simulation time 35911019 ps
CPU time 1.83 seconds
Started Feb 09 01:45:36 PM UTC 25
Finished Feb 09 01:45:39 PM UTC 25
Peak memory 226420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758421147 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.edn_genbits.1758421147
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/36.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/36.edn_intr.183165577
Short name T130
Test name
Test status
Simulation time 25381812 ps
CPU time 1.44 seconds
Started Feb 09 01:45:45 PM UTC 25
Finished Feb 09 01:45:48 PM UTC 25
Peak memory 228256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183165577 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 36.edn_intr.183165577
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/36.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/36.edn_smoke.2748843838
Short name T486
Test name
Test status
Simulation time 69564535 ps
CPU time 1.38 seconds
Started Feb 09 01:45:35 PM UTC 25
Finished Feb 09 01:45:38 PM UTC 25
Peak memory 226152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748843838 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 36.edn_smoke.2748843838
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/36.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/36.edn_stress_all.1503270151
Short name T488
Test name
Test status
Simulation time 560399914 ps
CPU time 4.71 seconds
Started Feb 09 01:45:38 PM UTC 25
Finished Feb 09 01:45:44 PM UTC 25
Peak memory 227264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503270151 -assert nopostproc +UVM_TESTNAME=edn_stress_all
_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.1503270151
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/36.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/36.edn_stress_all_with_rand_reset.3109617196
Short name T974
Test name
Test status
Simulation time 94378533923 ps
CPU time 663.8 seconds
Started Feb 09 01:45:40 PM UTC 25
Finished Feb 09 01:56:52 PM UTC 25
Peak memory 231532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3109617196 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.3109617196
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/36.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/37.edn_alert.2963958364
Short name T141
Test name
Test status
Simulation time 26208887 ps
CPU time 1.82 seconds
Started Feb 09 01:46:08 PM UTC 25
Finished Feb 09 01:46:11 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963958364 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 37.edn_alert.2963958364
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/37.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/37.edn_alert_test.720722330
Short name T498
Test name
Test status
Simulation time 13873181 ps
CPU time 1.36 seconds
Started Feb 09 01:46:21 PM UTC 25
Finished Feb 09 01:46:23 PM UTC 25
Peak memory 226776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720722330 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM
_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.720722330
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/37.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/37.edn_disable.4205801932
Short name T496
Test name
Test status
Simulation time 24068755 ps
CPU time 1.27 seconds
Started Feb 09 01:46:15 PM UTC 25
Finished Feb 09 01:46:17 PM UTC 25
Peak memory 226012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205801932 -assert nopostproc +UVM_TESTNAME=edn_disable_test +
UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.edn_disable.4205801932
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/37.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/37.edn_disable_auto_req_mode.809705802
Short name T497
Test name
Test status
Simulation time 84907702 ps
CPU time 1.56 seconds
Started Feb 09 01:46:18 PM UTC 25
Finished Feb 09 01:46:20 PM UTC 25
Peak memory 230172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809705802 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_re
q_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable_auto_req_mode.809705802
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/37.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/37.edn_err.1616051079
Short name T221
Test name
Test status
Simulation time 75470316 ps
CPU time 1.65 seconds
Started Feb 09 01:46:12 PM UTC 25
Finished Feb 09 01:46:14 PM UTC 25
Peak memory 230304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616051079 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 37.edn_err.1616051079
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/37.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/37.edn_genbits.4134264073
Short name T493
Test name
Test status
Simulation time 39656242 ps
CPU time 2.34 seconds
Started Feb 09 01:46:00 PM UTC 25
Finished Feb 09 01:46:03 PM UTC 25
Peak memory 229284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134264073 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.edn_genbits.4134264073
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/37.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/37.edn_intr.2810678635
Short name T495
Test name
Test status
Simulation time 21592796 ps
CPU time 1.39 seconds
Started Feb 09 01:46:05 PM UTC 25
Finished Feb 09 01:46:07 PM UTC 25
Peak memory 228256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810678635 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 37.edn_intr.2810678635
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/37.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/37.edn_smoke.239749331
Short name T492
Test name
Test status
Simulation time 15305331 ps
CPU time 1.39 seconds
Started Feb 09 01:45:58 PM UTC 25
Finished Feb 09 01:46:01 PM UTC 25
Peak memory 226136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239749331 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 37.edn_smoke.239749331
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/37.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/37.edn_stress_all.1693965652
Short name T494
Test name
Test status
Simulation time 84747642 ps
CPU time 1.33 seconds
Started Feb 09 01:46:02 PM UTC 25
Finished Feb 09 01:46:04 PM UTC 25
Peak memory 228204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693965652 -assert nopostproc +UVM_TESTNAME=edn_stress_all
_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.1693965652
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/37.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/37.edn_stress_all_with_rand_reset.1851524827
Short name T605
Test name
Test status
Simulation time 16815953063 ps
CPU time 393.86 seconds
Started Feb 09 01:46:04 PM UTC 25
Finished Feb 09 01:52:42 PM UTC 25
Peak memory 234508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1851524827 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.1851524827
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/37.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/38.edn_alert.2241880764
Short name T180
Test name
Test status
Simulation time 195781662 ps
CPU time 1.79 seconds
Started Feb 09 01:47:05 PM UTC 25
Finished Feb 09 01:47:08 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241880764 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 38.edn_alert.2241880764
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/38.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/38.edn_alert_test.3558109815
Short name T506
Test name
Test status
Simulation time 23854432 ps
CPU time 1.34 seconds
Started Feb 09 01:47:21 PM UTC 25
Finished Feb 09 01:47:23 PM UTC 25
Peak memory 215712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558109815 -assert nopostproc +UVM_TESTNAME=edn_base_test +UV
M_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.3558109815
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/38.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/38.edn_disable.1848297049
Short name T504
Test name
Test status
Simulation time 39918187 ps
CPU time 1.2 seconds
Started Feb 09 01:47:13 PM UTC 25
Finished Feb 09 01:47:16 PM UTC 25
Peak memory 226012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848297049 -assert nopostproc +UVM_TESTNAME=edn_disable_test +
UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.edn_disable.1848297049
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/38.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/38.edn_disable_auto_req_mode.1446149400
Short name T505
Test name
Test status
Simulation time 44548073 ps
CPU time 1.7 seconds
Started Feb 09 01:47:16 PM UTC 25
Finished Feb 09 01:47:19 PM UTC 25
Peak memory 228132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446149400 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_r
eq_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable_auto_req_mode.1446149400
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/38.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/38.edn_err.1236083941
Short name T503
Test name
Test status
Simulation time 18994440 ps
CPU time 1.79 seconds
Started Feb 09 01:47:09 PM UTC 25
Finished Feb 09 01:47:12 PM UTC 25
Peak memory 237060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236083941 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 38.edn_err.1236083941
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/38.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/38.edn_genbits.1974803478
Short name T500
Test name
Test status
Simulation time 57081610 ps
CPU time 2.28 seconds
Started Feb 09 01:46:27 PM UTC 25
Finished Feb 09 01:46:30 PM UTC 25
Peak memory 229344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974803478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.edn_genbits.1974803478
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/38.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/38.edn_intr.2770785238
Short name T502
Test name
Test status
Simulation time 38280107 ps
CPU time 1.3 seconds
Started Feb 09 01:47:02 PM UTC 25
Finished Feb 09 01:47:05 PM UTC 25
Peak memory 228376 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770785238 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 38.edn_intr.2770785238
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/38.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/38.edn_smoke.3773675275
Short name T499
Test name
Test status
Simulation time 33168332 ps
CPU time 1.39 seconds
Started Feb 09 01:46:24 PM UTC 25
Finished Feb 09 01:46:27 PM UTC 25
Peak memory 215912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773675275 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 38.edn_smoke.3773675275
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/38.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/38.edn_stress_all.3243957932
Short name T501
Test name
Test status
Simulation time 153154511 ps
CPU time 4.24 seconds
Started Feb 09 01:46:31 PM UTC 25
Finished Feb 09 01:46:37 PM UTC 25
Peak memory 229672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243957932 -assert nopostproc +UVM_TESTNAME=edn_stress_all
_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.3243957932
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/38.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/38.edn_stress_all_with_rand_reset.1642490352
Short name T989
Test name
Test status
Simulation time 225058530914 ps
CPU time 1301.02 seconds
Started Feb 09 01:46:37 PM UTC 25
Finished Feb 09 02:08:33 PM UTC 25
Peak memory 234452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1642490352 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.1642490352
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/38.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/39.edn_alert.1451581478
Short name T142
Test name
Test status
Simulation time 44675657 ps
CPU time 1.78 seconds
Started Feb 09 01:48:02 PM UTC 25
Finished Feb 09 01:48:05 PM UTC 25
Peak memory 230308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451581478 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 39.edn_alert.1451581478
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/39.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/39.edn_alert_test.1215113007
Short name T513
Test name
Test status
Simulation time 45680284 ps
CPU time 1.24 seconds
Started Feb 09 01:48:17 PM UTC 25
Finished Feb 09 01:48:20 PM UTC 25
Peak memory 215704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215113007 -assert nopostproc +UVM_TESTNAME=edn_base_test +UV
M_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.1215113007
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/39.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/39.edn_disable.2323179283
Short name T511
Test name
Test status
Simulation time 34905974 ps
CPU time 1.33 seconds
Started Feb 09 01:48:10 PM UTC 25
Finished Feb 09 01:48:13 PM UTC 25
Peak memory 226012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323179283 -assert nopostproc +UVM_TESTNAME=edn_disable_test +
UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.edn_disable.2323179283
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/39.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/39.edn_disable_auto_req_mode.3021396476
Short name T512
Test name
Test status
Simulation time 45664869 ps
CPU time 2.09 seconds
Started Feb 09 01:48:13 PM UTC 25
Finished Feb 09 01:48:16 PM UTC 25
Peak memory 229736 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021396476 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_r
eq_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable_auto_req_mode.3021396476
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/39.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/39.edn_err.2236461633
Short name T165
Test name
Test status
Simulation time 39162984 ps
CPU time 1.93 seconds
Started Feb 09 01:48:06 PM UTC 25
Finished Feb 09 01:48:09 PM UTC 25
Peak memory 243876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236461633 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 39.edn_err.2236461633
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/39.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/39.edn_genbits.3644082954
Short name T347
Test name
Test status
Simulation time 44198343 ps
CPU time 1.67 seconds
Started Feb 09 01:47:27 PM UTC 25
Finished Feb 09 01:47:30 PM UTC 25
Peak memory 230312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644082954 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.edn_genbits.3644082954
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/39.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/39.edn_intr.2542203902
Short name T510
Test name
Test status
Simulation time 22455150 ps
CPU time 1.81 seconds
Started Feb 09 01:47:58 PM UTC 25
Finished Feb 09 01:48:01 PM UTC 25
Peak memory 237060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542203902 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 39.edn_intr.2542203902
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/39.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/39.edn_smoke.888887899
Short name T507
Test name
Test status
Simulation time 25469092 ps
CPU time 1.4 seconds
Started Feb 09 01:47:24 PM UTC 25
Finished Feb 09 01:47:26 PM UTC 25
Peak memory 226152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888887899 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 39.edn_smoke.888887899
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/39.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/39.edn_stress_all.948962692
Short name T508
Test name
Test status
Simulation time 310495632 ps
CPU time 3.04 seconds
Started Feb 09 01:47:31 PM UTC 25
Finished Feb 09 01:47:35 PM UTC 25
Peak memory 229544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948962692 -assert nopostproc +UVM_TESTNAME=edn_stress_all_
test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.948962692
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/39.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/39.edn_stress_all_with_rand_reset.3959285515
Short name T992
Test name
Test status
Simulation time 303101235606 ps
CPU time 1612.07 seconds
Started Feb 09 01:47:36 PM UTC 25
Finished Feb 09 02:14:45 PM UTC 25
Peak memory 244476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3959285515 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.3959285515
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/39.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/4.edn_alert.979728154
Short name T124
Test name
Test status
Simulation time 38451234 ps
CPU time 1.57 seconds
Started Feb 09 01:29:14 PM UTC 25
Finished Feb 09 01:29:17 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979728154 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 4.edn_alert.979728154
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/4.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/4.edn_alert_test.2854145021
Short name T361
Test name
Test status
Simulation time 24846966 ps
CPU time 1.28 seconds
Started Feb 09 01:29:30 PM UTC 25
Finished Feb 09 01:29:33 PM UTC 25
Peak memory 215704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854145021 -assert nopostproc +UVM_TESTNAME=edn_base_test +UV
M_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.2854145021
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/4.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/4.edn_disable.1905718338
Short name T52
Test name
Test status
Simulation time 18713707 ps
CPU time 1.33 seconds
Started Feb 09 01:29:21 PM UTC 25
Finished Feb 09 01:29:24 PM UTC 25
Peak memory 230116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905718338 -assert nopostproc +UVM_TESTNAME=edn_disable_test +
UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.edn_disable.1905718338
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/4.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/4.edn_err.3398833809
Short name T8
Test name
Test status
Simulation time 41257320 ps
CPU time 1.84 seconds
Started Feb 09 01:29:17 PM UTC 25
Finished Feb 09 01:29:20 PM UTC 25
Peak memory 246228 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398833809 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 4.edn_err.3398833809
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/4.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/4.edn_genbits.32151448
Short name T40
Test name
Test status
Simulation time 40297233 ps
CPU time 2.08 seconds
Started Feb 09 01:29:05 PM UTC 25
Finished Feb 09 01:29:08 PM UTC 25
Peak memory 229264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32151448 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 4.edn_genbits.32151448
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/4.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/4.edn_intr.803590988
Short name T364
Test name
Test status
Simulation time 28368915 ps
CPU time 1.47 seconds
Started Feb 09 01:29:11 PM UTC 25
Finished Feb 09 01:29:14 PM UTC 25
Peak memory 226388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803590988 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 4.edn_intr.803590988
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/4.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/4.edn_regwen.1620905523
Short name T115
Test name
Test status
Simulation time 194091750 ps
CPU time 1.44 seconds
Started Feb 09 01:29:05 PM UTC 25
Finished Feb 09 01:29:08 PM UTC 25
Peak memory 215908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620905523 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 4.edn_regwen.1620905523
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/4.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/4.edn_sec_cm.1290559303
Short name T23
Test name
Test status
Simulation time 1743015385 ps
CPU time 7.87 seconds
Started Feb 09 01:29:29 PM UTC 25
Finished Feb 09 01:29:38 PM UTC 25
Peak memory 262584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290559303 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM
_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.1290559303
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/4.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/4.edn_smoke.1109088713
Short name T363
Test name
Test status
Simulation time 17611294 ps
CPU time 1.51 seconds
Started Feb 09 01:29:02 PM UTC 25
Finished Feb 09 01:29:05 PM UTC 25
Peak memory 226152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109088713 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 4.edn_smoke.1109088713
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/4.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/4.edn_stress_all.1143007403
Short name T212
Test name
Test status
Simulation time 35000760 ps
CPU time 1.4 seconds
Started Feb 09 01:29:08 PM UTC 25
Finished Feb 09 01:29:11 PM UTC 25
Peak memory 216004 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143007403 -assert nopostproc +UVM_TESTNAME=edn_stress_all
_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.1143007403
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/4.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/4.edn_stress_all_with_rand_reset.267347061
Short name T354
Test name
Test status
Simulation time 53172196193 ps
CPU time 1284.54 seconds
Started Feb 09 01:29:09 PM UTC 25
Finished Feb 09 01:50:48 PM UTC 25
Peak memory 233576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=267347061 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.267347061
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/4.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/40.edn_alert.2450028976
Short name T327
Test name
Test status
Simulation time 88584494 ps
CPU time 1.66 seconds
Started Feb 09 01:49:05 PM UTC 25
Finished Feb 09 01:49:08 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450028976 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 40.edn_alert.2450028976
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/40.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/40.edn_alert_test.2775747900
Short name T519
Test name
Test status
Simulation time 20881374 ps
CPU time 1.26 seconds
Started Feb 09 01:49:18 PM UTC 25
Finished Feb 09 01:49:20 PM UTC 25
Peak memory 216456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775747900 -assert nopostproc +UVM_TESTNAME=edn_base_test +UV
M_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.2775747900
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/40.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/40.edn_disable.3289402619
Short name T517
Test name
Test status
Simulation time 37807020 ps
CPU time 1.3 seconds
Started Feb 09 01:49:11 PM UTC 25
Finished Feb 09 01:49:13 PM UTC 25
Peak memory 226272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289402619 -assert nopostproc +UVM_TESTNAME=edn_disable_test +
UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.edn_disable.3289402619
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/40.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/40.edn_disable_auto_req_mode.722063144
Short name T518
Test name
Test status
Simulation time 92720529 ps
CPU time 1.66 seconds
Started Feb 09 01:49:14 PM UTC 25
Finished Feb 09 01:49:17 PM UTC 25
Peak memory 230172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722063144 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_re
q_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable_auto_req_mode.722063144
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/40.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/40.edn_err.4270343276
Short name T136
Test name
Test status
Simulation time 48073100 ps
CPU time 1.37 seconds
Started Feb 09 01:49:08 PM UTC 25
Finished Feb 09 01:49:11 PM UTC 25
Peak memory 230304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270343276 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 40.edn_err.4270343276
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/40.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/40.edn_genbits.332683308
Short name T12
Test name
Test status
Simulation time 376047208 ps
CPU time 2.57 seconds
Started Feb 09 01:48:25 PM UTC 25
Finished Feb 09 01:48:29 PM UTC 25
Peak memory 229344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332683308 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.edn_genbits.332683308
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/40.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/40.edn_intr.2155926250
Short name T516
Test name
Test status
Simulation time 40296963 ps
CPU time 1.35 seconds
Started Feb 09 01:49:02 PM UTC 25
Finished Feb 09 01:49:04 PM UTC 25
Peak memory 226208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155926250 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 40.edn_intr.2155926250
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/40.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/40.edn_smoke.500559090
Short name T514
Test name
Test status
Simulation time 27479986 ps
CPU time 1.4 seconds
Started Feb 09 01:48:21 PM UTC 25
Finished Feb 09 01:48:24 PM UTC 25
Peak memory 226140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500559090 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 40.edn_smoke.500559090
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/40.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/40.edn_stress_all.3234234040
Short name T515
Test name
Test status
Simulation time 127693797 ps
CPU time 4.25 seconds
Started Feb 09 01:48:29 PM UTC 25
Finished Feb 09 01:48:35 PM UTC 25
Peak memory 229352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234234040 -assert nopostproc +UVM_TESTNAME=edn_stress_all
_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.3234234040
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/40.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/40.edn_stress_all_with_rand_reset.3967806369
Short name T986
Test name
Test status
Simulation time 157704858696 ps
CPU time 966.18 seconds
Started Feb 09 01:48:35 PM UTC 25
Finished Feb 09 02:04:53 PM UTC 25
Peak memory 234088 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3967806369 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.3967806369
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/40.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/41.edn_alert.917375863
Short name T524
Test name
Test status
Simulation time 77625535 ps
CPU time 1.96 seconds
Started Feb 09 01:49:33 PM UTC 25
Finished Feb 09 01:49:36 PM UTC 25
Peak memory 226252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917375863 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 41.edn_alert.917375863
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/41.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/41.edn_alert_test.3116177005
Short name T528
Test name
Test status
Simulation time 34460211 ps
CPU time 1.24 seconds
Started Feb 09 01:49:40 PM UTC 25
Finished Feb 09 01:49:42 PM UTC 25
Peak memory 216636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116177005 -assert nopostproc +UVM_TESTNAME=edn_base_test +UV
M_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.3116177005
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/41.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/41.edn_disable.2275165552
Short name T526
Test name
Test status
Simulation time 30659219 ps
CPU time 1.26 seconds
Started Feb 09 01:49:37 PM UTC 25
Finished Feb 09 01:49:39 PM UTC 25
Peak memory 226008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275165552 -assert nopostproc +UVM_TESTNAME=edn_disable_test +
UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.edn_disable.2275165552
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/41.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/41.edn_disable_auto_req_mode.4220427310
Short name T527
Test name
Test status
Simulation time 90345401 ps
CPU time 1.65 seconds
Started Feb 09 01:49:37 PM UTC 25
Finished Feb 09 01:49:40 PM UTC 25
Peak memory 228132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220427310 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_r
eq_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable_auto_req_mode.4220427310
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/41.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/41.edn_err.61303307
Short name T525
Test name
Test status
Simulation time 25657612 ps
CPU time 1.31 seconds
Started Feb 09 01:49:34 PM UTC 25
Finished Feb 09 01:49:36 PM UTC 25
Peak memory 228256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61303307 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 41.edn_err.61303307
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/41.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/41.edn_genbits.258961989
Short name T521
Test name
Test status
Simulation time 64129037 ps
CPU time 2.3 seconds
Started Feb 09 01:49:22 PM UTC 25
Finished Feb 09 01:49:25 PM UTC 25
Peak memory 229600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258961989 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.edn_genbits.258961989
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/41.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/41.edn_intr.2091403701
Short name T523
Test name
Test status
Simulation time 19827341 ps
CPU time 1.61 seconds
Started Feb 09 01:49:31 PM UTC 25
Finished Feb 09 01:49:33 PM UTC 25
Peak memory 228256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091403701 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 41.edn_intr.2091403701
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/41.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/41.edn_smoke.1882595286
Short name T520
Test name
Test status
Simulation time 15151967 ps
CPU time 1.47 seconds
Started Feb 09 01:49:21 PM UTC 25
Finished Feb 09 01:49:23 PM UTC 25
Peak memory 215972 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882595286 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 41.edn_smoke.1882595286
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/41.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/41.edn_stress_all.2406846721
Short name T522
Test name
Test status
Simulation time 302336648 ps
CPU time 5.19 seconds
Started Feb 09 01:49:24 PM UTC 25
Finished Feb 09 01:49:30 PM UTC 25
Peak memory 229288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406846721 -assert nopostproc +UVM_TESTNAME=edn_stress_all
_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.2406846721
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/41.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/41.edn_stress_all_with_rand_reset.3840928295
Short name T981
Test name
Test status
Simulation time 29578565057 ps
CPU time 721.02 seconds
Started Feb 09 01:49:26 PM UTC 25
Finished Feb 09 02:01:35 PM UTC 25
Peak memory 229468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3840928295 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.3840928295
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/41.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/42.edn_alert.3387986596
Short name T532
Test name
Test status
Simulation time 39453898 ps
CPU time 1.82 seconds
Started Feb 09 01:49:51 PM UTC 25
Finished Feb 09 01:49:54 PM UTC 25
Peak memory 228320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387986596 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 42.edn_alert.3387986596
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/42.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/42.edn_alert_test.624543989
Short name T537
Test name
Test status
Simulation time 38768581 ps
CPU time 1.28 seconds
Started Feb 09 01:50:04 PM UTC 25
Finished Feb 09 01:50:06 PM UTC 25
Peak memory 226700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624543989 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM
_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.624543989
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/42.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/42.edn_disable.2545403411
Short name T534
Test name
Test status
Simulation time 19173105 ps
CPU time 1.21 seconds
Started Feb 09 01:49:59 PM UTC 25
Finished Feb 09 01:50:02 PM UTC 25
Peak memory 226012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545403411 -assert nopostproc +UVM_TESTNAME=edn_disable_test +
UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.edn_disable.2545403411
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/42.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/42.edn_disable_auto_req_mode.1147554059
Short name T536
Test name
Test status
Simulation time 77835633 ps
CPU time 1.66 seconds
Started Feb 09 01:50:02 PM UTC 25
Finished Feb 09 01:50:05 PM UTC 25
Peak memory 228132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147554059 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_r
eq_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable_auto_req_mode.1147554059
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/42.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/42.edn_err.2124889334
Short name T533
Test name
Test status
Simulation time 22504358 ps
CPU time 1.64 seconds
Started Feb 09 01:49:55 PM UTC 25
Finished Feb 09 01:49:58 PM UTC 25
Peak memory 237060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124889334 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 42.edn_err.2124889334
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/42.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/42.edn_genbits.2845040974
Short name T13
Test name
Test status
Simulation time 89288886 ps
CPU time 1.81 seconds
Started Feb 09 01:49:43 PM UTC 25
Finished Feb 09 01:49:46 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845040974 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.edn_genbits.2845040974
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/42.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/42.edn_intr.2002587096
Short name T531
Test name
Test status
Simulation time 36513651 ps
CPU time 1.5 seconds
Started Feb 09 01:49:48 PM UTC 25
Finished Feb 09 01:49:51 PM UTC 25
Peak memory 236852 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002587096 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 42.edn_intr.2002587096
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/42.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/42.edn_smoke.516494973
Short name T529
Test name
Test status
Simulation time 22440179 ps
CPU time 1.34 seconds
Started Feb 09 01:49:40 PM UTC 25
Finished Feb 09 01:49:43 PM UTC 25
Peak memory 226136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516494973 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 42.edn_smoke.516494973
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/42.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/42.edn_stress_all.1965611754
Short name T530
Test name
Test status
Simulation time 499657650 ps
CPU time 2.52 seconds
Started Feb 09 01:49:43 PM UTC 25
Finished Feb 09 01:49:47 PM UTC 25
Peak memory 229300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965611754 -assert nopostproc +UVM_TESTNAME=edn_stress_all
_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.1965611754
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/42.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/42.edn_stress_all_with_rand_reset.1277274925
Short name T975
Test name
Test status
Simulation time 73264277596 ps
CPU time 423.54 seconds
Started Feb 09 01:49:47 PM UTC 25
Finished Feb 09 01:56:56 PM UTC 25
Peak memory 234256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1277274925 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.1277274925
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/42.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/43.edn_alert.2508322733
Short name T131
Test name
Test status
Simulation time 23664518 ps
CPU time 1.71 seconds
Started Feb 09 01:50:14 PM UTC 25
Finished Feb 09 01:50:17 PM UTC 25
Peak memory 230148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508322733 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 43.edn_alert.2508322733
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/43.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/43.edn_alert_test.3307016765
Short name T545
Test name
Test status
Simulation time 14588189 ps
CPU time 1.35 seconds
Started Feb 09 01:50:20 PM UTC 25
Finished Feb 09 01:50:23 PM UTC 25
Peak memory 215712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307016765 -assert nopostproc +UVM_TESTNAME=edn_base_test +UV
M_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.3307016765
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/43.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/43.edn_disable.3524020508
Short name T543
Test name
Test status
Simulation time 13152906 ps
CPU time 1.34 seconds
Started Feb 09 01:50:17 PM UTC 25
Finished Feb 09 01:50:20 PM UTC 25
Peak memory 226020 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524020508 -assert nopostproc +UVM_TESTNAME=edn_disable_test +
UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.edn_disable.3524020508
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/43.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/43.edn_disable_auto_req_mode.3922492343
Short name T544
Test name
Test status
Simulation time 107041718 ps
CPU time 1.65 seconds
Started Feb 09 01:50:18 PM UTC 25
Finished Feb 09 01:50:21 PM UTC 25
Peak memory 228128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922492343 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_r
eq_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable_auto_req_mode.3922492343
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/43.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/43.edn_err.4264019500
Short name T542
Test name
Test status
Simulation time 50513510 ps
CPU time 1.24 seconds
Started Feb 09 01:50:14 PM UTC 25
Finished Feb 09 01:50:17 PM UTC 25
Peak memory 228008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264019500 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 43.edn_err.4264019500
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/43.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/43.edn_genbits.2545167001
Short name T539
Test name
Test status
Simulation time 34849010 ps
CPU time 2.03 seconds
Started Feb 09 01:50:07 PM UTC 25
Finished Feb 09 01:50:10 PM UTC 25
Peak memory 231516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545167001 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.edn_genbits.2545167001
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/43.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/43.edn_intr.4207046387
Short name T541
Test name
Test status
Simulation time 25288857 ps
CPU time 1.44 seconds
Started Feb 09 01:50:11 PM UTC 25
Finished Feb 09 01:50:14 PM UTC 25
Peak memory 228256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207046387 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 43.edn_intr.4207046387
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/43.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/43.edn_smoke.1765613355
Short name T538
Test name
Test status
Simulation time 16142557 ps
CPU time 1.42 seconds
Started Feb 09 01:50:06 PM UTC 25
Finished Feb 09 01:50:08 PM UTC 25
Peak memory 226148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765613355 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 43.edn_smoke.1765613355
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/43.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/43.edn_stress_all.3967569508
Short name T540
Test name
Test status
Simulation time 1898333547 ps
CPU time 5.1 seconds
Started Feb 09 01:50:07 PM UTC 25
Finished Feb 09 01:50:13 PM UTC 25
Peak memory 229584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967569508 -assert nopostproc +UVM_TESTNAME=edn_stress_all
_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.3967569508
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/43.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/43.edn_stress_all_with_rand_reset.2784686445
Short name T979
Test name
Test status
Simulation time 98110593080 ps
CPU time 592.29 seconds
Started Feb 09 01:50:09 PM UTC 25
Finished Feb 09 02:00:09 PM UTC 25
Peak memory 234444 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2784686445 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.2784686445
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/43.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/44.edn_alert.2891156869
Short name T129
Test name
Test status
Simulation time 81308126 ps
CPU time 1.73 seconds
Started Feb 09 01:50:38 PM UTC 25
Finished Feb 09 01:50:40 PM UTC 25
Peak memory 228320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891156869 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 44.edn_alert.2891156869
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/44.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/44.edn_alert_test.2977921326
Short name T551
Test name
Test status
Simulation time 32954434 ps
CPU time 1.39 seconds
Started Feb 09 01:50:49 PM UTC 25
Finished Feb 09 01:50:51 PM UTC 25
Peak memory 226700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977921326 -assert nopostproc +UVM_TESTNAME=edn_base_test +UV
M_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.2977921326
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/44.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/44.edn_disable.349962894
Short name T549
Test name
Test status
Simulation time 51617251 ps
CPU time 1.22 seconds
Started Feb 09 01:50:44 PM UTC 25
Finished Feb 09 01:50:46 PM UTC 25
Peak memory 228068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349962894 -assert nopostproc +UVM_TESTNAME=edn_disable_test +U
VM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.edn_disable.349962894
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/44.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/44.edn_disable_auto_req_mode.1465838770
Short name T550
Test name
Test status
Simulation time 120224119 ps
CPU time 1.7 seconds
Started Feb 09 01:50:47 PM UTC 25
Finished Feb 09 01:50:50 PM UTC 25
Peak memory 228432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465838770 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_r
eq_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable_auto_req_mode.1465838770
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/44.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/44.edn_genbits.3724450716
Short name T547
Test name
Test status
Simulation time 110440494 ps
CPU time 1.49 seconds
Started Feb 09 01:50:23 PM UTC 25
Finished Feb 09 01:50:26 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724450716 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.edn_genbits.3724450716
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/44.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/44.edn_intr.3175825585
Short name T107
Test name
Test status
Simulation time 40001433 ps
CPU time 1.28 seconds
Started Feb 09 01:50:35 PM UTC 25
Finished Feb 09 01:50:37 PM UTC 25
Peak memory 228316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175825585 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 44.edn_intr.3175825585
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/44.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/44.edn_smoke.526320291
Short name T546
Test name
Test status
Simulation time 28596364 ps
CPU time 1.38 seconds
Started Feb 09 01:50:21 PM UTC 25
Finished Feb 09 01:50:24 PM UTC 25
Peak memory 226140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526320291 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 44.edn_smoke.526320291
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/44.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/44.edn_stress_all.1763046566
Short name T548
Test name
Test status
Simulation time 297407969 ps
CPU time 8.2 seconds
Started Feb 09 01:50:24 PM UTC 25
Finished Feb 09 01:50:34 PM UTC 25
Peak memory 229588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763046566 -assert nopostproc +UVM_TESTNAME=edn_stress_all
_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.1763046566
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/44.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/44.edn_stress_all_with_rand_reset.70241424
Short name T248
Test name
Test status
Simulation time 80636695787 ps
CPU time 412.27 seconds
Started Feb 09 01:50:27 PM UTC 25
Finished Feb 09 01:57:24 PM UTC 25
Peak memory 229804 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=70241424 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.70241424
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/44.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/45.edn_alert.1741459430
Short name T148
Test name
Test status
Simulation time 166218727 ps
CPU time 1.91 seconds
Started Feb 09 01:51:02 PM UTC 25
Finished Feb 09 01:51:05 PM UTC 25
Peak memory 228320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741459430 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 45.edn_alert.1741459430
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/45.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/45.edn_alert_test.2066871584
Short name T559
Test name
Test status
Simulation time 31378210 ps
CPU time 1.4 seconds
Started Feb 09 01:51:18 PM UTC 25
Finished Feb 09 01:51:21 PM UTC 25
Peak memory 216088 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066871584 -assert nopostproc +UVM_TESTNAME=edn_base_test +UV
M_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.2066871584
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/45.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/45.edn_disable.956858660
Short name T557
Test name
Test status
Simulation time 24887213 ps
CPU time 1.36 seconds
Started Feb 09 01:51:10 PM UTC 25
Finished Feb 09 01:51:13 PM UTC 25
Peak memory 226012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956858660 -assert nopostproc +UVM_TESTNAME=edn_disable_test +U
VM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.edn_disable.956858660
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/45.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/45.edn_disable_auto_req_mode.453667976
Short name T558
Test name
Test status
Simulation time 96644625 ps
CPU time 1.65 seconds
Started Feb 09 01:51:14 PM UTC 25
Finished Feb 09 01:51:17 PM UTC 25
Peak memory 228124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453667976 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_re
q_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable_auto_req_mode.453667976
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/45.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/45.edn_err.1192375650
Short name T556
Test name
Test status
Simulation time 38184617 ps
CPU time 1.63 seconds
Started Feb 09 01:51:06 PM UTC 25
Finished Feb 09 01:51:09 PM UTC 25
Peak memory 232232 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192375650 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 45.edn_err.1192375650
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/45.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/45.edn_genbits.416293289
Short name T553
Test name
Test status
Simulation time 33046448 ps
CPU time 2.15 seconds
Started Feb 09 01:50:52 PM UTC 25
Finished Feb 09 01:50:55 PM UTC 25
Peak memory 229356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416293289 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.edn_genbits.416293289
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/45.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/45.edn_intr.3508584052
Short name T555
Test name
Test status
Simulation time 35538023 ps
CPU time 1.56 seconds
Started Feb 09 01:50:59 PM UTC 25
Finished Feb 09 01:51:02 PM UTC 25
Peak memory 237240 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3508584052 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 45.edn_intr.3508584052
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/45.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/45.edn_smoke.2567224617
Short name T552
Test name
Test status
Simulation time 26160974 ps
CPU time 1.41 seconds
Started Feb 09 01:50:50 PM UTC 25
Finished Feb 09 01:50:52 PM UTC 25
Peak memory 226144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567224617 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 45.edn_smoke.2567224617
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/45.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/45.edn_stress_all.3781383483
Short name T554
Test name
Test status
Simulation time 240899241 ps
CPU time 4.29 seconds
Started Feb 09 01:50:53 PM UTC 25
Finished Feb 09 01:50:59 PM UTC 25
Peak memory 227296 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781383483 -assert nopostproc +UVM_TESTNAME=edn_stress_all
_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.3781383483
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/45.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/45.edn_stress_all_with_rand_reset.2964473739
Short name T249
Test name
Test status
Simulation time 66595707175 ps
CPU time 1043.59 seconds
Started Feb 09 01:50:56 PM UTC 25
Finished Feb 09 02:08:31 PM UTC 25
Peak memory 231852 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2964473739 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.2964473739
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/45.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/46.edn_alert.1733311882
Short name T201
Test name
Test status
Simulation time 37531967 ps
CPU time 1.59 seconds
Started Feb 09 01:51:30 PM UTC 25
Finished Feb 09 01:51:33 PM UTC 25
Peak memory 228320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733311882 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 46.edn_alert.1733311882
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/46.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/46.edn_alert_test.2721613266
Short name T566
Test name
Test status
Simulation time 46807098 ps
CPU time 1.55 seconds
Started Feb 09 01:51:38 PM UTC 25
Finished Feb 09 01:51:40 PM UTC 25
Peak memory 226700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721613266 -assert nopostproc +UVM_TESTNAME=edn_base_test +UV
M_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.2721613266
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/46.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/46.edn_disable.3921882329
Short name T564
Test name
Test status
Simulation time 14570783 ps
CPU time 1.33 seconds
Started Feb 09 01:51:35 PM UTC 25
Finished Feb 09 01:51:37 PM UTC 25
Peak memory 230116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921882329 -assert nopostproc +UVM_TESTNAME=edn_disable_test +
UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.edn_disable.3921882329
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/46.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/46.edn_disable_auto_req_mode.1380971362
Short name T565
Test name
Test status
Simulation time 68737543 ps
CPU time 2.5 seconds
Started Feb 09 01:51:37 PM UTC 25
Finished Feb 09 01:51:40 PM UTC 25
Peak memory 229588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380971362 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_r
eq_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable_auto_req_mode.1380971362
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/46.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/46.edn_err.1675382743
Short name T226
Test name
Test status
Simulation time 33089199 ps
CPU time 2.16 seconds
Started Feb 09 01:51:33 PM UTC 25
Finished Feb 09 01:51:36 PM UTC 25
Peak memory 243616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675382743 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 46.edn_err.1675382743
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/46.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/46.edn_genbits.3865750460
Short name T561
Test name
Test status
Simulation time 66854771 ps
CPU time 2.09 seconds
Started Feb 09 01:51:25 PM UTC 25
Finished Feb 09 01:51:28 PM UTC 25
Peak memory 229348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865750460 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.edn_genbits.3865750460
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/46.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/46.edn_intr.907657998
Short name T563
Test name
Test status
Simulation time 32743996 ps
CPU time 1.37 seconds
Started Feb 09 01:51:29 PM UTC 25
Finished Feb 09 01:51:32 PM UTC 25
Peak memory 226208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907657998 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 46.edn_intr.907657998
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/46.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/46.edn_smoke.1915856820
Short name T560
Test name
Test status
Simulation time 97735088 ps
CPU time 1.38 seconds
Started Feb 09 01:51:22 PM UTC 25
Finished Feb 09 01:51:24 PM UTC 25
Peak memory 226148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915856820 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 46.edn_smoke.1915856820
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/46.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/46.edn_stress_all.1669013010
Short name T562
Test name
Test status
Simulation time 1118631419 ps
CPU time 3.12 seconds
Started Feb 09 01:51:25 PM UTC 25
Finished Feb 09 01:51:29 PM UTC 25
Peak memory 227380 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669013010 -assert nopostproc +UVM_TESTNAME=edn_stress_all
_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.1669013010
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/46.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/46.edn_stress_all_with_rand_reset.2853738365
Short name T978
Test name
Test status
Simulation time 34628810234 ps
CPU time 496.37 seconds
Started Feb 09 01:51:27 PM UTC 25
Finished Feb 09 01:59:50 PM UTC 25
Peak memory 229864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2853738365 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.2853738365
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/46.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/47.edn_alert.3992798774
Short name T569
Test name
Test status
Simulation time 71258941 ps
CPU time 1.63 seconds
Started Feb 09 01:51:48 PM UTC 25
Finished Feb 09 01:51:51 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992798774 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 47.edn_alert.3992798774
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/47.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/47.edn_alert_test.4002020679
Short name T574
Test name
Test status
Simulation time 23769051 ps
CPU time 1.34 seconds
Started Feb 09 01:51:53 PM UTC 25
Finished Feb 09 01:51:55 PM UTC 25
Peak memory 226700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002020679 -assert nopostproc +UVM_TESTNAME=edn_base_test +UV
M_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.4002020679
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/47.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/47.edn_disable.2014813613
Short name T571
Test name
Test status
Simulation time 10370743 ps
CPU time 1.07 seconds
Started Feb 09 01:51:52 PM UTC 25
Finished Feb 09 01:51:54 PM UTC 25
Peak memory 230116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014813613 -assert nopostproc +UVM_TESTNAME=edn_disable_test +
UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.edn_disable.2014813613
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/47.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/47.edn_disable_auto_req_mode.2048998260
Short name T572
Test name
Test status
Simulation time 63999568 ps
CPU time 1.32 seconds
Started Feb 09 01:51:52 PM UTC 25
Finished Feb 09 01:51:54 PM UTC 25
Peak memory 228128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048998260 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_r
eq_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable_auto_req_mode.2048998260
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/47.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/47.edn_err.894614607
Short name T137
Test name
Test status
Simulation time 26325844 ps
CPU time 1.35 seconds
Started Feb 09 01:51:50 PM UTC 25
Finished Feb 09 01:51:52 PM UTC 25
Peak memory 230284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894614607 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na
me 47.edn_err.894614607
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/47.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/47.edn_genbits.3599374012
Short name T315
Test name
Test status
Simulation time 123644745 ps
CPU time 1.73 seconds
Started Feb 09 01:51:41 PM UTC 25
Finished Feb 09 01:51:44 PM UTC 25
Peak memory 230312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599374012 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.edn_genbits.3599374012
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/47.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/47.edn_intr.4135354904
Short name T568
Test name
Test status
Simulation time 31651692 ps
CPU time 1.31 seconds
Started Feb 09 01:51:48 PM UTC 25
Finished Feb 09 01:51:51 PM UTC 25
Peak memory 226208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135354904 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 47.edn_intr.4135354904
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/47.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/47.edn_smoke.1069212764
Short name T567
Test name
Test status
Simulation time 17046181 ps
CPU time 1.48 seconds
Started Feb 09 01:51:41 PM UTC 25
Finished Feb 09 01:51:43 PM UTC 25
Peak memory 226152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069212764 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 47.edn_smoke.1069212764
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/47.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/47.edn_stress_all.3604406804
Short name T570
Test name
Test status
Simulation time 580807867 ps
CPU time 6.85 seconds
Started Feb 09 01:51:44 PM UTC 25
Finished Feb 09 01:51:52 PM UTC 25
Peak memory 231656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604406804 -assert nopostproc +UVM_TESTNAME=edn_stress_all
_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.3604406804
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/47.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/47.edn_stress_all_with_rand_reset.4148362911
Short name T995
Test name
Test status
Simulation time 324334266035 ps
CPU time 2174.78 seconds
Started Feb 09 01:51:45 PM UTC 25
Finished Feb 09 02:28:23 PM UTC 25
Peak memory 240340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4148362911 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.4148362911
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/47.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/48.edn_alert_test.4186316859
Short name T580
Test name
Test status
Simulation time 13548342 ps
CPU time 1.36 seconds
Started Feb 09 01:52:03 PM UTC 25
Finished Feb 09 01:52:05 PM UTC 25
Peak memory 215704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186316859 -assert nopostproc +UVM_TESTNAME=edn_base_test +UV
M_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.4186316859
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/48.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/48.edn_disable.608081187
Short name T578
Test name
Test status
Simulation time 69751125 ps
CPU time 1.34 seconds
Started Feb 09 01:52:01 PM UTC 25
Finished Feb 09 01:52:03 PM UTC 25
Peak memory 230116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608081187 -assert nopostproc +UVM_TESTNAME=edn_disable_test +U
VM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.edn_disable.608081187
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/48.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/48.edn_disable_auto_req_mode.2376693977
Short name T581
Test name
Test status
Simulation time 129543488 ps
CPU time 1.91 seconds
Started Feb 09 01:52:03 PM UTC 25
Finished Feb 09 01:52:06 PM UTC 25
Peak memory 230180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376693977 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_r
eq_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable_auto_req_mode.2376693977
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/48.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/48.edn_err.3236677481
Short name T577
Test name
Test status
Simulation time 25281152 ps
CPU time 1.48 seconds
Started Feb 09 01:51:59 PM UTC 25
Finished Feb 09 01:52:02 PM UTC 25
Peak memory 230176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236677481 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 48.edn_err.3236677481
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/48.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/48.edn_genbits.2902794087
Short name T575
Test name
Test status
Simulation time 32017572 ps
CPU time 2.27 seconds
Started Feb 09 01:51:55 PM UTC 25
Finished Feb 09 01:51:58 PM UTC 25
Peak memory 229676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902794087 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.edn_genbits.2902794087
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/48.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/48.edn_intr.1763399945
Short name T576
Test name
Test status
Simulation time 39111019 ps
CPU time 1.28 seconds
Started Feb 09 01:51:56 PM UTC 25
Finished Feb 09 01:51:59 PM UTC 25
Peak memory 226568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763399945 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 48.edn_intr.1763399945
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/48.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/48.edn_smoke.2503720151
Short name T573
Test name
Test status
Simulation time 51122563 ps
CPU time 1.13 seconds
Started Feb 09 01:51:53 PM UTC 25
Finished Feb 09 01:51:55 PM UTC 25
Peak memory 226152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503720151 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 48.edn_smoke.2503720151
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/48.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/48.edn_stress_all.3138768133
Short name T579
Test name
Test status
Simulation time 558698760 ps
CPU time 8.15 seconds
Started Feb 09 01:51:55 PM UTC 25
Finished Feb 09 01:52:04 PM UTC 25
Peak memory 229276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138768133 -assert nopostproc +UVM_TESTNAME=edn_stress_all
_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.3138768133
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/48.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/48.edn_stress_all_with_rand_reset.504383144
Short name T990
Test name
Test status
Simulation time 544166829061 ps
CPU time 1206.5 seconds
Started Feb 09 01:51:56 PM UTC 25
Finished Feb 09 02:12:16 PM UTC 25
Peak memory 234272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=504383144 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.504383144
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/48.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/49.edn_alert.3120288622
Short name T587
Test name
Test status
Simulation time 30202313 ps
CPU time 1.84 seconds
Started Feb 09 01:52:09 PM UTC 25
Finished Feb 09 01:52:12 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120288622 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 49.edn_alert.3120288622
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/49.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/49.edn_alert_test.1789287853
Short name T590
Test name
Test status
Simulation time 32915696 ps
CPU time 1.26 seconds
Started Feb 09 01:52:13 PM UTC 25
Finished Feb 09 01:52:16 PM UTC 25
Peak memory 226640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789287853 -assert nopostproc +UVM_TESTNAME=edn_base_test +UV
M_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.1789287853
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/49.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/49.edn_disable.3393970332
Short name T588
Test name
Test status
Simulation time 24226138 ps
CPU time 1.27 seconds
Started Feb 09 01:52:10 PM UTC 25
Finished Feb 09 01:52:13 PM UTC 25
Peak memory 226012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393970332 -assert nopostproc +UVM_TESTNAME=edn_disable_test +
UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.edn_disable.3393970332
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/49.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/49.edn_disable_auto_req_mode.912715265
Short name T589
Test name
Test status
Simulation time 76232321 ps
CPU time 1.47 seconds
Started Feb 09 01:52:12 PM UTC 25
Finished Feb 09 01:52:15 PM UTC 25
Peak memory 230172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912715265 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_re
q_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable_auto_req_mode.912715265
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/49.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/49.edn_err.3297044317
Short name T586
Test name
Test status
Simulation time 34988421 ps
CPU time 1.36 seconds
Started Feb 09 01:52:09 PM UTC 25
Finished Feb 09 01:52:12 PM UTC 25
Peak memory 230304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297044317 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 49.edn_err.3297044317
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/49.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/49.edn_genbits.651022716
Short name T583
Test name
Test status
Simulation time 68295164 ps
CPU time 2.22 seconds
Started Feb 09 01:52:05 PM UTC 25
Finished Feb 09 01:52:08 PM UTC 25
Peak memory 229360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651022716 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.edn_genbits.651022716
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/49.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/49.edn_intr.600726593
Short name T585
Test name
Test status
Simulation time 25013192 ps
CPU time 1.6 seconds
Started Feb 09 01:52:07 PM UTC 25
Finished Feb 09 01:52:10 PM UTC 25
Peak memory 237060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600726593 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 49.edn_intr.600726593
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/49.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/49.edn_smoke.868233292
Short name T582
Test name
Test status
Simulation time 23264154 ps
CPU time 1.36 seconds
Started Feb 09 01:52:04 PM UTC 25
Finished Feb 09 01:52:07 PM UTC 25
Peak memory 226136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868233292 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 49.edn_smoke.868233292
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/49.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/49.edn_stress_all.2374425308
Short name T584
Test name
Test status
Simulation time 46757571 ps
CPU time 1.7 seconds
Started Feb 09 01:52:06 PM UTC 25
Finished Feb 09 01:52:09 PM UTC 25
Peak memory 226156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374425308 -assert nopostproc +UVM_TESTNAME=edn_stress_all
_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.2374425308
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/49.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/49.edn_stress_all_with_rand_reset.2760081180
Short name T991
Test name
Test status
Simulation time 57582764674 ps
CPU time 1236.08 seconds
Started Feb 09 01:52:07 PM UTC 25
Finished Feb 09 02:12:57 PM UTC 25
Peak memory 231744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2760081180 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.2760081180
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/49.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/5.edn_alert_test.3017677596
Short name T367
Test name
Test status
Simulation time 64463896 ps
CPU time 1.42 seconds
Started Feb 09 01:29:50 PM UTC 25
Finished Feb 09 01:29:53 PM UTC 25
Peak memory 216088 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017677596 -assert nopostproc +UVM_TESTNAME=edn_base_test +UV
M_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.3017677596
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/5.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/5.edn_disable.4038158640
Short name T184
Test name
Test status
Simulation time 39922482 ps
CPU time 1.21 seconds
Started Feb 09 01:29:47 PM UTC 25
Finished Feb 09 01:29:49 PM UTC 25
Peak memory 228068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038158640 -assert nopostproc +UVM_TESTNAME=edn_disable_test +
UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.edn_disable.4038158640
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/5.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/5.edn_err.1673886570
Short name T365
Test name
Test status
Simulation time 23708189 ps
CPU time 1.76 seconds
Started Feb 09 01:29:46 PM UTC 25
Finished Feb 09 01:29:49 PM UTC 25
Peak memory 230192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673886570 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 5.edn_err.1673886570
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/5.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/5.edn_intr.4085163727
Short name T59
Test name
Test status
Simulation time 50557899 ps
CPU time 1.44 seconds
Started Feb 09 01:29:43 PM UTC 25
Finished Feb 09 01:29:45 PM UTC 25
Peak memory 236596 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085163727 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 5.edn_intr.4085163727
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/5.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/5.edn_regwen.3021541861
Short name T122
Test name
Test status
Simulation time 169961622 ps
CPU time 1.42 seconds
Started Feb 09 01:29:36 PM UTC 25
Finished Feb 09 01:29:39 PM UTC 25
Peak memory 215908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021541861 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 5.edn_regwen.3021541861
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/5.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/5.edn_smoke.1327263541
Short name T117
Test name
Test status
Simulation time 46692526 ps
CPU time 1.32 seconds
Started Feb 09 01:29:33 PM UTC 25
Finished Feb 09 01:29:36 PM UTC 25
Peak memory 226148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327263541 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 5.edn_smoke.1327263541
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/5.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/5.edn_stress_all.294796323
Short name T116
Test name
Test status
Simulation time 35142438 ps
CPU time 1.96 seconds
Started Feb 09 01:29:39 PM UTC 25
Finished Feb 09 01:29:43 PM UTC 25
Peak memory 228404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294796323 -assert nopostproc +UVM_TESTNAME=edn_stress_all_
test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.294796323
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/5.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/5.edn_stress_all_with_rand_reset.4195635569
Short name T993
Test name
Test status
Simulation time 689606091685 ps
CPU time 2804.84 seconds
Started Feb 09 01:29:39 PM UTC 25
Finished Feb 09 02:16:55 PM UTC 25
Peak memory 250568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4195635569 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.4195635569
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/5.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/50.edn_alert.707984988
Short name T593
Test name
Test status
Simulation time 74171582 ps
CPU time 2.02 seconds
Started Feb 09 01:52:16 PM UTC 25
Finished Feb 09 01:52:19 PM UTC 25
Peak memory 232128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707984988 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 50.edn_alert.707984988
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/50.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/50.edn_err.588747868
Short name T591
Test name
Test status
Simulation time 33340180 ps
CPU time 1.54 seconds
Started Feb 09 01:52:17 PM UTC 25
Finished Feb 09 01:52:19 PM UTC 25
Peak memory 230304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588747868 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na
me 50.edn_err.588747868
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/50.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/50.edn_genbits.3549883141
Short name T592
Test name
Test status
Simulation time 45754334 ps
CPU time 1.94 seconds
Started Feb 09 01:52:13 PM UTC 25
Finished Feb 09 01:52:17 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549883141 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 50.edn_genbits.3549883141
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/50.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/51.edn_alert.2030368465
Short name T594
Test name
Test status
Simulation time 23378354 ps
CPU time 1.73 seconds
Started Feb 09 01:52:20 PM UTC 25
Finished Feb 09 01:52:23 PM UTC 25
Peak memory 230308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030368465 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 51.edn_alert.2030368465
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/51.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/51.edn_err.2460470032
Short name T188
Test name
Test status
Simulation time 23022281 ps
CPU time 1.52 seconds
Started Feb 09 01:52:20 PM UTC 25
Finished Feb 09 01:52:22 PM UTC 25
Peak memory 237060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460470032 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 51.edn_err.2460470032
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/51.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/51.edn_genbits.180227007
Short name T357
Test name
Test status
Simulation time 71450407 ps
CPU time 3.84 seconds
Started Feb 09 01:52:18 PM UTC 25
Finished Feb 09 01:52:23 PM UTC 25
Peak memory 231412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180227007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 51.edn_genbits.180227007
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/51.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/52.edn_alert.3001377667
Short name T328
Test name
Test status
Simulation time 28697273 ps
CPU time 1.89 seconds
Started Feb 09 01:52:24 PM UTC 25
Finished Feb 09 01:52:27 PM UTC 25
Peak memory 228320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001377667 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 52.edn_alert.3001377667
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/52.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/52.edn_err.2121595554
Short name T596
Test name
Test status
Simulation time 37602348 ps
CPU time 1.34 seconds
Started Feb 09 01:52:24 PM UTC 25
Finished Feb 09 01:52:26 PM UTC 25
Peak memory 228256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121595554 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 52.edn_err.2121595554
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/52.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/52.edn_genbits.2697962289
Short name T595
Test name
Test status
Simulation time 40024030 ps
CPU time 2.15 seconds
Started Feb 09 01:52:23 PM UTC 25
Finished Feb 09 01:52:26 PM UTC 25
Peak memory 229600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697962289 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 52.edn_genbits.2697962289
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/52.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/53.edn_alert.2577266973
Short name T597
Test name
Test status
Simulation time 84124112 ps
CPU time 1.66 seconds
Started Feb 09 01:52:27 PM UTC 25
Finished Feb 09 01:52:30 PM UTC 25
Peak memory 226252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577266973 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 53.edn_alert.2577266973
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/53.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/53.edn_err.4026744160
Short name T161
Test name
Test status
Simulation time 21063278 ps
CPU time 1.66 seconds
Started Feb 09 01:52:28 PM UTC 25
Finished Feb 09 01:52:31 PM UTC 25
Peak memory 230304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026744160 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 53.edn_err.4026744160
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/53.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/53.edn_genbits.2296098415
Short name T599
Test name
Test status
Simulation time 271681756 ps
CPU time 6.42 seconds
Started Feb 09 01:52:27 PM UTC 25
Finished Feb 09 01:52:35 PM UTC 25
Peak memory 231324 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296098415 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 53.edn_genbits.2296098415
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/53.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/54.edn_alert.4246466318
Short name T600
Test name
Test status
Simulation time 57157029 ps
CPU time 1.77 seconds
Started Feb 09 01:52:32 PM UTC 25
Finished Feb 09 01:52:35 PM UTC 25
Peak memory 226252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246466318 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 54.edn_alert.4246466318
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/54.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/54.edn_err.2483697379
Short name T601
Test name
Test status
Simulation time 20610181 ps
CPU time 1.67 seconds
Started Feb 09 01:52:34 PM UTC 25
Finished Feb 09 01:52:37 PM UTC 25
Peak memory 230292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483697379 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 54.edn_err.2483697379
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/54.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/54.edn_genbits.2053184579
Short name T598
Test name
Test status
Simulation time 77759234 ps
CPU time 1.54 seconds
Started Feb 09 01:52:31 PM UTC 25
Finished Feb 09 01:52:34 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053184579 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 54.edn_genbits.2053184579
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/54.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/55.edn_alert.2151778469
Short name T602
Test name
Test status
Simulation time 69381799 ps
CPU time 1.62 seconds
Started Feb 09 01:52:35 PM UTC 25
Finished Feb 09 01:52:38 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151778469 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 55.edn_alert.2151778469
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/55.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/55.edn_err.753989262
Short name T222
Test name
Test status
Simulation time 33161794 ps
CPU time 1.7 seconds
Started Feb 09 01:52:38 PM UTC 25
Finished Feb 09 01:52:41 PM UTC 25
Peak memory 243992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753989262 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na
me 55.edn_err.753989262
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/55.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/55.edn_genbits.2809745724
Short name T603
Test name
Test status
Simulation time 134028476 ps
CPU time 1.63 seconds
Started Feb 09 01:52:35 PM UTC 25
Finished Feb 09 01:52:38 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809745724 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 55.edn_genbits.2809745724
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/55.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/56.edn_alert.447528513
Short name T191
Test name
Test status
Simulation time 27132547 ps
CPU time 1.81 seconds
Started Feb 09 01:52:39 PM UTC 25
Finished Feb 09 01:52:42 PM UTC 25
Peak memory 230428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447528513 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 56.edn_alert.447528513
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/56.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/56.edn_err.1962216569
Short name T607
Test name
Test status
Simulation time 56232145 ps
CPU time 1.67 seconds
Started Feb 09 01:52:43 PM UTC 25
Finished Feb 09 01:52:45 PM UTC 25
Peak memory 236856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962216569 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 56.edn_err.1962216569
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/56.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/56.edn_genbits.2262522580
Short name T604
Test name
Test status
Simulation time 55141469 ps
CPU time 2.28 seconds
Started Feb 09 01:52:38 PM UTC 25
Finished Feb 09 01:52:42 PM UTC 25
Peak memory 229604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262522580 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 56.edn_genbits.2262522580
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/56.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/57.edn_alert.1323367484
Short name T151
Test name
Test status
Simulation time 26768568 ps
CPU time 1.84 seconds
Started Feb 09 01:52:44 PM UTC 25
Finished Feb 09 01:52:47 PM UTC 25
Peak memory 228320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323367484 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 57.edn_alert.1323367484
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/57.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/57.edn_err.2578980663
Short name T138
Test name
Test status
Simulation time 154842750 ps
CPU time 1.42 seconds
Started Feb 09 01:52:44 PM UTC 25
Finished Feb 09 01:52:46 PM UTC 25
Peak memory 230308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578980663 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 57.edn_err.2578980663
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/57.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/57.edn_genbits.2971835195
Short name T606
Test name
Test status
Simulation time 181751562 ps
CPU time 1.6 seconds
Started Feb 09 01:52:43 PM UTC 25
Finished Feb 09 01:52:45 PM UTC 25
Peak memory 226216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971835195 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 57.edn_genbits.2971835195
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/57.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/58.edn_alert.2243845377
Short name T325
Test name
Test status
Simulation time 29628453 ps
CPU time 1.86 seconds
Started Feb 09 01:52:47 PM UTC 25
Finished Feb 09 01:52:50 PM UTC 25
Peak memory 228316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243845377 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 58.edn_alert.2243845377
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/58.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/58.edn_err.1868519710
Short name T608
Test name
Test status
Simulation time 20133100 ps
CPU time 1.75 seconds
Started Feb 09 01:52:47 PM UTC 25
Finished Feb 09 01:52:50 PM UTC 25
Peak memory 236856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868519710 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 58.edn_err.1868519710
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/58.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/58.edn_genbits.921358788
Short name T609
Test name
Test status
Simulation time 154725774 ps
CPU time 2.86 seconds
Started Feb 09 01:52:46 PM UTC 25
Finished Feb 09 01:52:50 PM UTC 25
Peak memory 231540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921358788 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 58.edn_genbits.921358788
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/58.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/59.edn_alert.1383375613
Short name T612
Test name
Test status
Simulation time 28839808 ps
CPU time 1.54 seconds
Started Feb 09 01:52:51 PM UTC 25
Finished Feb 09 01:52:54 PM UTC 25
Peak memory 228320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383375613 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 59.edn_alert.1383375613
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/59.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/59.edn_err.2986233123
Short name T611
Test name
Test status
Simulation time 60829502 ps
CPU time 1.06 seconds
Started Feb 09 01:52:51 PM UTC 25
Finished Feb 09 01:52:53 PM UTC 25
Peak memory 228256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986233123 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 59.edn_err.2986233123
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/59.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/59.edn_genbits.3981537614
Short name T610
Test name
Test status
Simulation time 46020025 ps
CPU time 1.73 seconds
Started Feb 09 01:52:48 PM UTC 25
Finished Feb 09 01:52:51 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981537614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 59.edn_genbits.3981537614
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/59.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/6.edn_alert_test.1747881474
Short name T369
Test name
Test status
Simulation time 18951669 ps
CPU time 1.45 seconds
Started Feb 09 01:30:04 PM UTC 25
Finished Feb 09 01:30:07 PM UTC 25
Peak memory 217132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747881474 -assert nopostproc +UVM_TESTNAME=edn_base_test +UV
M_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.1747881474
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/6.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/6.edn_disable.2851644698
Short name T71
Test name
Test status
Simulation time 11992099 ps
CPU time 1.38 seconds
Started Feb 09 01:30:03 PM UTC 25
Finished Feb 09 01:30:05 PM UTC 25
Peak memory 226008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851644698 -assert nopostproc +UVM_TESTNAME=edn_disable_test +
UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.edn_disable.2851644698
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/6.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/6.edn_disable_auto_req_mode.493319172
Short name T22
Test name
Test status
Simulation time 110976797 ps
CPU time 1.68 seconds
Started Feb 09 01:30:03 PM UTC 25
Finished Feb 09 01:30:06 PM UTC 25
Peak memory 228124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493319172 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_re
q_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable_auto_req_mode.493319172
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/6.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/6.edn_err.1819936164
Short name T181
Test name
Test status
Simulation time 18923499 ps
CPU time 1.55 seconds
Started Feb 09 01:30:00 PM UTC 25
Finished Feb 09 01:30:03 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819936164 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 6.edn_err.1819936164
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/6.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/6.edn_genbits.1984175125
Short name T312
Test name
Test status
Simulation time 43845734 ps
CPU time 2.18 seconds
Started Feb 09 01:29:53 PM UTC 25
Finished Feb 09 01:29:57 PM UTC 25
Peak memory 229352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984175125 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.edn_genbits.1984175125
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/6.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/6.edn_intr.4052437990
Short name T368
Test name
Test status
Simulation time 22739017 ps
CPU time 1.59 seconds
Started Feb 09 01:29:57 PM UTC 25
Finished Feb 09 01:30:00 PM UTC 25
Peak memory 226452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052437990 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 6.edn_intr.4052437990
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/6.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/6.edn_regwen.3899108411
Short name T326
Test name
Test status
Simulation time 16808294 ps
CPU time 1.53 seconds
Started Feb 09 01:29:52 PM UTC 25
Finished Feb 09 01:29:55 PM UTC 25
Peak memory 215908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899108411 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 6.edn_regwen.3899108411
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/6.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/6.edn_smoke.1472038259
Short name T366
Test name
Test status
Simulation time 38694007 ps
CPU time 1.31 seconds
Started Feb 09 01:29:50 PM UTC 25
Finished Feb 09 01:29:53 PM UTC 25
Peak memory 226152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472038259 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 6.edn_smoke.1472038259
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/6.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/6.edn_stress_all.2175458199
Short name T322
Test name
Test status
Simulation time 131603469 ps
CPU time 2.82 seconds
Started Feb 09 01:29:53 PM UTC 25
Finished Feb 09 01:29:57 PM UTC 25
Peak memory 229356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175458199 -assert nopostproc +UVM_TESTNAME=edn_stress_all
_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.2175458199
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/6.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/6.edn_stress_all_with_rand_reset.1664571294
Short name T647
Test name
Test status
Simulation time 171246897850 ps
CPU time 1394.61 seconds
Started Feb 09 01:29:55 PM UTC 25
Finished Feb 09 01:53:27 PM UTC 25
Peak memory 234176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1664571294 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.1664571294
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/6.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/60.edn_alert.1964861873
Short name T152
Test name
Test status
Simulation time 24883080 ps
CPU time 1.77 seconds
Started Feb 09 01:52:52 PM UTC 25
Finished Feb 09 01:52:55 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964861873 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 60.edn_alert.1964861873
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/60.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/60.edn_err.1849733384
Short name T613
Test name
Test status
Simulation time 19023606 ps
CPU time 1.5 seconds
Started Feb 09 01:52:54 PM UTC 25
Finished Feb 09 01:52:57 PM UTC 25
Peak memory 228196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849733384 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 60.edn_err.1849733384
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/60.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/61.edn_alert.2794011873
Short name T615
Test name
Test status
Simulation time 30622100 ps
CPU time 1.79 seconds
Started Feb 09 01:52:55 PM UTC 25
Finished Feb 09 01:52:58 PM UTC 25
Peak memory 230024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794011873 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 61.edn_alert.2794011873
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/61.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/61.edn_err.2346586756
Short name T616
Test name
Test status
Simulation time 29584706 ps
CPU time 1.23 seconds
Started Feb 09 01:52:56 PM UTC 25
Finished Feb 09 01:52:59 PM UTC 25
Peak memory 236856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346586756 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 61.edn_err.2346586756
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/61.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/61.edn_genbits.1456389248
Short name T614
Test name
Test status
Simulation time 35465299 ps
CPU time 1.73 seconds
Started Feb 09 01:52:55 PM UTC 25
Finished Feb 09 01:52:58 PM UTC 25
Peak memory 227932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456389248 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 61.edn_genbits.1456389248
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/61.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/62.edn_err.4098564964
Short name T198
Test name
Test status
Simulation time 36475099 ps
CPU time 1.39 seconds
Started Feb 09 01:52:58 PM UTC 25
Finished Feb 09 01:53:01 PM UTC 25
Peak memory 236856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098564964 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 62.edn_err.4098564964
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/62.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/62.edn_genbits.2949933893
Short name T617
Test name
Test status
Simulation time 212824565 ps
CPU time 1.56 seconds
Started Feb 09 01:52:57 PM UTC 25
Finished Feb 09 01:53:00 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949933893 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 62.edn_genbits.2949933893
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/62.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/63.edn_alert.4174003096
Short name T192
Test name
Test status
Simulation time 23063626 ps
CPU time 1.67 seconds
Started Feb 09 01:52:59 PM UTC 25
Finished Feb 09 01:53:02 PM UTC 25
Peak memory 228320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174003096 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 63.edn_alert.4174003096
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/63.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/63.edn_err.1492537298
Short name T149
Test name
Test status
Simulation time 21138754 ps
CPU time 1.78 seconds
Started Feb 09 01:53:01 PM UTC 25
Finished Feb 09 01:53:03 PM UTC 25
Peak memory 244112 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492537298 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 63.edn_err.1492537298
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/63.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/63.edn_genbits.150391125
Short name T358
Test name
Test status
Simulation time 79066026 ps
CPU time 1.77 seconds
Started Feb 09 01:52:58 PM UTC 25
Finished Feb 09 01:53:01 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150391125 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 63.edn_genbits.150391125
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/63.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/64.edn_err.830817315
Short name T620
Test name
Test status
Simulation time 32268918 ps
CPU time 1.35 seconds
Started Feb 09 01:53:02 PM UTC 25
Finished Feb 09 01:53:04 PM UTC 25
Peak memory 228196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830817315 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na
me 64.edn_err.830817315
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/64.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/64.edn_genbits.162514487
Short name T619
Test name
Test status
Simulation time 131547113 ps
CPU time 2.04 seconds
Started Feb 09 01:53:01 PM UTC 25
Finished Feb 09 01:53:04 PM UTC 25
Peak memory 231648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162514487 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 64.edn_genbits.162514487
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/64.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/65.edn_alert.2897424522
Short name T196
Test name
Test status
Simulation time 51443622 ps
CPU time 1.82 seconds
Started Feb 09 01:53:03 PM UTC 25
Finished Feb 09 01:53:06 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897424522 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 65.edn_alert.2897424522
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/65.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/65.edn_err.2236941705
Short name T621
Test name
Test status
Simulation time 70492009 ps
CPU time 1.51 seconds
Started Feb 09 01:53:04 PM UTC 25
Finished Feb 09 01:53:06 PM UTC 25
Peak memory 230304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236941705 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 65.edn_err.2236941705
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/65.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/65.edn_genbits.2132666663
Short name T344
Test name
Test status
Simulation time 31185113 ps
CPU time 2 seconds
Started Feb 09 01:53:02 PM UTC 25
Finished Feb 09 01:53:05 PM UTC 25
Peak memory 230312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132666663 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 65.edn_genbits.2132666663
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/65.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/66.edn_alert.1496170345
Short name T623
Test name
Test status
Simulation time 139071794 ps
CPU time 1.68 seconds
Started Feb 09 01:53:05 PM UTC 25
Finished Feb 09 01:53:08 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496170345 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 66.edn_alert.1496170345
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/66.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/66.edn_err.3996577063
Short name T622
Test name
Test status
Simulation time 18487339 ps
CPU time 1.47 seconds
Started Feb 09 01:53:05 PM UTC 25
Finished Feb 09 01:53:08 PM UTC 25
Peak memory 228256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996577063 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 66.edn_err.3996577063
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/66.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/66.edn_genbits.992592942
Short name T624
Test name
Test status
Simulation time 36538555 ps
CPU time 2 seconds
Started Feb 09 01:53:05 PM UTC 25
Finished Feb 09 01:53:08 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992592942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 66.edn_genbits.992592942
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/66.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/67.edn_alert.2239027467
Short name T202
Test name
Test status
Simulation time 81728910 ps
CPU time 1.76 seconds
Started Feb 09 01:53:07 PM UTC 25
Finished Feb 09 01:53:10 PM UTC 25
Peak memory 226212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239027467 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 67.edn_alert.2239027467
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/67.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/67.edn_err.683995446
Short name T626
Test name
Test status
Simulation time 40899339 ps
CPU time 1.35 seconds
Started Feb 09 01:53:07 PM UTC 25
Finished Feb 09 01:53:10 PM UTC 25
Peak memory 230304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683995446 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na
me 67.edn_err.683995446
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/67.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/67.edn_genbits.2528959572
Short name T625
Test name
Test status
Simulation time 42837868 ps
CPU time 1.59 seconds
Started Feb 09 01:53:06 PM UTC 25
Finished Feb 09 01:53:09 PM UTC 25
Peak memory 228260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528959572 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 67.edn_genbits.2528959572
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/67.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/68.edn_alert.1166658654
Short name T321
Test name
Test status
Simulation time 38963458 ps
CPU time 1.67 seconds
Started Feb 09 01:53:08 PM UTC 25
Finished Feb 09 01:53:11 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166658654 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 68.edn_alert.1166658654
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/68.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/68.edn_err.1629313952
Short name T628
Test name
Test status
Simulation time 19628873 ps
CPU time 1.44 seconds
Started Feb 09 01:53:09 PM UTC 25
Finished Feb 09 01:53:12 PM UTC 25
Peak memory 228256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629313952 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 68.edn_err.1629313952
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/68.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/69.edn_alert.751830774
Short name T185
Test name
Test status
Simulation time 78931561 ps
CPU time 1.66 seconds
Started Feb 09 01:53:10 PM UTC 25
Finished Feb 09 01:53:13 PM UTC 25
Peak memory 226052 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751830774 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 69.edn_alert.751830774
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/69.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/69.edn_genbits.4268392366
Short name T629
Test name
Test status
Simulation time 43786000 ps
CPU time 2.11 seconds
Started Feb 09 01:53:09 PM UTC 25
Finished Feb 09 01:53:12 PM UTC 25
Peak memory 229604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268392366 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 69.edn_genbits.4268392366
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/69.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/7.edn_alert_test.3510226241
Short name T371
Test name
Test status
Simulation time 41341570 ps
CPU time 1.25 seconds
Started Feb 09 01:30:18 PM UTC 25
Finished Feb 09 01:30:20 PM UTC 25
Peak memory 215704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510226241 -assert nopostproc +UVM_TESTNAME=edn_base_test +UV
M_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.3510226241
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/7.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/7.edn_disable.1366184067
Short name T172
Test name
Test status
Simulation time 46886760 ps
CPU time 1.25 seconds
Started Feb 09 01:30:15 PM UTC 25
Finished Feb 09 01:30:17 PM UTC 25
Peak memory 226268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366184067 -assert nopostproc +UVM_TESTNAME=edn_disable_test +
UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.edn_disable.1366184067
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/7.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/7.edn_disable_auto_req_mode.2063126448
Short name T51
Test name
Test status
Simulation time 74729867 ps
CPU time 1.73 seconds
Started Feb 09 01:30:17 PM UTC 25
Finished Feb 09 01:30:20 PM UTC 25
Peak memory 228120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063126448 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_r
eq_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable_auto_req_mode.2063126448
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/7.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/7.edn_err.1781971672
Short name T61
Test name
Test status
Simulation time 22747076 ps
CPU time 1.82 seconds
Started Feb 09 01:30:13 PM UTC 25
Finished Feb 09 01:30:16 PM UTC 25
Peak memory 244536 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781971672 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 7.edn_err.1781971672
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/7.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/7.edn_genbits.1324016773
Short name T49
Test name
Test status
Simulation time 36538482 ps
CPU time 2.27 seconds
Started Feb 09 01:30:06 PM UTC 25
Finished Feb 09 01:30:10 PM UTC 25
Peak memory 229344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324016773 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.edn_genbits.1324016773
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/7.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/7.edn_intr.519781586
Short name T60
Test name
Test status
Simulation time 33470316 ps
CPU time 1.48 seconds
Started Feb 09 01:30:09 PM UTC 25
Finished Feb 09 01:30:12 PM UTC 25
Peak memory 236592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519781586 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 7.edn_intr.519781586
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/7.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/7.edn_regwen.803646275
Short name T330
Test name
Test status
Simulation time 45980920 ps
CPU time 1.41 seconds
Started Feb 09 01:30:06 PM UTC 25
Finished Feb 09 01:30:09 PM UTC 25
Peak memory 215912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803646275 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 7.edn_regwen.803646275
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/7.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/7.edn_smoke.1944736366
Short name T370
Test name
Test status
Simulation time 87254106 ps
CPU time 1.43 seconds
Started Feb 09 01:30:04 PM UTC 25
Finished Feb 09 01:30:07 PM UTC 25
Peak memory 226152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944736366 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 7.edn_smoke.1944736366
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/7.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/7.edn_stress_all_with_rand_reset.6511799
Short name T987
Test name
Test status
Simulation time 100791959508 ps
CPU time 2142.77 seconds
Started Feb 09 01:30:07 PM UTC 25
Finished Feb 09 02:06:14 PM UTC 25
Peak memory 236312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=6511799 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.6511799
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/7.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/70.edn_alert.41767238
Short name T632
Test name
Test status
Simulation time 52246393 ps
CPU time 1.72 seconds
Started Feb 09 01:53:13 PM UTC 25
Finished Feb 09 01:53:15 PM UTC 25
Peak memory 228328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41767238 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 70.edn_alert.41767238
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/70.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/70.edn_err.2270359335
Short name T631
Test name
Test status
Simulation time 34825160 ps
CPU time 1.29 seconds
Started Feb 09 01:53:13 PM UTC 25
Finished Feb 09 01:53:15 PM UTC 25
Peak memory 228260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270359335 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 70.edn_err.2270359335
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/70.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/70.edn_genbits.1741607477
Short name T630
Test name
Test status
Simulation time 40195528 ps
CPU time 2.04 seconds
Started Feb 09 01:53:11 PM UTC 25
Finished Feb 09 01:53:15 PM UTC 25
Peak memory 229360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741607477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 70.edn_genbits.1741607477
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/70.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/71.edn_alert.2382608985
Short name T633
Test name
Test status
Simulation time 78415984 ps
CPU time 1.64 seconds
Started Feb 09 01:53:14 PM UTC 25
Finished Feb 09 01:53:16 PM UTC 25
Peak memory 228320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382608985 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 71.edn_alert.2382608985
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/71.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/71.edn_err.3777044741
Short name T219
Test name
Test status
Simulation time 42999091 ps
CPU time 1.45 seconds
Started Feb 09 01:53:14 PM UTC 25
Finished Feb 09 01:53:16 PM UTC 25
Peak memory 236856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777044741 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 71.edn_err.3777044741
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/71.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/71.edn_genbits.2239307682
Short name T634
Test name
Test status
Simulation time 65768904 ps
CPU time 2.1 seconds
Started Feb 09 01:53:14 PM UTC 25
Finished Feb 09 01:53:17 PM UTC 25
Peak memory 229604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239307682 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 71.edn_genbits.2239307682
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/71.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/72.edn_alert.2618317060
Short name T193
Test name
Test status
Simulation time 373104206 ps
CPU time 1.76 seconds
Started Feb 09 01:53:16 PM UTC 25
Finished Feb 09 01:53:19 PM UTC 25
Peak memory 228320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618317060 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 72.edn_alert.2618317060
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/72.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/72.edn_err.4280774447
Short name T205
Test name
Test status
Simulation time 29700012 ps
CPU time 1.3 seconds
Started Feb 09 01:53:16 PM UTC 25
Finished Feb 09 01:53:18 PM UTC 25
Peak memory 228376 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280774447 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 72.edn_err.4280774447
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/72.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/72.edn_genbits.32832995
Short name T635
Test name
Test status
Simulation time 136018308 ps
CPU time 1.75 seconds
Started Feb 09 01:53:16 PM UTC 25
Finished Feb 09 01:53:19 PM UTC 25
Peak memory 228260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32832995 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 72.edn_genbits.32832995
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/72.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/73.edn_alert.146042729
Short name T323
Test name
Test status
Simulation time 27552736 ps
CPU time 1.87 seconds
Started Feb 09 01:53:17 PM UTC 25
Finished Feb 09 01:53:20 PM UTC 25
Peak memory 228260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146042729 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 73.edn_alert.146042729
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/73.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/73.edn_err.95345272
Short name T637
Test name
Test status
Simulation time 20840030 ps
CPU time 1.36 seconds
Started Feb 09 01:53:18 PM UTC 25
Finished Feb 09 01:53:20 PM UTC 25
Peak memory 226208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95345272 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 73.edn_err.95345272
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/73.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/73.edn_genbits.218147361
Short name T353
Test name
Test status
Simulation time 325262543 ps
CPU time 2.2 seconds
Started Feb 09 01:53:17 PM UTC 25
Finished Feb 09 01:53:20 PM UTC 25
Peak memory 231668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218147361 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 73.edn_genbits.218147361
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/73.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/74.edn_alert.2996474102
Short name T302
Test name
Test status
Simulation time 49702949 ps
CPU time 1.83 seconds
Started Feb 09 01:53:19 PM UTC 25
Finished Feb 09 01:53:22 PM UTC 25
Peak memory 228320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996474102 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 74.edn_alert.2996474102
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/74.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/74.edn_err.2057744130
Short name T638
Test name
Test status
Simulation time 32817750 ps
CPU time 1.51 seconds
Started Feb 09 01:53:19 PM UTC 25
Finished Feb 09 01:53:22 PM UTC 25
Peak memory 236856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057744130 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 74.edn_err.2057744130
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/74.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/74.edn_genbits.3105136252
Short name T639
Test name
Test status
Simulation time 47520328 ps
CPU time 2.16 seconds
Started Feb 09 01:53:19 PM UTC 25
Finished Feb 09 01:53:22 PM UTC 25
Peak memory 231416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105136252 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 74.edn_genbits.3105136252
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/74.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/75.edn_alert.224182500
Short name T640
Test name
Test status
Simulation time 41642910 ps
CPU time 1.27 seconds
Started Feb 09 01:53:21 PM UTC 25
Finished Feb 09 01:53:24 PM UTC 25
Peak memory 230348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224182500 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 75.edn_alert.224182500
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/75.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/75.edn_err.1456728351
Short name T641
Test name
Test status
Simulation time 48560383 ps
CPU time 1.52 seconds
Started Feb 09 01:53:21 PM UTC 25
Finished Feb 09 01:53:24 PM UTC 25
Peak memory 228316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456728351 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 75.edn_err.1456728351
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/75.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/75.edn_genbits.3197068471
Short name T643
Test name
Test status
Simulation time 51879771 ps
CPU time 2.61 seconds
Started Feb 09 01:53:21 PM UTC 25
Finished Feb 09 01:53:25 PM UTC 25
Peak memory 229344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197068471 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 75.edn_genbits.3197068471
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/75.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/76.edn_alert.3262924310
Short name T644
Test name
Test status
Simulation time 100876679 ps
CPU time 1.82 seconds
Started Feb 09 01:53:22 PM UTC 25
Finished Feb 09 01:53:25 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262924310 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 76.edn_alert.3262924310
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/76.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/76.edn_err.835468135
Short name T646
Test name
Test status
Simulation time 22939477 ps
CPU time 1.59 seconds
Started Feb 09 01:53:23 PM UTC 25
Finished Feb 09 01:53:26 PM UTC 25
Peak memory 236856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835468135 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na
me 76.edn_err.835468135
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/76.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/76.edn_genbits.489159080
Short name T642
Test name
Test status
Simulation time 36125830 ps
CPU time 1.74 seconds
Started Feb 09 01:53:21 PM UTC 25
Finished Feb 09 01:53:24 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489159080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 76.edn_genbits.489159080
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/76.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/77.edn_alert.1529782298
Short name T649
Test name
Test status
Simulation time 94098910 ps
CPU time 1.71 seconds
Started Feb 09 01:53:25 PM UTC 25
Finished Feb 09 01:53:27 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529782298 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 77.edn_alert.1529782298
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/77.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/77.edn_err.2995111472
Short name T206
Test name
Test status
Simulation time 19865180 ps
CPU time 1.59 seconds
Started Feb 09 01:53:25 PM UTC 25
Finished Feb 09 01:53:27 PM UTC 25
Peak memory 228256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995111472 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 77.edn_err.2995111472
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/77.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/77.edn_genbits.3682770641
Short name T645
Test name
Test status
Simulation time 55356057 ps
CPU time 1.52 seconds
Started Feb 09 01:53:23 PM UTC 25
Finished Feb 09 01:53:26 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682770641 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 77.edn_genbits.3682770641
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/77.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/78.edn_alert.951531714
Short name T650
Test name
Test status
Simulation time 57291740 ps
CPU time 1.37 seconds
Started Feb 09 01:53:26 PM UTC 25
Finished Feb 09 01:53:28 PM UTC 25
Peak memory 228320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951531714 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 78.edn_alert.951531714
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/78.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/78.edn_err.3097341484
Short name T162
Test name
Test status
Simulation time 25367871 ps
CPU time 1.73 seconds
Started Feb 09 01:53:26 PM UTC 25
Finished Feb 09 01:53:29 PM UTC 25
Peak memory 230288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097341484 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 78.edn_err.3097341484
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/78.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/78.edn_genbits.902505359
Short name T648
Test name
Test status
Simulation time 61295228 ps
CPU time 1.59 seconds
Started Feb 09 01:53:25 PM UTC 25
Finished Feb 09 01:53:27 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902505359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 78.edn_genbits.902505359
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/78.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/79.edn_alert.2425008003
Short name T651
Test name
Test status
Simulation time 32336169 ps
CPU time 1.61 seconds
Started Feb 09 01:53:27 PM UTC 25
Finished Feb 09 01:53:30 PM UTC 25
Peak memory 230308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425008003 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 79.edn_alert.2425008003
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/79.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/79.edn_err.3558378627
Short name T652
Test name
Test status
Simulation time 36045427 ps
CPU time 1.49 seconds
Started Feb 09 01:53:28 PM UTC 25
Finished Feb 09 01:53:30 PM UTC 25
Peak memory 236816 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558378627 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 79.edn_err.3558378627
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/79.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/79.edn_genbits.2917007862
Short name T653
Test name
Test status
Simulation time 274242672 ps
CPU time 2.82 seconds
Started Feb 09 01:53:27 PM UTC 25
Finished Feb 09 01:53:31 PM UTC 25
Peak memory 231320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917007862 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 79.edn_genbits.2917007862
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/79.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/8.edn_alert.2829659822
Short name T53
Test name
Test status
Simulation time 27225916 ps
CPU time 1.8 seconds
Started Feb 09 01:30:28 PM UTC 25
Finished Feb 09 01:30:31 PM UTC 25
Peak memory 228260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829659822 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 8.edn_alert.2829659822
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/8.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/8.edn_alert_test.3939256697
Short name T373
Test name
Test status
Simulation time 56807089 ps
CPU time 1.37 seconds
Started Feb 09 01:30:34 PM UTC 25
Finished Feb 09 01:30:37 PM UTC 25
Peak memory 217252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939256697 -assert nopostproc +UVM_TESTNAME=edn_base_test +UV
M_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.3939256697
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/8.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/8.edn_disable.1531719949
Short name T81
Test name
Test status
Simulation time 34150133 ps
CPU time 1.29 seconds
Started Feb 09 01:30:31 PM UTC 25
Finished Feb 09 01:30:34 PM UTC 25
Peak memory 226012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531719949 -assert nopostproc +UVM_TESTNAME=edn_disable_test +
UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.edn_disable.1531719949
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/8.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/8.edn_disable_auto_req_mode.1700419017
Short name T91
Test name
Test status
Simulation time 77891563 ps
CPU time 1.52 seconds
Started Feb 09 01:30:32 PM UTC 25
Finished Feb 09 01:30:35 PM UTC 25
Peak memory 230180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700419017 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_r
eq_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable_auto_req_mode.1700419017
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/8.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/8.edn_err.1158007035
Short name T183
Test name
Test status
Simulation time 63335743 ps
CPU time 1.22 seconds
Started Feb 09 01:30:28 PM UTC 25
Finished Feb 09 01:30:31 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158007035 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 8.edn_err.1158007035
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/8.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/8.edn_genbits.2741271948
Short name T72
Test name
Test status
Simulation time 60244339 ps
CPU time 1.82 seconds
Started Feb 09 01:30:21 PM UTC 25
Finished Feb 09 01:30:24 PM UTC 25
Peak memory 228464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741271948 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.edn_genbits.2741271948
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/8.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/8.edn_intr.766898701
Short name T32
Test name
Test status
Simulation time 33442591 ps
CPU time 1.09 seconds
Started Feb 09 01:30:25 PM UTC 25
Finished Feb 09 01:30:27 PM UTC 25
Peak memory 228436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766898701 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 8.edn_intr.766898701
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/8.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/8.edn_regwen.1381048733
Short name T331
Test name
Test status
Simulation time 20208742 ps
CPU time 1.48 seconds
Started Feb 09 01:30:21 PM UTC 25
Finished Feb 09 01:30:23 PM UTC 25
Peak memory 215908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381048733 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 8.edn_regwen.1381048733
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/8.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/8.edn_smoke.956819777
Short name T372
Test name
Test status
Simulation time 16629706 ps
CPU time 1.49 seconds
Started Feb 09 01:30:19 PM UTC 25
Finished Feb 09 01:30:22 PM UTC 25
Peak memory 226136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956819777 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 8.edn_smoke.956819777
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/8.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/8.edn_stress_all.176015960
Short name T311
Test name
Test status
Simulation time 490539920 ps
CPU time 4.02 seconds
Started Feb 09 01:30:22 PM UTC 25
Finished Feb 09 01:30:27 PM UTC 25
Peak memory 229336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176015960 -assert nopostproc +UVM_TESTNAME=edn_stress_all_
test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.176015960
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/8.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/8.edn_stress_all_with_rand_reset.3635099760
Short name T235
Test name
Test status
Simulation time 21026509580 ps
CPU time 749.22 seconds
Started Feb 09 01:30:24 PM UTC 25
Finished Feb 09 01:43:02 PM UTC 25
Peak memory 232000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3635099760 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.3635099760
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/8.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/80.edn_alert.181623017
Short name T203
Test name
Test status
Simulation time 86011798 ps
CPU time 1.82 seconds
Started Feb 09 01:53:28 PM UTC 25
Finished Feb 09 01:53:31 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181623017 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 80.edn_alert.181623017
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/80.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/80.edn_err.1307710936
Short name T654
Test name
Test status
Simulation time 33668913 ps
CPU time 2 seconds
Started Feb 09 01:53:28 PM UTC 25
Finished Feb 09 01:53:31 PM UTC 25
Peak memory 242108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307710936 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 80.edn_err.1307710936
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/80.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/80.edn_genbits.2116309431
Short name T657
Test name
Test status
Simulation time 391188570 ps
CPU time 5.03 seconds
Started Feb 09 01:53:28 PM UTC 25
Finished Feb 09 01:53:34 PM UTC 25
Peak memory 229240 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116309431 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 80.edn_genbits.2116309431
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/80.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/81.edn_alert.2349228061
Short name T655
Test name
Test status
Simulation time 86276208 ps
CPU time 1.66 seconds
Started Feb 09 01:53:29 PM UTC 25
Finished Feb 09 01:53:32 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349228061 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 81.edn_alert.2349228061
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/81.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/81.edn_err.2149351424
Short name T195
Test name
Test status
Simulation time 28571971 ps
CPU time 1.27 seconds
Started Feb 09 01:53:29 PM UTC 25
Finished Feb 09 01:53:32 PM UTC 25
Peak memory 228492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149351424 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 81.edn_err.2149351424
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/81.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/81.edn_genbits.2340477948
Short name T656
Test name
Test status
Simulation time 44706580 ps
CPU time 2.17 seconds
Started Feb 09 01:53:29 PM UTC 25
Finished Feb 09 01:53:33 PM UTC 25
Peak memory 229368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340477948 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 81.edn_genbits.2340477948
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/81.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/82.edn_alert.3827022567
Short name T659
Test name
Test status
Simulation time 88058729 ps
CPU time 1.67 seconds
Started Feb 09 01:53:32 PM UTC 25
Finished Feb 09 01:53:34 PM UTC 25
Peak memory 230308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827022567 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 82.edn_alert.3827022567
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/82.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/82.edn_err.1190883810
Short name T658
Test name
Test status
Simulation time 20915626 ps
CPU time 1.68 seconds
Started Feb 09 01:53:32 PM UTC 25
Finished Feb 09 01:53:34 PM UTC 25
Peak memory 230304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190883810 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 82.edn_err.1190883810
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/82.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/82.edn_genbits.2544626777
Short name T355
Test name
Test status
Simulation time 46102536 ps
CPU time 2.46 seconds
Started Feb 09 01:53:30 PM UTC 25
Finished Feb 09 01:53:34 PM UTC 25
Peak memory 231660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544626777 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 82.edn_genbits.2544626777
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/82.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/83.edn_alert.3334157550
Short name T197
Test name
Test status
Simulation time 29482665 ps
CPU time 1.82 seconds
Started Feb 09 01:53:32 PM UTC 25
Finished Feb 09 01:53:35 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334157550 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 83.edn_alert.3334157550
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/83.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/83.edn_err.3613664808
Short name T662
Test name
Test status
Simulation time 52890744 ps
CPU time 1.79 seconds
Started Feb 09 01:53:33 PM UTC 25
Finished Feb 09 01:53:36 PM UTC 25
Peak memory 230260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613664808 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 83.edn_err.3613664808
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/83.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/83.edn_genbits.3299194852
Short name T660
Test name
Test status
Simulation time 90979927 ps
CPU time 1.69 seconds
Started Feb 09 01:53:32 PM UTC 25
Finished Feb 09 01:53:35 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299194852 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 83.edn_genbits.3299194852
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/83.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/84.edn_alert.304242273
Short name T176
Test name
Test status
Simulation time 58877838 ps
CPU time 1.74 seconds
Started Feb 09 01:53:34 PM UTC 25
Finished Feb 09 01:53:37 PM UTC 25
Peak memory 228320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304242273 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 84.edn_alert.304242273
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/84.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/84.edn_err.161950691
Short name T208
Test name
Test status
Simulation time 26469606 ps
CPU time 1.39 seconds
Started Feb 09 01:53:35 PM UTC 25
Finished Feb 09 01:53:37 PM UTC 25
Peak memory 230304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161950691 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na
me 84.edn_err.161950691
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/84.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/84.edn_genbits.2810502229
Short name T661
Test name
Test status
Simulation time 74743012 ps
CPU time 1.63 seconds
Started Feb 09 01:53:33 PM UTC 25
Finished Feb 09 01:53:36 PM UTC 25
Peak memory 228256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810502229 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 84.edn_genbits.2810502229
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/84.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/85.edn_alert.49155469
Short name T665
Test name
Test status
Simulation time 26077578 ps
CPU time 1.84 seconds
Started Feb 09 01:53:35 PM UTC 25
Finished Feb 09 01:53:38 PM UTC 25
Peak memory 228268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49155469 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 85.edn_alert.49155469
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/85.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/85.edn_err.1892940537
Short name T663
Test name
Test status
Simulation time 54985510 ps
CPU time 1.25 seconds
Started Feb 09 01:53:35 PM UTC 25
Finished Feb 09 01:53:37 PM UTC 25
Peak memory 228260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892940537 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 85.edn_err.1892940537
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/85.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/85.edn_genbits.3531130374
Short name T666
Test name
Test status
Simulation time 160839283 ps
CPU time 2.12 seconds
Started Feb 09 01:53:35 PM UTC 25
Finished Feb 09 01:53:38 PM UTC 25
Peak memory 229364 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531130374 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 85.edn_genbits.3531130374
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/85.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/86.edn_alert.2732683930
Short name T664
Test name
Test status
Simulation time 73646669 ps
CPU time 1.59 seconds
Started Feb 09 01:53:35 PM UTC 25
Finished Feb 09 01:53:38 PM UTC 25
Peak memory 230308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732683930 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 86.edn_alert.2732683930
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/86.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/86.edn_err.3104976353
Short name T668
Test name
Test status
Simulation time 76793735 ps
CPU time 1.77 seconds
Started Feb 09 01:53:36 PM UTC 25
Finished Feb 09 01:53:39 PM UTC 25
Peak memory 242144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104976353 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 86.edn_err.3104976353
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/86.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/86.edn_genbits.426399748
Short name T359
Test name
Test status
Simulation time 50494225 ps
CPU time 2.31 seconds
Started Feb 09 01:53:35 PM UTC 25
Finished Feb 09 01:53:39 PM UTC 25
Peak memory 229360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426399748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 86.edn_genbits.426399748
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/86.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/87.edn_alert.28895320
Short name T669
Test name
Test status
Simulation time 166959470 ps
CPU time 1.78 seconds
Started Feb 09 01:53:37 PM UTC 25
Finished Feb 09 01:53:40 PM UTC 25
Peak memory 228328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28895320 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 87.edn_alert.28895320
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/87.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/87.edn_err.1404505510
Short name T670
Test name
Test status
Simulation time 25933337 ps
CPU time 1.48 seconds
Started Feb 09 01:53:38 PM UTC 25
Finished Feb 09 01:53:41 PM UTC 25
Peak memory 230308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404505510 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 87.edn_err.1404505510
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/87.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/87.edn_genbits.2701650390
Short name T667
Test name
Test status
Simulation time 95652520 ps
CPU time 1.56 seconds
Started Feb 09 01:53:36 PM UTC 25
Finished Feb 09 01:53:39 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701650390 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 87.edn_genbits.2701650390
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/87.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/88.edn_alert.752750266
Short name T672
Test name
Test status
Simulation time 85006847 ps
CPU time 1.8 seconds
Started Feb 09 01:53:38 PM UTC 25
Finished Feb 09 01:53:41 PM UTC 25
Peak memory 228320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752750266 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 88.edn_alert.752750266
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/88.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/88.edn_err.3955973325
Short name T673
Test name
Test status
Simulation time 50323613 ps
CPU time 1.52 seconds
Started Feb 09 01:53:39 PM UTC 25
Finished Feb 09 01:53:42 PM UTC 25
Peak memory 236860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955973325 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 88.edn_err.3955973325
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/88.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/88.edn_genbits.3579169624
Short name T671
Test name
Test status
Simulation time 70986790 ps
CPU time 1.82 seconds
Started Feb 09 01:53:38 PM UTC 25
Finished Feb 09 01:53:41 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579169624 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 88.edn_genbits.3579169624
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/88.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/89.edn_alert.1570818175
Short name T329
Test name
Test status
Simulation time 31367513 ps
CPU time 1.78 seconds
Started Feb 09 01:53:40 PM UTC 25
Finished Feb 09 01:53:42 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570818175 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 89.edn_alert.1570818175
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/89.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/89.edn_err.47337593
Short name T674
Test name
Test status
Simulation time 20022577 ps
CPU time 1.62 seconds
Started Feb 09 01:53:40 PM UTC 25
Finished Feb 09 01:53:42 PM UTC 25
Peak memory 236856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47337593 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 89.edn_err.47337593
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/89.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/89.edn_genbits.37545254
Short name T675
Test name
Test status
Simulation time 94172409 ps
CPU time 2.5 seconds
Started Feb 09 01:53:39 PM UTC 25
Finished Feb 09 01:53:43 PM UTC 25
Peak memory 229268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37545254 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 89.edn_genbits.37545254
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/89.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/9.edn_alert_test.3988166325
Short name T375
Test name
Test status
Simulation time 172566762 ps
CPU time 1.24 seconds
Started Feb 09 01:30:50 PM UTC 25
Finished Feb 09 01:30:53 PM UTC 25
Peak memory 215704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988166325 -assert nopostproc +UVM_TESTNAME=edn_base_test +UV
M_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.3988166325
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/9.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/9.edn_disable_auto_req_mode.2812392846
Short name T54
Test name
Test status
Simulation time 71823404 ps
CPU time 1.59 seconds
Started Feb 09 01:30:49 PM UTC 25
Finished Feb 09 01:30:52 PM UTC 25
Peak memory 230176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812392846 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_r
eq_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable_auto_req_mode.2812392846
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/9.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/9.edn_err.2528909681
Short name T62
Test name
Test status
Simulation time 96605211 ps
CPU time 1.4 seconds
Started Feb 09 01:30:47 PM UTC 25
Finished Feb 09 01:30:50 PM UTC 25
Peak memory 236864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528909681 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 9.edn_err.2528909681
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/9.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/9.edn_intr.2569796123
Short name T34
Test name
Test status
Simulation time 21986128 ps
CPU time 1.62 seconds
Started Feb 09 01:30:43 PM UTC 25
Finished Feb 09 01:30:46 PM UTC 25
Peak memory 228260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569796123 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 9.edn_intr.2569796123
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/9.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/9.edn_regwen.2140078487
Short name T251
Test name
Test status
Simulation time 87090483 ps
CPU time 1.38 seconds
Started Feb 09 01:30:37 PM UTC 25
Finished Feb 09 01:30:40 PM UTC 25
Peak memory 215908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140078487 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 9.edn_regwen.2140078487
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/9.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/9.edn_smoke.3909996614
Short name T374
Test name
Test status
Simulation time 50356586 ps
CPU time 1.36 seconds
Started Feb 09 01:30:35 PM UTC 25
Finished Feb 09 01:30:38 PM UTC 25
Peak memory 226148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909996614 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 9.edn_smoke.3909996614
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/9.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/9.edn_stress_all.227906892
Short name T110
Test name
Test status
Simulation time 99794539 ps
CPU time 3.58 seconds
Started Feb 09 01:30:41 PM UTC 25
Finished Feb 09 01:30:45 PM UTC 25
Peak memory 229528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227906892 -assert nopostproc +UVM_TESTNAME=edn_stress_all_
test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.227906892
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/9.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/9.edn_stress_all_with_rand_reset.3758165258
Short name T988
Test name
Test status
Simulation time 81279220825 ps
CPU time 2226.14 seconds
Started Feb 09 01:30:42 PM UTC 25
Finished Feb 09 02:08:13 PM UTC 25
Peak memory 238352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3758165258 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.3758165258
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/9.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/90.edn_alert.3921197324
Short name T679
Test name
Test status
Simulation time 23104212 ps
CPU time 1.73 seconds
Started Feb 09 01:53:42 PM UTC 25
Finished Feb 09 01:53:45 PM UTC 25
Peak memory 230136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921197324 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 90.edn_alert.3921197324
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/90.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/90.edn_err.2076409453
Short name T676
Test name
Test status
Simulation time 20915648 ps
CPU time 1.36 seconds
Started Feb 09 01:53:42 PM UTC 25
Finished Feb 09 01:53:44 PM UTC 25
Peak memory 228156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076409453 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 90.edn_err.2076409453
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/90.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/90.edn_genbits.2218823690
Short name T677
Test name
Test status
Simulation time 44426973 ps
CPU time 2.51 seconds
Started Feb 09 01:53:41 PM UTC 25
Finished Feb 09 01:53:44 PM UTC 25
Peak memory 229420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218823690 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 90.edn_genbits.2218823690
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/90.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/91.edn_err.1760003078
Short name T681
Test name
Test status
Simulation time 21302331 ps
CPU time 1.35 seconds
Started Feb 09 01:53:43 PM UTC 25
Finished Feb 09 01:53:45 PM UTC 25
Peak memory 228256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760003078 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 91.edn_err.1760003078
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/91.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/91.edn_genbits.14292806
Short name T678
Test name
Test status
Simulation time 73682765 ps
CPU time 1.58 seconds
Started Feb 09 01:53:42 PM UTC 25
Finished Feb 09 01:53:44 PM UTC 25
Peak memory 228256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14292806 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 91.edn_genbits.14292806
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/91.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/92.edn_alert.3666024995
Short name T683
Test name
Test status
Simulation time 97314131 ps
CPU time 1.75 seconds
Started Feb 09 01:53:43 PM UTC 25
Finished Feb 09 01:53:46 PM UTC 25
Peak memory 232416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666024995 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 92.edn_alert.3666024995
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/92.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/92.edn_err.2069967930
Short name T684
Test name
Test status
Simulation time 24972783 ps
CPU time 1.45 seconds
Started Feb 09 01:53:44 PM UTC 25
Finished Feb 09 01:53:47 PM UTC 25
Peak memory 228256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069967930 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 92.edn_err.2069967930
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/92.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/92.edn_genbits.839160131
Short name T682
Test name
Test status
Simulation time 63373380 ps
CPU time 1.52 seconds
Started Feb 09 01:53:43 PM UTC 25
Finished Feb 09 01:53:45 PM UTC 25
Peak memory 230312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839160131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 92.edn_genbits.839160131
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/92.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/93.edn_alert.3318868022
Short name T685
Test name
Test status
Simulation time 23418710 ps
CPU time 1.67 seconds
Started Feb 09 01:53:45 PM UTC 25
Finished Feb 09 01:53:48 PM UTC 25
Peak memory 228196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318868022 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 93.edn_alert.3318868022
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/93.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/93.edn_err.1410481395
Short name T177
Test name
Test status
Simulation time 23632953 ps
CPU time 1.56 seconds
Started Feb 09 01:53:45 PM UTC 25
Finished Feb 09 01:53:48 PM UTC 25
Peak memory 236856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410481395 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 93.edn_err.1410481395
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/93.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/93.edn_genbits.1021541212
Short name T686
Test name
Test status
Simulation time 47520922 ps
CPU time 1.78 seconds
Started Feb 09 01:53:45 PM UTC 25
Finished Feb 09 01:53:48 PM UTC 25
Peak memory 228068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021541212 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 93.edn_genbits.1021541212
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/93.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/94.edn_alert.1655271454
Short name T687
Test name
Test status
Simulation time 65909169 ps
CPU time 1.69 seconds
Started Feb 09 01:53:45 PM UTC 25
Finished Feb 09 01:53:48 PM UTC 25
Peak memory 228260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655271454 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 94.edn_alert.1655271454
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/94.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/94.edn_err.1315867372
Short name T689
Test name
Test status
Simulation time 24362515 ps
CPU time 1.57 seconds
Started Feb 09 01:53:46 PM UTC 25
Finished Feb 09 01:53:49 PM UTC 25
Peak memory 236856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315867372 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 94.edn_err.1315867372
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/94.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/94.edn_genbits.2826781026
Short name T688
Test name
Test status
Simulation time 92642120 ps
CPU time 1.88 seconds
Started Feb 09 01:53:45 PM UTC 25
Finished Feb 09 01:53:48 PM UTC 25
Peak memory 226216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826781026 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 94.edn_genbits.2826781026
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/94.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/95.edn_alert.4155942595
Short name T324
Test name
Test status
Simulation time 34125428 ps
CPU time 1.67 seconds
Started Feb 09 01:53:46 PM UTC 25
Finished Feb 09 01:53:49 PM UTC 25
Peak memory 228320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155942595 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 95.edn_alert.4155942595
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/95.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/95.edn_err.2057072346
Short name T227
Test name
Test status
Simulation time 26001818 ps
CPU time 1.48 seconds
Started Feb 09 01:53:47 PM UTC 25
Finished Feb 09 01:53:50 PM UTC 25
Peak memory 230304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057072346 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 95.edn_err.2057072346
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/95.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/95.edn_genbits.1118386134
Short name T690
Test name
Test status
Simulation time 28414410 ps
CPU time 1.81 seconds
Started Feb 09 01:53:46 PM UTC 25
Finished Feb 09 01:53:49 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118386134 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 95.edn_genbits.1118386134
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/95.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/96.edn_alert.608649929
Short name T258
Test name
Test status
Simulation time 82305388 ps
CPU time 1.62 seconds
Started Feb 09 01:53:48 PM UTC 25
Finished Feb 09 01:53:51 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608649929 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 96.edn_alert.608649929
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/96.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/96.edn_err.3620081685
Short name T150
Test name
Test status
Simulation time 45567364 ps
CPU time 1.5 seconds
Started Feb 09 01:53:49 PM UTC 25
Finished Feb 09 01:53:51 PM UTC 25
Peak memory 230304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620081685 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 96.edn_err.3620081685
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/96.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/96.edn_genbits.489054229
Short name T260
Test name
Test status
Simulation time 44578639 ps
CPU time 2.7 seconds
Started Feb 09 01:53:48 PM UTC 25
Finished Feb 09 01:53:52 PM UTC 25
Peak memory 229268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489054229 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 96.edn_genbits.489054229
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/96.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/97.edn_alert.1701923341
Short name T262
Test name
Test status
Simulation time 42665532 ps
CPU time 1.73 seconds
Started Feb 09 01:53:50 PM UTC 25
Finished Feb 09 01:53:52 PM UTC 25
Peak memory 228256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701923341 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 97.edn_alert.1701923341
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/97.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/97.edn_err.3194136650
Short name T261
Test name
Test status
Simulation time 21182840 ps
CPU time 1.67 seconds
Started Feb 09 01:53:50 PM UTC 25
Finished Feb 09 01:53:52 PM UTC 25
Peak memory 230288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194136650 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 97.edn_err.3194136650
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/97.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/97.edn_genbits.2776226465
Short name T259
Test name
Test status
Simulation time 67985217 ps
CPU time 2.07 seconds
Started Feb 09 01:53:49 PM UTC 25
Finished Feb 09 01:53:52 PM UTC 25
Peak memory 231344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776226465 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 97.edn_genbits.2776226465
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/97.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/98.edn_alert.1217315833
Short name T263
Test name
Test status
Simulation time 163395841 ps
CPU time 1.57 seconds
Started Feb 09 01:53:50 PM UTC 25
Finished Feb 09 01:53:52 PM UTC 25
Peak memory 230368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217315833 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 98.edn_alert.1217315833
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/98.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/98.edn_err.432022655
Short name T265
Test name
Test status
Simulation time 25511125 ps
CPU time 1.63 seconds
Started Feb 09 01:53:51 PM UTC 25
Finished Feb 09 01:53:54 PM UTC 25
Peak memory 244468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432022655 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na
me 98.edn_err.432022655
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/98.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/98.edn_genbits.2063579975
Short name T264
Test name
Test status
Simulation time 80542738 ps
CPU time 1.66 seconds
Started Feb 09 01:53:50 PM UTC 25
Finished Feb 09 01:53:52 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063579975 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 98.edn_genbits.2063579975
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/98.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/99.edn_alert.1212870490
Short name T266
Test name
Test status
Simulation time 37777303 ps
CPU time 1.6 seconds
Started Feb 09 01:53:52 PM UTC 25
Finished Feb 09 01:53:55 PM UTC 25
Peak memory 228320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212870490 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 99.edn_alert.1212870490
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/99.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/99.edn_err.4216947660
Short name T693
Test name
Test status
Simulation time 66563613 ps
CPU time 1.62 seconds
Started Feb 09 01:53:53 PM UTC 25
Finished Feb 09 01:53:56 PM UTC 25
Peak memory 230508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216947660 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 99.edn_err.4216947660
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/99.edn_err/latest

Test location /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default/99.edn_genbits.3024503434
Short name T267
Test name
Test status
Simulation time 59098768 ps
CPU time 1.96 seconds
Started Feb 09 01:53:52 PM UTC 25
Finished Feb 09 01:53:55 PM UTC 25
Peak memory 228544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024503434 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/edn-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 99.edn_genbits.3024503434
Directory /workspaces/repo/scratch/os_regression/edn-sim-vcs/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%