EDN Lint Results
Thursday April 18 2024 19:02:27 UTC
Branch: os_regression
Tool: ASCENTLINT
| Build Mode |
Flow Infos |
Flow Warnings |
Flow Errors |
Lint Infos |
Lint Warnings |
Lint Errors |
| default |
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211 |
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Messages for Build Mode 'default'
Lint Infos
I FSM_DEFAULT_REQ: prim_diff_decode.sv:158 Next state register 'gen_async.state_d' has no assignment in the default branch of the case statement for this finite state machine New
I NESTED_SUBPROG: tlul_pkg.sv:143 Function 'prim_mubi_pkg::mubi4_test_invalid' is called from within a function New
I VAR_INDEX_WRITE: prim_fifo_sync.sv:124 Variable index expression 'gen_normal_fifo.storage[gen_normal_fifo.fifo_wptr]' encountered New
I CASE_INC: edn_ack_sm.sv:60 Case statement tag not specified for value 'b000000000 and many other values New
I CASE_INC: edn_main_sm.sv:61 Case statement tag not specified for value 'b000000000 and many other values New
I CASE_INC: prim_alert_sender.sv:199 Case statement tag not specified for value 'b111 New
I CASE_INC: prim_diff_decode.sv:115 Case statement tag not specified for value 'b11 New
I CASE_INC: tlul_err.sv:62 Case statement tag not specified for value 'h3 New
I ONE_BIT_VEC: edn_core.sv:86 Declaration range '[BootReqCopies - 1:1]' ([1:1]) of 'boot_req_mode_fo' has a length of one, instance 'edn.u_edn_core' of module 'edn_core' (BootReqCopies=2) New
I ONE_BIT_VEC: edn_reg_top.sv:588 Declaration range '[0:0]' of 'sw_cmd_req_flds_we' has a length of one New
I ONE_BIT_VEC: edn_reg_top.sv:855 Declaration range '[0:0]' of 'reseed_cmd_flds_we' has a length of one New
I ONE_BIT_VEC: edn_reg_top.sv:875 Declaration range '[0:0]' of 'generate_cmd_flds_we' has a length of one New
I ONE_BIT_VEC: edn_reg_top.sv:895 Declaration range '[0:0]' of 'max_num_reqs_between_reseeds_flds_we' has a length of one New
I ONE_BIT_VEC: edn_reg_top.sv:1317 Declaration range '[0:0]' of 'err_code_test_flds_we' has a length of one New
I ONE_BIT_VEC: prim_buf.sv:24 Declaration range '[Width - 1:0]' ([0:0]) of 'in_i' has a length of one, instance 'edn.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[0].gen_bits[0].u_prim_buf' of module 'prim_buf' (Width=1) New
I ONE_BIT_VEC: prim_buf.sv:25 Declaration range '[Width - 1:0]' ([0:0]) of 'out_o' has a length of one, instance 'edn.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[0].gen_bits[0].u_prim_buf' of module 'prim_buf' (Width=1) New
I ONE_BIT_VEC: prim_flop.sv:22 Declaration range '[Width - 1:0]' ([0:0]) of 'ResetValue' has a length of one, instance 'edn.u_reg.u_max_num_reqs_between_reseeds0_qe' of module 'prim_flop' (Width=1) New
I ONE_BIT_VEC: prim_flop.sv:27 Declaration range '[Width - 1:0]' ([0:0]) of 'd_i' has a length of one, instance 'edn.u_reg.u_max_num_reqs_between_reseeds0_qe' of module 'prim_flop' (Width=1) New
I ONE_BIT_VEC: prim_flop.sv:28 Declaration range '[Width - 1:0]' ([0:0]) of 'q_o' has a length of one, instance 'edn.u_reg.u_max_num_reqs_between_reseeds0_qe' of module 'prim_flop' (Width=1) New
I ONE_BIT_VEC: prim_intr_hw.sv:44 Declaration range '[Width - 1:0]' ([0:0]) of 'event_intr_i' has a length of one, instance 'edn.u_edn_core.u_intr_hw_edn_cmd_req_done' of module 'prim_intr_hw' (Width=1) New
I ONE_BIT_VEC: prim_intr_hw.sv:47 Declaration range '[Width - 1:0]' ([0:0]) of 'reg2hw_intr_enable_q_i' has a length of one, instance 'edn.u_edn_core.u_intr_hw_edn_cmd_req_done' of module 'prim_intr_hw' (Width=1) New
I ONE_BIT_VEC: prim_intr_hw.sv:48 Declaration range '[Width - 1:0]' ([0:0]) of 'reg2hw_intr_test_q_i' has a length of one, instance 'edn.u_edn_core.u_intr_hw_edn_cmd_req_done' of module 'prim_intr_hw' (Width=1) New
I ONE_BIT_VEC: prim_intr_hw.sv:50 Declaration range '[Width - 1:0]' ([0:0]) of 'reg2hw_intr_state_q_i' has a length of one, instance 'edn.u_edn_core.u_intr_hw_edn_cmd_req_done' of module 'prim_intr_hw' (Width=1) New
I ONE_BIT_VEC: prim_intr_hw.sv:52 Declaration range '[Width - 1:0]' ([0:0]) of 'hw2reg_intr_state_d_o' has a length of one, instance 'edn.u_edn_core.u_intr_hw_edn_cmd_req_done' of module 'prim_intr_hw' (Width=1) New
I ONE_BIT_VEC: prim_intr_hw.sv:55 Declaration range '[Width - 1:0]' ([0:0]) of 'intr_o' has a length of one, instance 'edn.u_edn_core.u_intr_hw_edn_cmd_req_done' of module 'prim_intr_hw' (Width=1) New
I ONE_BIT_VEC: prim_intr_hw.sv:58 Declaration range '[Width - 1:0]' ([0:0]) of 'status' has a length of one, instance 'edn.u_edn_core.u_intr_hw_edn_cmd_req_done' of module 'prim_intr_hw' (Width=1) New
I ONE_BIT_VEC: prim_intr_hw.sv:61 Declaration range '[Width - 1:0]' ([0:0]) of 'g_intr_event.new_event' has a length of one, instance 'edn.u_edn_core.u_intr_hw_edn_cmd_req_done' of module 'prim_intr_hw' (Width=1) New
I ONE_BIT_VEC: prim_packer_fifo.sv:64 Declaration range '[DepthW:0]' ([0:0]) of 'depth_o' has a length of one, instance 'edn.u_edn_core.u_prim_packer_fifo_cs' of module 'prim_packer_fifo' (DepthW=0 ('$clog2(MaxW / MinW)'),InW=128,MaxW=128 ('(InW > OutW) ? InW : OutW'),MinW=128 ('(InW < OutW) ? InW : OutW'),OutW=128) New
I ONE_BIT_VEC: prim_packer_fifo.sv:68 Declaration range '[DepthW:0]' ([0:0]) of 'FullDepth' has a length of one, instance 'edn.u_edn_core.u_prim_packer_fifo_cs' of module 'prim_packer_fifo' (DepthW=0 ('$clog2(MaxW / MinW)'),InW=128,MaxW=128 ('(InW > OutW) ? InW : OutW'),MinW=128 ('(InW < OutW) ? InW : OutW'),OutW=128) New
I ONE_BIT_VEC: prim_packer_fifo.sv:69 Declaration range '[DepthW:0]' ([0:0]) of 'DepthOne' has a length of one, instance 'edn.u_edn_core.u_prim_packer_fifo_cs' of module 'prim_packer_fifo' (DepthW=0 ('$clog2(MaxW / MinW)'),InW=128,MaxW=128 ('(InW > OutW) ? InW : OutW'),MinW=128 ('(InW < OutW) ? InW : OutW'),OutW=128) New
I ONE_BIT_VEC: prim_packer_fifo.sv:77 Declaration range '[DepthW:0]' ([0:0]) of 'depth_q' has a length of one, instance 'edn.u_edn_core.u_prim_packer_fifo_cs' of module 'prim_packer_fifo' (DepthW=0 ('$clog2(MaxW / MinW)'),InW=128,MaxW=128 ('(InW > OutW) ? InW : OutW'),MinW=128 ('(InW < OutW) ? InW : OutW'),OutW=128) New
I ONE_BIT_VEC: prim_packer_fifo.sv:122 Declaration range '[DepthW:0]' ([0:0]) of 'gen_unpack_mode.ptr_q' has a length of one, instance 'edn.u_edn_core.u_prim_packer_fifo_cs' of module 'prim_packer_fifo' (DepthW=0 ('$clog2(MaxW / MinW)'),InW=128,MaxW=128 ('(InW > OutW) ? InW : OutW'),MinW=128 ('(InW < OutW) ? InW : OutW'),OutW=128) New
I ONE_BIT_VEC: prim_packer_fifo.sv:123 Declaration range '[DepthW:0]' ([0:0]) of 'gen_unpack_mode.lsb_is_one' has a length of one, instance 'edn.u_edn_core.u_prim_packer_fifo_cs' of module 'prim_packer_fifo' (DepthW=0 ('$clog2(MaxW / MinW)'),InW=128,MaxW=128 ('(InW > OutW) ? InW : OutW'),MinW=128 ('(InW < OutW) ? InW : OutW'),OutW=128) New
I ONE_BIT_VEC: prim_packer_fifo.sv:124 Declaration range '[DepthW:0]' ([0:0]) of 'gen_unpack_mode.max_value' has a length of one, instance 'edn.u_edn_core.u_prim_packer_fifo_cs' of module 'prim_packer_fifo' (DepthW=0 ('$clog2(MaxW / MinW)'),InW=128,MaxW=128 ('(InW > OutW) ? InW : OutW'),MinW=128 ('(InW < OutW) ? InW : OutW'),OutW=128) New
I ONE_BIT_VEC: prim_arbiter_ppc.sv:44 Declaration range '[DW - 1:0]' ([0:0]) of 'data_i' has a length of one, instance 'edn.u_edn_core.u_prim_arbiter_ppc_packer_arb' of module 'prim_arbiter_ppc' (DW=1) New
I ONE_BIT_VEC: prim_arbiter_ppc.sv:49 Declaration range '[DW - 1:0]' ([0:0]) of 'data_o' has a length of one, instance 'edn.u_edn_core.u_prim_arbiter_ppc_packer_arb' of module 'prim_arbiter_ppc' (DW=1) New
I ONE_BIT_VEC: prim_arbiter_ppc.sv:119 Declaration range '[DW - 1:0]' ([0:0]) of 'gen_normal_case.gen_nodatapath.unused_data' has a length of one, instance 'edn.u_edn_core.u_prim_arbiter_ppc_packer_arb' of module 'prim_arbiter_ppc' (DW=1) New
I ONE_BIT_VEC: prim_edge_detector.sv:10 Declaration range '[Width - 1:0]' ([0:0]) of 'ResetValue' has a length of one, instance 'edn.u_edn_core.u_prim_edge_detector_recov_alert' of module 'prim_edge_detector' (Width=1) New
I ONE_BIT_VEC: prim_edge_detector.sv:21 Declaration range '[Width - 1:0]' ([0:0]) of 'd_i' has a length of one, instance 'edn.u_edn_core.u_prim_edge_detector_recov_alert' of module 'prim_edge_detector' (Width=1) New
I ONE_BIT_VEC: prim_edge_detector.sv:22 Declaration range '[Width - 1:0]' ([0:0]) of 'q_sync_o' has a length of one, instance 'edn.u_edn_core.u_prim_edge_detector_recov_alert' of module 'prim_edge_detector' (Width=1) New
I ONE_BIT_VEC: prim_edge_detector.sv:24 Declaration range '[Width - 1:0]' ([0:0]) of 'q_posedge_pulse_o' has a length of one, instance 'edn.u_edn_core.u_prim_edge_detector_recov_alert' of module 'prim_edge_detector' (Width=1) New
I ONE_BIT_VEC: prim_edge_detector.sv:25 Declaration range '[Width - 1:0]' ([0:0]) of 'q_negedge_pulse_o' has a length of one, instance 'edn.u_edn_core.u_prim_edge_detector_recov_alert' of module 'prim_edge_detector' (Width=1) New
I ONE_BIT_VEC: prim_edge_detector.sv:28 Declaration range '[Width - 1:0]' ([0:0]) of 'q_sync_d' has a length of one, instance 'edn.u_edn_core.u_prim_edge_detector_recov_alert' of module 'prim_edge_detector' (Width=1) New
I ONE_BIT_VEC: prim_flop_2sync.sv:11 Declaration range '[Width - 1:0]' ([0:0]) of 'ResetValue' has a length of one, instance 'edn.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p' of module 'prim_flop_2sync' (Width=1) New
I ONE_BIT_VEC: prim_flop_2sync.sv:16 Declaration range '[Width - 1:0]' ([0:0]) of 'd_i' has a length of one, instance 'edn.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p' of module 'prim_flop_2sync' (Width=1) New
I ONE_BIT_VEC: prim_flop_2sync.sv:17 Declaration range '[Width - 1:0]' ([0:0]) of 'q_o' has a length of one, instance 'edn.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p' of module 'prim_flop_2sync' (Width=1) New
I ONE_BIT_VEC: prim_flop_2sync.sv:20 Declaration range '[Width - 1:0]' ([0:0]) of 'd_o' has a length of one, instance 'edn.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p' of module 'prim_flop_2sync' (Width=1) New
I ONE_BIT_VEC: prim_flop_2sync.sv:21 Declaration range '[Width - 1:0]' ([0:0]) of 'intq' has a length of one, instance 'edn.gen_alert_tx[0].u_prim_alert_sender.u_decode_ping.gen_async.i_sync_p' of module 'prim_flop_2sync' (Width=1) New
I ONE_BIT_VEC: prim_generic_buf.sv:10 Declaration range '[Width - 1:0]' ([0:0]) of 'in_i' has a length of one, instance 'edn.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic' of module 'prim_generic_buf' (Width=1) New
I ONE_BIT_VEC: prim_generic_buf.sv:11 Declaration range '[Width - 1:0]' ([0:0]) of 'out_o' has a length of one, instance 'edn.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic' of module 'prim_generic_buf' (Width=1) New
I ONE_BIT_VEC: prim_generic_buf.sv:14 Declaration range '[Width - 1:0]' ([0:0]) of 'inv' has a length of one, instance 'edn.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic' of module 'prim_generic_buf' (Width=1) New
I ONE_BIT_VEC: prim_generic_flop.sv:9 Declaration range '[Width - 1:0]' ([0:0]) of 'ResetValue' has a length of one, instance 'edn.u_reg.u_max_num_reqs_between_reseeds0_qe.gen_generic.u_impl_generic' of module 'prim_generic_flop' (Width=1) New
I ONE_BIT_VEC: prim_generic_flop.sv:13 Declaration range '[Width - 1:0]' ([0:0]) of 'd_i' has a length of one, instance 'edn.u_reg.u_max_num_reqs_between_reseeds0_qe.gen_generic.u_impl_generic' of module 'prim_generic_flop' (Width=1) New
I ONE_BIT_VEC: prim_generic_flop.sv:14 Declaration range '[Width - 1:0]' ([0:0]) of 'q_o' has a length of one, instance 'edn.u_reg.u_max_num_reqs_between_reseeds0_qe.gen_generic.u_impl_generic' of module 'prim_generic_flop' (Width=1) New
I ONE_BIT_VEC: prim_sec_anchor_buf.sv:10 Declaration range '[Width - 1:0]' ([0:0]) of 'in_i' has a length of one, instance 'edn.gen_alert_tx[0].u_prim_alert_sender.u_prim_buf_in_req' of module 'prim_sec_anchor_buf' (Width=1) New
I ONE_BIT_VEC: prim_sec_anchor_buf.sv:11 Declaration range '[Width - 1:0]' ([0:0]) of 'out_o' has a length of one, instance 'edn.gen_alert_tx[0].u_prim_alert_sender.u_prim_buf_in_req' of module 'prim_sec_anchor_buf' (Width=1) New
I ONE_BIT_VEC: prim_subreg.sv:12 Declaration range '[DW - 1:0]' ([0:0]) of 'RESVAL' has a length of one, instance 'edn.u_reg.u_intr_state_edn_cmd_req_done' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg.sv:21 Declaration range '[DW - 1:0]' ([0:0]) of 'wd' has a length of one, instance 'edn.u_reg.u_intr_state_edn_cmd_req_done' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg.sv:25 Declaration range '[DW - 1:0]' ([0:0]) of 'd' has a length of one, instance 'edn.u_reg.u_intr_state_edn_cmd_req_done' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg.sv:29 Declaration range '[DW - 1:0]' ([0:0]) of 'q' has a length of one, instance 'edn.u_reg.u_intr_state_edn_cmd_req_done' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg.sv:34 Declaration range '[DW - 1:0]' ([0:0]) of 'ds' has a length of one, instance 'edn.u_reg.u_intr_state_edn_cmd_req_done' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg.sv:35 Declaration range '[DW - 1:0]' ([0:0]) of 'qs' has a length of one, instance 'edn.u_reg.u_intr_state_edn_cmd_req_done' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg.sv:39 Declaration range '[DW - 1:0]' ([0:0]) of 'wr_data' has a length of one, instance 'edn.u_reg.u_intr_state_edn_cmd_req_done' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg_arb.sv:17 Declaration range '[DW - 1:0]' ([0:0]) of 'wd' has a length of one, instance 'edn.u_reg.u_intr_state_edn_cmd_req_done.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1) New
I ONE_BIT_VEC: prim_subreg_arb.sv:21 Declaration range '[DW - 1:0]' ([0:0]) of 'd' has a length of one, instance 'edn.u_reg.u_intr_state_edn_cmd_req_done.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1) New
I ONE_BIT_VEC: prim_subreg_arb.sv:24 Declaration range '[DW - 1:0]' ([0:0]) of 'q' has a length of one, instance 'edn.u_reg.u_intr_state_edn_cmd_req_done.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1) New
I ONE_BIT_VEC: prim_subreg_arb.sv:28 Declaration range '[DW - 1:0]' ([0:0]) of 'wr_data' has a length of one, instance 'edn.u_reg.u_intr_state_edn_cmd_req_done.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1) New
I ONE_BIT_VEC: prim_subreg_arb.sv:36 Declaration range '[DW - 1:0]' ([0:0]) of 'gen_w.unused_q' has a length of one, instance 'edn.u_reg.u_intr_enable_edn_cmd_req_done.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1) New
I ONE_BIT_VEC: prim_subreg_arb.sv:47 Declaration range '[DW - 1:0]' ([0:0]) of 'gen_ro.unused_wd' has a length of one, instance 'edn.u_reg.u_sw_cmd_sts_cmd_reg_rdy.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1) New
I ONE_BIT_VEC: prim_subreg_arb.sv:48 Declaration range '[DW - 1:0]' ([0:0]) of 'gen_ro.unused_q' has a length of one, instance 'edn.u_reg.u_sw_cmd_sts_cmd_reg_rdy.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1) New
I ONE_BIT_VEC: prim_subreg_ext.sv:12 Declaration range '[DW - 1:0]' ([0:0]) of 'wd' has a length of one, instance 'edn.u_reg.u_intr_test_edn_cmd_req_done' of module 'prim_subreg_ext' (DW=1) New
I ONE_BIT_VEC: prim_subreg_ext.sv:14 Declaration range '[DW - 1:0]' ([0:0]) of 'd' has a length of one, instance 'edn.u_reg.u_intr_test_edn_cmd_req_done' of module 'prim_subreg_ext' (DW=1) New
I ONE_BIT_VEC: prim_subreg_ext.sv:19 Declaration range '[DW - 1:0]' ([0:0]) of 'q' has a length of one, instance 'edn.u_reg.u_intr_test_edn_cmd_req_done' of module 'prim_subreg_ext' (DW=1) New
I ONE_BIT_VEC: prim_subreg_ext.sv:20 Declaration range '[DW - 1:0]' ([0:0]) of 'ds' has a length of one, instance 'edn.u_reg.u_intr_test_edn_cmd_req_done' of module 'prim_subreg_ext' (DW=1) New
I ONE_BIT_VEC: prim_subreg_ext.sv:21 Declaration range '[DW - 1:0]' ([0:0]) of 'qs' has a length of one, instance 'edn.u_reg.u_intr_test_edn_cmd_req_done' of module 'prim_subreg_ext' (DW=1) New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'd_sink' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_d2h_t' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_i' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_o' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_o_pre' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_reg_d2h' has a length of one New
I EXPLICIT_BITLEN: edn_core.sv:752 Bit length not specified for constant '1' New
I EXPLICIT_BITLEN: edn_core.sv:772 Bit length not specified for constant '1' New
I EXPLICIT_BITLEN: edn_core.sv:777 Bit length not specified for constant '1' New
I EXPLICIT_BITLEN: prim_fifo_sync_cnt.sv:51 Bit length not specified for constant '1' New
I EXPLICIT_BITLEN: prim_fifo_sync_cnt.sv:52 Bit length not specified for constant '1' New
I EXPLICIT_BITLEN: prim_util_pkg.sv:85 Bit length not specified for constant '1' New
I EXPLICIT_BITLEN: tlul_err.sv:69 Bit length not specified for constant "'h1" New
I EXPLICIT_BITLEN: tlul_err.sv:77 Bit length not specified for constant "'h2" New
I MIN_NAME_LEN: edn_reg_pkg.sv:25 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: edn_reg_pkg.sv:28 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: edn_reg_pkg.sv:34 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: edn_reg_pkg.sv:37 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: edn_reg_pkg.sv:43 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: edn_reg_pkg.sv:47 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: edn_reg_pkg.sv:54 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: edn_reg_pkg.sv:58 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: edn_reg_pkg.sv:65 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: edn_reg_pkg.sv:68 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: edn_reg_pkg.sv:71 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: edn_reg_pkg.sv:74 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: edn_reg_pkg.sv:79 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: edn_reg_pkg.sv:83 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: edn_reg_pkg.sv:87 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: edn_reg_pkg.sv:92 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: edn_reg_pkg.sv:97 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: edn_reg_pkg.sv:102 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: edn_reg_pkg.sv:107 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: edn_reg_pkg.sv:113 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: edn_reg_pkg.sv:117 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: edn_reg_pkg.sv:124 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: edn_reg_pkg.sv:128 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: edn_reg_pkg.sv:132 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: edn_reg_pkg.sv:136 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: edn_reg_pkg.sv:143 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: edn_reg_pkg.sv:147 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: edn_reg_pkg.sv:151 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: edn_reg_pkg.sv:155 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: edn_reg_pkg.sv:159 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: edn_reg_pkg.sv:166 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: edn_reg_pkg.sv:170 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: edn_reg_pkg.sv:174 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: edn_reg_pkg.sv:178 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: edn_reg_pkg.sv:182 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: edn_reg_pkg.sv:186 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: edn_reg_pkg.sv:193 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: edn_reg_pkg.sv:197 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: edn_reg_pkg.sv:201 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: edn_reg_pkg.sv:205 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: edn_reg_pkg.sv:209 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: edn_reg_pkg.sv:213 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: edn_reg_pkg.sv:217 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: edn_reg_pkg.sv:221 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: edn_reg_pkg.sv:227 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_arbiter_ppc.sv:28 Name 'N' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_arbiter_ppc.sv:83 Name 'i' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_arbiter_ppc.sv:110 Name 'i' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_arbiter_ppc.sv:125 Name 'i' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:80 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:80 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:85 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:106 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:106 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:111 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:124 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:124 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:131 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:131 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:212 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:212 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:217 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:238 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:238 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:243 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:256 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:256 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:263 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:263 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:344 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:344 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:349 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:370 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:370 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:375 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:388 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:388 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:395 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:395 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:476 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:476 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:481 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:502 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:502 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:507 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:520 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:520 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:527 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:527 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_subreg.sv:25 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_subreg.sv:29 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_subreg_arb.sv:21 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_subreg_arb.sv:24 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_subreg_ext.sv:14 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_subreg_ext.sv:19 Name 'q' is shorter than minimum length 2 New
I ZERO_BASED: edn_core.sv:84 Declaration range '[EdnEnableCopies - 1:FatalErr]' ([19:1]) of 'edn_enable_fo' is not zero-based New
I ZERO_BASED: edn_core.sv:85 Declaration range '[FifoRstCopies - 1:1]' ([3:1]) of 'cmd_fifo_rst_fo' is not zero-based New
I ZERO_BASED: edn_core.sv:86 Declaration range '[BootReqCopies - 1:1]' ([1:1]) of 'boot_req_mode_fo' is not zero-based New
I CONST_OUTPUT: edn_core.sv:332 Output 'hw2reg.err_code.sfifo_rescmd_err.d' is driven by constant one in module 'edn_core' (NumEndPoints=8) New
I CONST_OUTPUT: edn_core.sv:335 Output 'hw2reg.err_code.sfifo_gencmd_err.d' is driven by constant one in module 'edn_core' (NumEndPoints=8) New
I CONST_OUTPUT: edn_core.sv:338 Output 'hw2reg.err_code.edn_ack_sm_err.d' is driven by constant one in module 'edn_core' (NumEndPoints=8) New
I CONST_OUTPUT: edn_core.sv:341 Output 'hw2reg.err_code.edn_main_sm_err.d' is driven by constant one in module 'edn_core' (NumEndPoints=8) New
I CONST_OUTPUT: edn_core.sv:344 Output 'hw2reg.err_code.edn_cntr_err.d' is driven by constant one in module 'edn_core' (NumEndPoints=8) New
I CONST_OUTPUT: edn_core.sv:352 Output 'hw2reg.err_code.fifo_write_err.d' is driven by constant one in module 'edn_core' (NumEndPoints=8) New
I CONST_OUTPUT: edn_core.sv:355 Output 'hw2reg.err_code.fifo_read_err.d' is driven by constant one in module 'edn_core' (NumEndPoints=8) New
I CONST_OUTPUT: edn_core.sv:358 Output 'hw2reg.err_code.fifo_state_err.d' is driven by constant one in module 'edn_core' (NumEndPoints=8) New
I CONST_OUTPUT: edn_core.sv:542 Output 'hw2reg.sw_cmd_sts.cmd_rdy.de' is driven by constant one in module 'edn_core' (NumEndPoints=8) New
I CONST_OUTPUT: edn_core.sv:557 Output 'hw2reg.sw_cmd_sts.cmd_reg_rdy.de' is driven by constant one in module 'edn_core' (NumEndPoints=8) New
I CONST_OUTPUT: edn_core.sv:568 Output 'hw2reg.sw_cmd_sts.cmd_sts.de' is driven by constant one in module 'edn_core' (NumEndPoints=8) New
I CONST_OUTPUT: edn_core.sv:576 Output 'hw2reg.sw_cmd_sts.cmd_ack.de' is driven by constant one in module 'edn_core' (NumEndPoints=8) New
I CONST_OUTPUT: edn_core.sv:588 Output 'hw2reg.hw_cmd_sts.boot_mode.de' is driven by constant one in module 'edn_core' (NumEndPoints=8) New
I CONST_OUTPUT: edn_core.sv:594 Output 'hw2reg.hw_cmd_sts.auto_mode.de' is driven by constant one in module 'edn_core' (NumEndPoints=8) New
I CONST_OUTPUT: edn_core.sv:601 Output 'hw2reg.hw_cmd_sts.cmd_sts.de' is driven by constant one in module 'edn_core' (NumEndPoints=8) New
I CONST_OUTPUT: edn_core.sv:611 Output 'hw2reg.hw_cmd_sts.cmd_ack.de' is driven by constant one in module 'edn_core' (NumEndPoints=8) New
I CONST_OUTPUT: edn_core.sv:621 Output 'hw2reg.hw_cmd_sts.cmd_type.de' is driven by constant one in module 'edn_core' (NumEndPoints=8) New
I CONST_OUTPUT: edn_core.sv:939 Output 'hw2reg.main_sm_state.de' is driven by constant one in module 'edn_core' (NumEndPoints=8) New
I CONST_OUTPUT: prim_arbiter_ppc.sv:117 Output 'data_o' is driven by constant one in module 'prim_arbiter_ppc' (DW=1,EnDataPort=0) New
I CONST_OUTPUT: prim_fifo_sync.sv:98 Output 'err_o' is driven by constant zero by port 'gen_normal_fifo.u_fifo_cnt.err_o' in module 'prim_fifo_sync' (Width=32'h20,Pass=0,Depth=32'hd) New
I CONST_OUTPUT: prim_fifo_sync_cnt.sv:136 Output 'err_o' is driven by constant zero in module 'prim_fifo_sync_cnt' (Depth=32'hd) New
I CONST_OUTPUT: tlul_adapter_reg.sv:91 Output 'addr_o[1:0]' is driven by constant zeros in module 'tlul_adapter_reg' (RegAw=7) New
I CONST_OUTPUT: tlul_adapter_reg.sv:195 Output 'intg_error_o' is driven by constant zero in module 'tlul_adapter_reg' (RegAw=7) New
Past Results