e3fb01b5e
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | entropy_src_smoke | 4.000s | 21.797us | 50 | 50 | 100.00 |
V1 | csr_hw_reset | entropy_src_csr_hw_reset | 5.000s | 70.107us | 5 | 5 | 100.00 |
V1 | csr_rw | entropy_src_csr_rw | 4.000s | 106.727us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | entropy_src_csr_bit_bash | 16.000s | 790.487us | 5 | 5 | 100.00 |
V1 | csr_aliasing | entropy_src_csr_aliasing | 8.000s | 204.360us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | entropy_src_csr_mem_rw_with_rand_reset | 5.000s | 326.207us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | entropy_src_csr_rw | 4.000s | 106.727us | 20 | 20 | 100.00 |
entropy_src_csr_aliasing | 8.000s | 204.360us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 105 | 105 | 100.00 | |||
V2 | firmware | entropy_src_smoke | 4.000s | 21.797us | 50 | 50 | 100.00 |
entropy_src_rng | 10.733m | 10.015ms | 300 | 300 | 100.00 | ||
entropy_src_fw_ov | 2.033m | 5.024ms | 296 | 300 | 98.67 | ||
V2 | firmware_mode | entropy_src_fw_ov | 2.033m | 5.024ms | 296 | 300 | 98.67 |
V2 | rng_mode | entropy_src_rng | 10.733m | 10.015ms | 300 | 300 | 100.00 |
V2 | rng_max_rate | entropy_src_rng_max_rate | 11.033m | 10.015ms | 400 | 400 | 100.00 |
V2 | health_checks | entropy_src_rng | 10.733m | 10.015ms | 300 | 300 | 100.00 |
V2 | conditioning | entropy_src_rng | 10.733m | 10.015ms | 300 | 300 | 100.00 |
V2 | interrupts | entropy_src_rng | 10.733m | 10.015ms | 300 | 300 | 100.00 |
V2 | alerts | entropy_src_rng | 10.733m | 10.015ms | 300 | 300 | 100.00 |
entropy_src_functional_alerts | 5.000s | 56.727us | 50 | 50 | 100.00 | ||
V2 | stress_all | entropy_src_stress_all | 10.000s | 471.075us | 50 | 50 | 100.00 |
V2 | functional_errors | entropy_src_functional_errors | 5.000s | 55.304us | 1000 | 1000 | 100.00 |
V2 | intr_test | entropy_src_intr_test | 5.000s | 110.873us | 50 | 50 | 100.00 |
V2 | alert_test | entropy_src_alert_test | 4.000s | 27.083us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | entropy_src_tl_errors | 8.000s | 1.333ms | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | entropy_src_tl_errors | 8.000s | 1.333ms | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | entropy_src_csr_hw_reset | 5.000s | 70.107us | 5 | 5 | 100.00 |
entropy_src_csr_rw | 4.000s | 106.727us | 20 | 20 | 100.00 | ||
entropy_src_csr_aliasing | 8.000s | 204.360us | 5 | 5 | 100.00 | ||
entropy_src_same_csr_outstanding | 5.000s | 277.440us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | entropy_src_csr_hw_reset | 5.000s | 70.107us | 5 | 5 | 100.00 |
entropy_src_csr_rw | 4.000s | 106.727us | 20 | 20 | 100.00 | ||
entropy_src_csr_aliasing | 8.000s | 204.360us | 5 | 5 | 100.00 | ||
entropy_src_same_csr_outstanding | 5.000s | 277.440us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 2236 | 2240 | 99.82 | |||
V2S | tl_intg_err | entropy_src_sec_cm | 4.000s | 276.841us | 5 | 5 | 100.00 |
entropy_src_tl_intg_err | 7.000s | 1.300ms | 20 | 20 | 100.00 | ||
V2S | sec_cm_config_regwen | entropy_src_rng | 10.733m | 10.015ms | 300 | 300 | 100.00 |
entropy_src_cfg_regwen | 4.000s | 29.914us | 50 | 50 | 100.00 | ||
V2S | sec_cm_config_mubi | entropy_src_rng | 10.733m | 10.015ms | 300 | 300 | 100.00 |
V2S | sec_cm_config_redun | entropy_src_rng | 10.733m | 10.015ms | 300 | 300 | 100.00 |
V2S | sec_cm_intersig_mubi | entropy_src_rng | 10.733m | 10.015ms | 300 | 300 | 100.00 |
entropy_src_fw_ov | 2.033m | 5.024ms | 296 | 300 | 98.67 | ||
V2S | sec_cm_main_sm_fsm_sparse | entropy_src_functional_errors | 5.000s | 55.304us | 1000 | 1000 | 100.00 |
entropy_src_sec_cm | 4.000s | 276.841us | 5 | 5 | 100.00 | ||
V2S | sec_cm_ack_sm_fsm_sparse | entropy_src_functional_errors | 5.000s | 55.304us | 1000 | 1000 | 100.00 |
entropy_src_sec_cm | 4.000s | 276.841us | 5 | 5 | 100.00 | ||
V2S | sec_cm_rng_bkgn_chk | entropy_src_rng | 10.733m | 10.015ms | 300 | 300 | 100.00 |
V2S | sec_cm_ctr_redun | entropy_src_functional_errors | 5.000s | 55.304us | 1000 | 1000 | 100.00 |
entropy_src_sec_cm | 4.000s | 276.841us | 5 | 5 | 100.00 | ||
V2S | sec_cm_ctr_local_esc | entropy_src_functional_errors | 5.000s | 55.304us | 1000 | 1000 | 100.00 |
V2S | sec_cm_esfinal_rdata_bus_consistency | entropy_src_functional_alerts | 5.000s | 56.727us | 50 | 50 | 100.00 |
V2S | sec_cm_tile_link_bus_integrity | entropy_src_tl_intg_err | 7.000s | 1.300ms | 20 | 20 | 100.00 |
V2S | TOTAL | 75 | 75 | 100.00 | |||
V3 | external_health_tests | entropy_src_rng_with_xht_rsps | 4.817m | 10.015ms | 50 | 50 | 100.00 |
V3 | stress_all_with_rand_reset | entropy_src_stress_all_with_rand_reset | 0 | 0 | -- | ||
V3 | TOTAL | 50 | 50 | 100.00 | |||
TOTAL | 2466 | 2470 | 99.84 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 6 | 6 | 6 | 100.00 |
V2 | 10 | 10 | 9 | 90.00 |
V2S | 3 | 3 | 3 | 100.00 |
V3 | 2 | 1 | 1 | 50.00 |
Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
---|---|---|---|---|---|---|---|---|
98.42 | 99.04 | 97.60 | 99.68 | 96.93 | 99.40 | 87.39 | 91.61 | 96.54 |
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_entropy_src_*/rtl/entropy_src_core.sv,2990): Assertion AtReset_EsbitFifoPushedIntoPosthtFifo_A has failed
has 3 failures:
22.entropy_src_fw_ov.1304573300
Line 421, in log /container/opentitan-public/scratch/os_regression/entropy_src-sim-xcelium/22.entropy_src_fw_ov/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_entropy_src_0.1/rtl/entropy_src_core.sv,2990): (time 399881978 PS) Assertion tb.dut.u_entropy_src_core.AtReset_EsbitFifoPushedIntoPosthtFifo_A has failed
UVM_ERROR @ 399881978 ps: (entropy_src_core.sv:2990) [ASSERT FAILED] AtReset_EsbitFifoPushedIntoPosthtFifo_A
UVM_INFO @ 399881978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
88.entropy_src_fw_ov.3558081087
Line 467, in log /container/opentitan-public/scratch/os_regression/entropy_src-sim-xcelium/88.entropy_src_fw_ov/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_entropy_src_0.1/rtl/entropy_src_core.sv,2990): (time 1738931745 PS) Assertion tb.dut.u_entropy_src_core.AtReset_EsbitFifoPushedIntoPosthtFifo_A has failed
UVM_ERROR @ 1738931745 ps: (entropy_src_core.sv:2990) [ASSERT FAILED] AtReset_EsbitFifoPushedIntoPosthtFifo_A
UVM_INFO @ 1738931745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_scoreboard.sv:282) scoreboard [scoreboard] alert recov_alert did not trigger max_delay:*
has 1 failures:
177.entropy_src_fw_ov.2535831571
Line 565, in log /container/opentitan-public/scratch/os_regression/entropy_src-sim-xcelium/177.entropy_src_fw_ov/latest/run.log
UVM_ERROR @ 2358256418 ps: (cip_base_scoreboard.sv:282) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_alert did not trigger max_delay:5
UVM_INFO @ 2358256418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---