26b0ee226
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | entropy_src_smoke | 5.000s | 29.876us | 50 | 50 | 100.00 |
V1 | csr_hw_reset | entropy_src_csr_hw_reset | 4.000s | 113.939us | 5 | 5 | 100.00 |
V1 | csr_rw | entropy_src_csr_rw | 4.000s | 97.838us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | entropy_src_csr_bit_bash | 15.000s | 1.067ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | entropy_src_csr_aliasing | 7.000s | 418.078us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | entropy_src_csr_mem_rw_with_rand_reset | 5.000s | 91.329us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | entropy_src_csr_rw | 4.000s | 97.838us | 20 | 20 | 100.00 |
entropy_src_csr_aliasing | 7.000s | 418.078us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 105 | 105 | 100.00 | |||
V2 | firmware | entropy_src_smoke | 5.000s | 29.876us | 50 | 50 | 100.00 |
entropy_src_rng | 10.900m | 10.016ms | 300 | 300 | 100.00 | ||
entropy_src_fw_ov | 2.050m | 5.027ms | 300 | 300 | 100.00 | ||
V2 | firmware_mode | entropy_src_fw_ov | 2.050m | 5.027ms | 300 | 300 | 100.00 |
V2 | rng_mode | entropy_src_rng | 10.900m | 10.016ms | 300 | 300 | 100.00 |
V2 | rng_max_rate | entropy_src_rng_max_rate | 11.933m | 10.016ms | 398 | 400 | 99.50 |
V2 | health_checks | entropy_src_rng | 10.900m | 10.016ms | 300 | 300 | 100.00 |
V2 | conditioning | entropy_src_rng | 10.900m | 10.016ms | 300 | 300 | 100.00 |
V2 | interrupts | entropy_src_rng | 10.900m | 10.016ms | 300 | 300 | 100.00 |
V2 | alerts | entropy_src_rng | 10.900m | 10.016ms | 300 | 300 | 100.00 |
entropy_src_functional_alerts | 5.000s | 319.929us | 50 | 50 | 100.00 | ||
V2 | stress_all | entropy_src_stress_all | 11.000s | 512.920us | 50 | 50 | 100.00 |
V2 | functional_errors | entropy_src_functional_errors | 5.000s | 162.221us | 1000 | 1000 | 100.00 |
V2 | intr_test | entropy_src_intr_test | 4.000s | 42.186us | 50 | 50 | 100.00 |
V2 | alert_test | entropy_src_alert_test | 4.000s | 105.408us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | entropy_src_tl_errors | 7.000s | 124.624us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | entropy_src_tl_errors | 7.000s | 124.624us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | entropy_src_csr_hw_reset | 4.000s | 113.939us | 5 | 5 | 100.00 |
entropy_src_csr_rw | 4.000s | 97.838us | 20 | 20 | 100.00 | ||
entropy_src_csr_aliasing | 7.000s | 418.078us | 5 | 5 | 100.00 | ||
entropy_src_same_csr_outstanding | 4.000s | 108.180us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | entropy_src_csr_hw_reset | 4.000s | 113.939us | 5 | 5 | 100.00 |
entropy_src_csr_rw | 4.000s | 97.838us | 20 | 20 | 100.00 | ||
entropy_src_csr_aliasing | 7.000s | 418.078us | 5 | 5 | 100.00 | ||
entropy_src_same_csr_outstanding | 4.000s | 108.180us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 2238 | 2240 | 99.91 | |||
V2S | tl_intg_err | entropy_src_sec_cm | 4.000s | 134.552us | 5 | 5 | 100.00 |
entropy_src_tl_intg_err | 7.000s | 829.298us | 20 | 20 | 100.00 | ||
V2S | sec_cm_config_regwen | entropy_src_rng | 10.900m | 10.016ms | 300 | 300 | 100.00 |
entropy_src_cfg_regwen | 4.000s | 16.637us | 50 | 50 | 100.00 | ||
V2S | sec_cm_config_mubi | entropy_src_rng | 10.900m | 10.016ms | 300 | 300 | 100.00 |
V2S | sec_cm_config_redun | entropy_src_rng | 10.900m | 10.016ms | 300 | 300 | 100.00 |
V2S | sec_cm_intersig_mubi | entropy_src_rng | 10.900m | 10.016ms | 300 | 300 | 100.00 |
entropy_src_fw_ov | 2.050m | 5.027ms | 300 | 300 | 100.00 | ||
V2S | sec_cm_main_sm_fsm_sparse | entropy_src_functional_errors | 5.000s | 162.221us | 1000 | 1000 | 100.00 |
entropy_src_sec_cm | 4.000s | 134.552us | 5 | 5 | 100.00 | ||
V2S | sec_cm_ack_sm_fsm_sparse | entropy_src_functional_errors | 5.000s | 162.221us | 1000 | 1000 | 100.00 |
entropy_src_sec_cm | 4.000s | 134.552us | 5 | 5 | 100.00 | ||
V2S | sec_cm_rng_bkgn_chk | entropy_src_rng | 10.900m | 10.016ms | 300 | 300 | 100.00 |
V2S | sec_cm_ctr_redun | entropy_src_functional_errors | 5.000s | 162.221us | 1000 | 1000 | 100.00 |
entropy_src_sec_cm | 4.000s | 134.552us | 5 | 5 | 100.00 | ||
V2S | sec_cm_ctr_local_esc | entropy_src_functional_errors | 5.000s | 162.221us | 1000 | 1000 | 100.00 |
V2S | sec_cm_esfinal_rdata_bus_consistency | entropy_src_functional_alerts | 5.000s | 319.929us | 50 | 50 | 100.00 |
V2S | sec_cm_tile_link_bus_integrity | entropy_src_tl_intg_err | 7.000s | 829.298us | 20 | 20 | 100.00 |
V2S | TOTAL | 75 | 75 | 100.00 | |||
V3 | external_health_tests | entropy_src_rng_with_xht_rsps | 10.433m | 10.014ms | 50 | 50 | 100.00 |
V3 | stress_all_with_rand_reset | entropy_src_stress_all_with_rand_reset | 0 | 0 | -- | ||
V3 | TOTAL | 50 | 50 | 100.00 | |||
TOTAL | 2468 | 2470 | 99.92 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 6 | 6 | 6 | 100.00 |
V2 | 10 | 10 | 9 | 90.00 |
V2S | 3 | 3 | 3 | 100.00 |
V3 | 2 | 1 | 1 | 50.00 |
Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
---|---|---|---|---|---|---|---|---|
98.51 | 99.06 | 97.65 | 99.71 | 96.98 | 99.40 | 88.29 | 91.61 | 96.97 |
UVM_ERROR (entropy_src_scoreboard.sv:1804) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: entropy_src_reg_block.recov_alert_sts
has 1 failures:
126.entropy_src_rng_max_rate.2743047564
Line 647, in log /container/opentitan-public/scratch/os_regression/entropy_src-sim-xcelium/126.entropy_src_rng_max_rate/latest/run.log
UVM_ERROR @ 3296932760 ps: (entropy_src_scoreboard.sv:1804) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4096 [0x1000] vs 0 [0x0]) reg name: entropy_src_reg_block.recov_alert_sts
UVM_INFO @ 3296932760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:282) scoreboard [scoreboard] alert recov_alert did not trigger max_delay:*
has 1 failures:
273.entropy_src_rng_max_rate.253905961
Line 1983, in log /container/opentitan-public/scratch/os_regression/entropy_src-sim-xcelium/273.entropy_src_rng_max_rate/latest/run.log
UVM_ERROR @ 9702926337 ps: (cip_base_scoreboard.sv:282) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_alert did not trigger max_delay:5
UVM_INFO @ 9702926337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---