ENTROPY_SRC Simulation Results

Saturday May 27 2023 07:02:22 UTC

GitHub Revision: c06cc3921

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 2359737659

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 6.000s 23.541us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 3.000s 34.687us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 5.000s 27.138us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 13.000s 528.678us 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 9.000s 281.937us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 4.000s 89.882us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 5.000s 27.138us 20 20 100.00
entropy_src_csr_aliasing 9.000s 281.937us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 6.000s 23.541us 50 50 100.00
entropy_src_rng 10.867m 10.015ms 298 300 99.33
entropy_src_fw_ov 2.050m 5.026ms 299 300 99.67
V2 firmware_mode entropy_src_fw_ov 2.050m 5.026ms 299 300 99.67
V2 rng_mode entropy_src_rng 10.867m 10.015ms 298 300 99.33
V2 rng_max_rate entropy_src_rng_max_rate 11.017m 10.014ms 398 400 99.50
V2 health_checks entropy_src_rng 10.867m 10.015ms 298 300 99.33
V2 conditioning entropy_src_rng 10.867m 10.015ms 298 300 99.33
V2 interrupts entropy_src_rng 10.867m 10.015ms 298 300 99.33
V2 alerts entropy_src_rng 10.867m 10.015ms 298 300 99.33
entropy_src_functional_alerts 5.000s 57.113us 50 50 100.00
V2 stress_all entropy_src_stress_all 10.000s 499.411us 50 50 100.00
V2 functional_errors entropy_src_functional_errors 9.000s 48.219us 1000 1000 100.00
V2 intr_test entropy_src_intr_test 4.000s 31.025us 50 50 100.00
V2 alert_test entropy_src_alert_test 4.000s 57.663us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 8.000s 2.723ms 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 8.000s 2.723ms 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 3.000s 34.687us 5 5 100.00
entropy_src_csr_rw 5.000s 27.138us 20 20 100.00
entropy_src_csr_aliasing 9.000s 281.937us 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 96.551us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 3.000s 34.687us 5 5 100.00
entropy_src_csr_rw 5.000s 27.138us 20 20 100.00
entropy_src_csr_aliasing 9.000s 281.937us 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 96.551us 20 20 100.00
V2 TOTAL 2235 2240 99.78
V2S tl_intg_err entropy_src_sec_cm 4.000s 285.980us 5 5 100.00
entropy_src_tl_intg_err 7.000s 192.193us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 10.867m 10.015ms 298 300 99.33
entropy_src_cfg_regwen 4.000s 22.318us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 10.867m 10.015ms 298 300 99.33
V2S sec_cm_config_redun entropy_src_rng 10.867m 10.015ms 298 300 99.33
V2S sec_cm_intersig_mubi entropy_src_rng 10.867m 10.015ms 298 300 99.33
entropy_src_fw_ov 2.050m 5.026ms 299 300 99.67
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 9.000s 48.219us 1000 1000 100.00
entropy_src_sec_cm 4.000s 285.980us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 9.000s 48.219us 1000 1000 100.00
entropy_src_sec_cm 4.000s 285.980us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 10.867m 10.015ms 298 300 99.33
V2S sec_cm_ctr_redun entropy_src_functional_errors 9.000s 48.219us 1000 1000 100.00
entropy_src_sec_cm 4.000s 285.980us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 9.000s 48.219us 1000 1000 100.00
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 5.000s 57.113us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 7.000s 192.193us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.400m 10.020ms 50 50 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 50 50 100.00
TOTAL 2465 2470 99.80

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 10 10 7 70.00
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.42 99.02 97.54 99.68 96.84 99.40 87.39 91.61 96.68

Failure Buckets

Past Results