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loaded run directory /workspace/cov_merge/merged model files domain : hdl /workspace/cov_merge/merged/icc_4a7c6f08_7db19ebf.ucm ucds files domain : hdl /workspace/cov_merge/merged/icc_4a7c6f08_7db19ebf.ucd loaded refinements /workspace/mnt/repo_top/hw/ip/entropy_src/dv/cov/entropy_src_cnt_out_excl.vRefine /workspace/mnt/repo_top/hw/ip/entropy_src/dv/cov/entropy_src_UNR.vRefine /workspace/mnt/repo_top/hw/ip/entropy_src/dv/cov/entropy_src_extht_exclusions.vRefine /workspace/mnt/repo_top/hw/ip/entropy_src/dv/cov/entropy_src_cnt_err_excl.vRefine /workspace/mnt/repo_top/hw/ip/entropy_src/dv/cov/entropy_src_fifo_in_excl.vRefine ccf files /workspace/mnt/repo_top/hw/dv/tools/xcelium/cover_reg_top.ccf // Copyright lowRISC contributors (OpenTitan project). // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // Include our common coverage CCF. include_ccf ${dv_root}/tools/xcelium/common.ccf /workspace/mnt/repo_top/hw/dv/tools/xcelium/common.ccf // Copyright lowRISC contributors (OpenTitan project). // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // Common coverage commands that apply to all DUTs. // // This coverge config file is provided by Xcelium and is located at: // ${XCELIUM_HOME}/tools/icc/include/all_coverage.ccf // Xcelium recommends including it, since it bundles together the common set of commands that enable // coverage collection on various design elements, that are otherwise turned off by default. We // maintain it locally with minor amends. // Enables expression coverage of various Verilog operators. set_expr_coverable_operators -all -event_or // Enables expression coverage of operators in various conditions and assignments. set_expr_coverable_statements -procassign -event_control -misc // Enables scoring of Verilog modules compiled with -v/-y or -libcell option but continues to // disable the scoring of Verilog modules defined with the 'celldefine compiler directive. set_libcell_scoring // Enables scoring of SystemVerilog continuous assignments, which is by disabled by default. set_assign_scoring // Scores branches together with block coverage. set_branch_scoring // Scores statements within a block. set_statement_scoring // Enables Toggle scoring and reporting of SystemVerilog enumerations and multidimensional static // arrays , vectors, packed union, modport and generate blocks. set_toggle_scoring -sv_enum enable_mda -sv_struct_with_enum -sv_modport -sv_mda 16 -sv_mda_of_struct -sv_generate -sv_packed_union // Enable toggle coverage only on ports. set_toggle_portsonly // Enable scoring of FSM arcs (state transitions). // TODO: re-enable this setting, temp disable due to #12544 // set_fsm_arc_scoring // Include X->1|0 for toggle coverage collection. #10332 set_toggle_includex // For ternary operator in default SOP mode set_expr_scoring -vlog_short_circuit // Only collect code coverage on the *_reg_top instance. deselect_coverage -betfs -module ${DUT_TOP}... select_coverage -befs -module *_reg_top... deselect_coverage -betfs -module prim_onehot_check... deselect_coverage -betfs -module prim_secded_inv_64_57_dec... deselect_coverage -betfs -module prim_secded_inv_39_32_dec... // Black-box DV CDC module. deselect_coverage -betfs -module prim_cdc_rand_delay // csr_assert_fpv is an auto-generated csr read assertion module. So only assertion coverage is // meaningful to collect. deselect_coverage -betf -module *csr_assert_fpv... select_coverage -assert -module *csr_assert_fpv // Only enable assertion coverage deselect_coverage -betf -module *tlul_assert... select_coverage -assert -module *tlul_assert // Include toggle coverage on `prim_alert_sender` because the `alert_test` task under // `cip_base_vseq` drives `alert_test_i` and verifies `alert_rx/tx` handshake in each IP. select_coverage -toggle -module prim_alert_sender select_coverage -toggle -module prim_secded_inv_64_57_dec select_coverage -toggle -module prim_secded_inv_39_32_dec // TODO: The intent below is to only enable coverage on the DUT's TL interfaces (tests using this // ccf file are meant to fully exercise the TL interfaces, but they do not verify the rest of the // functionality of the block). We enable coverage on all DUT ports but exclude ports that do not // contain tl_i or tl_o in the port name using a separate excludefile that supports regexes. select_coverage -toggle -module ${DUT_TOP} set_toggle_excludefile ${dv_root}/tools/xcelium/cover_reg_top_toggle_excl |
Verification Scope: default
Version: IMC: 21.03-s003: (c) Copyright 1995-2021 Cadence Design Systems Inc
Metrics tree View Name: All_Metrics
Block View Name: Block
Expression View Name: Expression
Toggle View Name: Toggle
Statement View Name: Statement
FSM View Name: FSM
Cover group View Name: CoverGroups
Assertion View Name: Assertions
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| Exclusion Rule Type | UNR | Name | State Average Grade | Transition Average Grade | Arc Average Grade | Enclosing Entity | Source Code |
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| Exclusion Rule Type | UNR | Name | Overall Average Grade | Overall Covered | Score | At Least | Source Code |
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