1a84e2dc2| Milestone | Name | Tests | Passing | Total | Pass Rate |
|---|---|---|---|---|---|
| V1 | smoke | flash_ctrl_smoke | 5 | 5 | 100.00 |
| V1 | csr_hw_reset | flash_ctrl_csr_hw_reset | 5 | 5 | 100.00 |
| V1 | csr_rw | flash_ctrl_csr_rw | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | flash_ctrl_csr_bit_bash | 5 | 5 | 100.00 |
| V1 | csr_aliasing | flash_ctrl_csr_aliasing | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | flash_ctrl_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 |
| V1 | mem_walk | flash_ctrl_mem_walk | 5 | 5 | 100.00 |
| V1 | mem_partial_access | flash_ctrl_mem_partial_access | 5 | 5 | 100.00 |
| V1 | TOTAL | 50 | 70 | 71.43 | |
| V2 | backpressure | backpressure | 0 | 0 | -- |
| V2 | all_partitions | flash_ctrl_rand_ops | 50 | 50 | 100.00 |
| V2 | host_read_check | host_read_check | 0 | 0 | -- |
| V2 | host_illegal_access | host_illegal_access | 0 | 0 | -- |
| V2 | host_outstanding_access | host_outstanding_access | 0 | 0 | -- |
| V2 | intr_enabled | intr_enabled | 0 | 0 | -- |
| V2 | host_ctrl_arb | host_ctrl_arb | 0 | 0 | -- |
| V2 | host_read_collide | host_read_collide | 0 | 0 | -- |
| V2 | en_mp_regions | en_mp_regions | 0 | 0 | -- |
| V2 | redundant_pages | redundant_pages | 0 | 0 | -- |
| V2 | lc_ctrl_if | lc_ctrl_if | 0 | 0 | -- |
| V2 | key_mgr_if | key_mgr_if | 0 | 0 | -- |
| V2 | scramble | scramble | 0 | 0 | -- |
| V2 | ecc | ecc | 0 | 0 | -- |
| V2 | read_ecc_metadata | read_ecc_metadata | 0 | 0 | -- |
| V2 | error | error | 0 | 0 | -- |
| V2 | flash_macro_timing | flash_macro_timing | 0 | 0 | -- |
| V2 | stress_all | flash_ctrl_stress_all | 0 | 50 | 0.00 |
| V2 | flash_init | flash_init | 0 | 0 | -- |
| V2 | tlul_to_vendor | tlul_to_vendor | 0 | 0 | -- |
| V2 | alert_test | flash_ctrl_alert_test | 50 | 50 | 100.00 |
| V2 | intr_test | flash_ctrl_intr_test | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | flash_ctrl_tl_errors | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | flash_ctrl_tl_errors | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | flash_ctrl_csr_hw_reset | 5 | 5 | 100.00 |
| flash_ctrl_csr_rw | 20 | 20 | 100.00 | ||
| flash_ctrl_csr_aliasing | 5 | 5 | 100.00 | ||
| flash_ctrl_same_csr_outstanding | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | flash_ctrl_csr_hw_reset | 5 | 5 | 100.00 |
| flash_ctrl_csr_rw | 20 | 20 | 100.00 | ||
| flash_ctrl_csr_aliasing | 5 | 5 | 100.00 | ||
| flash_ctrl_same_csr_outstanding | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 190 | 240 | 79.17 | |
| V2S | TOTAL | 0 | 0 | -- | |
| V3 | tl_intg_err | flash_ctrl_tl_intg_err | 0 | 20 | 0.00 |
| V3 | stress_all_with_rand_reset | flash_ctrl_stress_all_with_rand_reset | 0 | 50 | 0.00 |
| V3 | TOTAL | 0 | 70 | 0.00 | |
| TOTAL | 240 | 380 | 63.16 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 24 | 6 | 5 | 20.83 |
| V3 | 2 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 64.09 | 96.09 | 84.11 | 17.70 | 33.99 | 94.66 | 85.84 | 36.28 |
UVM_WARNING [BDTYP] Cannot create an object of type 'flash_ctrl_stress_all_vseq' because it is not registered with the factory. has 100 failures:
0.flash_ctrl_stress_all.789188810
Line 37, in log /usr/local/google/home/chencindy/nightly_openTitan/master/flash_ctrl_wrapper-sim-vcs/0.flash_ctrl_stress_all/out/run.log
UVM_WARNING @ 0 ps: [BDTYP] Cannot create an object of type 'flash_ctrl_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 0 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
1.flash_ctrl_stress_all.1767465660
Line 37, in log /usr/local/google/home/chencindy/nightly_openTitan/master/flash_ctrl_wrapper-sim-vcs/1.flash_ctrl_stress_all/out/run.log
UVM_WARNING @ 0 ps: [BDTYP] Cannot create an object of type 'flash_ctrl_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 0 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
... and 48 more failures.
0.flash_ctrl_stress_all_with_rand_reset.2418169967
Line 46, in log /usr/local/google/home/chencindy/nightly_openTitan/master/flash_ctrl_wrapper-sim-vcs/0.flash_ctrl_stress_all_with_rand_reset/out/run.log
UVM_WARNING @ 2012668 ps: [BDTYP] Cannot create an object of type 'flash_ctrl_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 2012668 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
1.flash_ctrl_stress_all_with_rand_reset.1135336159
Line 46, in log /usr/local/google/home/chencindy/nightly_openTitan/master/flash_ctrl_wrapper-sim-vcs/1.flash_ctrl_stress_all_with_rand_reset/out/run.log
UVM_WARNING @ 2155164 ps: [BDTYP] Cannot create an object of type 'flash_ctrl_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 2155164 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
... and 48 more failures.
UVM_FATAL (cip_base_vseq__tl_errors.svh:319) [flash_ctrl_common_vseq] Check failed (cfg.tl_intg_alert_name inside {cfg.list_of_alerts}) tl intg alert (fatal_intg_err) is not inside '{"recov_err", "fatal_err"} has 20 failures:
0.flash_ctrl_tl_intg_err.2469549553
Line 49, in log /usr/local/google/home/chencindy/nightly_openTitan/master/flash_ctrl_wrapper-sim-vcs/0.flash_ctrl_tl_intg_err/out/run.log
UVM_FATAL @ 3088419 ps: (cip_base_vseq__tl_errors.svh:319) [uvm_test_top.env.virtual_sequencer.flash_ctrl_common_vseq] Check failed (cfg.tl_intg_alert_name inside {cfg.list_of_alerts}) tl intg alert (fatal_intg_err) is not inside '{"recov_err", "fatal_err"}
UVM_INFO @ 3088419 ps: (uvm_report_server.svh:901) [UVM/REPORT/SERVER]
--- UVM Report Summary ---
Quit count : 0 of 1
1.flash_ctrl_tl_intg_err.1008950728
Line 53, in log /usr/local/google/home/chencindy/nightly_openTitan/master/flash_ctrl_wrapper-sim-vcs/1.flash_ctrl_tl_intg_err/out/run.log
UVM_FATAL @ 6523995 ps: (cip_base_vseq__tl_errors.svh:319) [uvm_test_top.env.virtual_sequencer.flash_ctrl_common_vseq] Check failed (cfg.tl_intg_alert_name inside {cfg.list_of_alerts}) tl intg alert (fatal_intg_err) is not inside '{"recov_err", "fatal_err"}
UVM_INFO @ 6523995 ps: (uvm_report_server.svh:901) [UVM/REPORT/SERVER]
--- UVM Report Summary ---
Quit count : 0 of 1
... and 18 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.phy_status has 12 failures:
1.flash_ctrl_csr_mem_rw_with_rand_reset.639994030
Line 51, in log /usr/local/google/home/chencindy/nightly_openTitan/master/flash_ctrl_wrapper-sim-vcs/1.flash_ctrl_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 23831289 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (7 [0x7] vs 6 [0x6]) Regname: flash_ctrl_core_reg_block.phy_status
UVM_INFO @ 23831289 ps: (uvm_report_server.svh:901) [UVM/REPORT/SERVER]
--- UVM Report Summary ---
Quit count reached!
2.flash_ctrl_csr_mem_rw_with_rand_reset.3071500874
Line 51, in log /usr/local/google/home/chencindy/nightly_openTitan/master/flash_ctrl_wrapper-sim-vcs/2.flash_ctrl_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 11249400 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (7 [0x7] vs 6 [0x6]) Regname: flash_ctrl_core_reg_block.phy_status
UVM_INFO @ 11249400 ps: (uvm_report_server.svh:901) [UVM/REPORT/SERVER]
--- UVM Report Summary ---
Quit count reached!
... and 10 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.status has 8 failures:
0.flash_ctrl_csr_mem_rw_with_rand_reset.1335402434
Line 51, in log /usr/local/google/home/chencindy/nightly_openTitan/master/flash_ctrl_wrapper-sim-vcs/0.flash_ctrl_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 8388095 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (26 [0x1a] vs 10 [0xa]) Regname: flash_ctrl_core_reg_block.status
UVM_INFO @ 8388095 ps: (uvm_report_server.svh:901) [UVM/REPORT/SERVER]
--- UVM Report Summary ---
Quit count reached!
4.flash_ctrl_csr_mem_rw_with_rand_reset.3885204510
Line 51, in log /usr/local/google/home/chencindy/nightly_openTitan/master/flash_ctrl_wrapper-sim-vcs/4.flash_ctrl_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 9577207 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (26 [0x1a] vs 10 [0xa]) Regname: flash_ctrl_core_reg_block.status
UVM_INFO @ 9577207 ps: (uvm_report_server.svh:901) [UVM/REPORT/SERVER]
--- UVM Report Summary ---
Quit count reached!
... and 6 more failures.