4c51f91c9| Milestone | Name | Tests | Passing | Total | Pass Rate |
|---|---|---|---|---|---|
| V1 | smoke | flash_ctrl_smoke | 5 | 5 | 100.00 |
| V1 | csr_hw_reset | flash_ctrl_csr_hw_reset | 5 | 5 | 100.00 |
| V1 | csr_rw | flash_ctrl_csr_rw | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | flash_ctrl_csr_bit_bash | 5 | 5 | 100.00 |
| V1 | csr_aliasing | flash_ctrl_csr_aliasing | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | flash_ctrl_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 |
| V1 | mem_walk | flash_ctrl_mem_walk | 5 | 5 | 100.00 |
| V1 | mem_partial_access | flash_ctrl_mem_partial_access | 5 | 5 | 100.00 |
| V1 | shadow_reg_update_error | flash_ctrl_shadow_reg_errors | 20 | 20 | 100.00 |
| V1 | shadow_reg_read_clear_staged_value | flash_ctrl_shadow_reg_errors | 20 | 20 | 100.00 |
| V1 | shadow_reg_storage_error | flash_ctrl_shadow_reg_errors | 20 | 20 | 100.00 |
| V1 | shadowed_reset_glitch | flash_ctrl_shadow_reg_errors | 20 | 20 | 100.00 |
| V1 | shadow_reg_update_error_with_csr_rw | flash_ctrl_shadow_reg_errors_with_csr_rw | 19 | 20 | 95.00 |
| V1 | TOTAL | 89 | 110 | 80.91 | |
| V2 | backpressure | backpressure | 0 | 0 | -- |
| V2 | all_partitions | flash_ctrl_rand_ops | 50 | 50 | 100.00 |
| V2 | host_read_check | host_read_check | 0 | 0 | -- |
| V2 | host_illegal_access | host_illegal_access | 0 | 0 | -- |
| V2 | host_outstanding_access | host_outstanding_access | 0 | 0 | -- |
| V2 | intr_enabled | intr_enabled | 0 | 0 | -- |
| V2 | host_ctrl_arb | host_ctrl_arb | 0 | 0 | -- |
| V2 | host_read_collide | host_read_collide | 0 | 0 | -- |
| V2 | en_mp_regions | en_mp_regions | 0 | 0 | -- |
| V2 | redundant_pages | redundant_pages | 0 | 0 | -- |
| V2 | lc_ctrl_if | lc_ctrl_if | 0 | 0 | -- |
| V2 | key_mgr_if | key_mgr_if | 0 | 0 | -- |
| V2 | scramble | scramble | 0 | 0 | -- |
| V2 | ecc | ecc | 0 | 0 | -- |
| V2 | read_ecc_metadata | read_ecc_metadata | 0 | 0 | -- |
| V2 | error | error | 0 | 0 | -- |
| V2 | flash_macro_timing | flash_macro_timing | 0 | 0 | -- |
| V2 | stress_all | flash_ctrl_stress_all | 0 | 50 | 0.00 |
| V2 | flash_init | flash_init | 0 | 0 | -- |
| V2 | tlul_to_vendor | tlul_to_vendor | 0 | 0 | -- |
| V2 | alert_test | flash_ctrl_alert_test | 50 | 50 | 100.00 |
| V2 | intr_test | flash_ctrl_intr_test | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | flash_ctrl_tl_errors | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | flash_ctrl_tl_errors | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | flash_ctrl_csr_hw_reset | 5 | 5 | 100.00 |
| flash_ctrl_csr_rw | 20 | 20 | 100.00 | ||
| flash_ctrl_csr_aliasing | 5 | 5 | 100.00 | ||
| flash_ctrl_same_csr_outstanding | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | flash_ctrl_csr_hw_reset | 5 | 5 | 100.00 |
| flash_ctrl_csr_rw | 20 | 20 | 100.00 | ||
| flash_ctrl_csr_aliasing | 5 | 5 | 100.00 | ||
| flash_ctrl_same_csr_outstanding | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 190 | 240 | 79.17 | |
| V2S | TOTAL | 0 | 0 | -- | |
| V3 | tl_intg_err | flash_ctrl_tl_intg_err | 0 | 20 | 0.00 |
| V3 | stress_all_with_rand_reset | flash_ctrl_stress_all_with_rand_reset | 0 | 50 | 0.00 |
| V3 | TOTAL | 0 | 70 | 0.00 | |
| TOTAL | 279 | 420 | 66.43 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 10 | 10 | 8 | 80.00 |
| V2 | 24 | 6 | 5 | 20.83 |
| V3 | 2 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 65.07 | 96.10 | 89.98 | 17.86 | 34.84 | 94.65 | 85.63 | 36.46 |
UVM_WARNING [BDTYP] Cannot create an object of type 'flash_ctrl_stress_all_vseq' because it is not registered with the factory. has 100 failures:
0.flash_ctrl_stress_all.2941515422
Line 37, in log /usr/local/google/home/chencindy/nightly_openTitan/master/flash_ctrl_wrapper-sim-vcs/0.flash_ctrl_stress_all/out/run.log
UVM_WARNING @ 0 ps: [BDTYP] Cannot create an object of type 'flash_ctrl_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 0 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
1.flash_ctrl_stress_all.3878191874
Line 37, in log /usr/local/google/home/chencindy/nightly_openTitan/master/flash_ctrl_wrapper-sim-vcs/1.flash_ctrl_stress_all/out/run.log
UVM_WARNING @ 0 ps: [BDTYP] Cannot create an object of type 'flash_ctrl_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 0 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
... and 48 more failures.
0.flash_ctrl_stress_all_with_rand_reset.4266677846
Line 46, in log /usr/local/google/home/chencindy/nightly_openTitan/master/flash_ctrl_wrapper-sim-vcs/0.flash_ctrl_stress_all_with_rand_reset/out/run.log
UVM_WARNING @ 2159171 ps: [BDTYP] Cannot create an object of type 'flash_ctrl_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 2159171 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
1.flash_ctrl_stress_all_with_rand_reset.3666706926
Line 46, in log /usr/local/google/home/chencindy/nightly_openTitan/master/flash_ctrl_wrapper-sim-vcs/1.flash_ctrl_stress_all_with_rand_reset/out/run.log
UVM_WARNING @ 1923970 ps: [BDTYP] Cannot create an object of type 'flash_ctrl_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 1923970 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
... and 48 more failures.
UVM_FATAL (cip_base_vseq__tl_errors.svh:319) [flash_ctrl_common_vseq] Check failed (cfg.tl_intg_alert_name inside {cfg.list_of_alerts}) tl intg alert (fatal_intg_err) is not inside '{"recov_err", "fatal_err"} has 20 failures:
0.flash_ctrl_tl_intg_err.2188787681
Line 56, in log /usr/local/google/home/chencindy/nightly_openTitan/master/flash_ctrl_wrapper-sim-vcs/0.flash_ctrl_tl_intg_err/out/run.log
UVM_FATAL @ 2459572 ps: (cip_base_vseq__tl_errors.svh:319) [uvm_test_top.env.virtual_sequencer.flash_ctrl_common_vseq] Check failed (cfg.tl_intg_alert_name inside {cfg.list_of_alerts}) tl intg alert (fatal_intg_err) is not inside '{"recov_err", "fatal_err"}
UVM_INFO @ 2459572 ps: (uvm_report_server.svh:901) [UVM/REPORT/SERVER]
--- UVM Report Summary ---
Quit count : 0 of 1
1.flash_ctrl_tl_intg_err.332923587
Line 53, in log /usr/local/google/home/chencindy/nightly_openTitan/master/flash_ctrl_wrapper-sim-vcs/1.flash_ctrl_tl_intg_err/out/run.log
UVM_FATAL @ 2863824 ps: (cip_base_vseq__tl_errors.svh:319) [uvm_test_top.env.virtual_sequencer.flash_ctrl_common_vseq] Check failed (cfg.tl_intg_alert_name inside {cfg.list_of_alerts}) tl intg alert (fatal_intg_err) is not inside '{"recov_err", "fatal_err"}
UVM_INFO @ 2863824 ps: (uvm_report_server.svh:901) [UVM/REPORT/SERVER]
--- UVM Report Summary ---
Quit count : 0 of 1
... and 18 more failures.
UVM_ERROR (csr_utils_pkg.sv:431) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.status has 13 failures:
0.flash_ctrl_csr_mem_rw_with_rand_reset.1835924074
Line 51, in log /usr/local/google/home/chencindy/nightly_openTitan/master/flash_ctrl_wrapper-sim-vcs/0.flash_ctrl_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 6955623 ps: (csr_utils_pkg.sv:431) [csr_utils::csr_rd_check] Check failed obs == exp (26 [0x1a] vs 10 [0xa]) Regname: flash_ctrl_core_reg_block.status
UVM_INFO @ 6955623 ps: (uvm_report_server.svh:901) [UVM/REPORT/SERVER]
--- UVM Report Summary ---
Quit count reached!
1.flash_ctrl_csr_mem_rw_with_rand_reset.4130326506
Line 51, in log /usr/local/google/home/chencindy/nightly_openTitan/master/flash_ctrl_wrapper-sim-vcs/1.flash_ctrl_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 10916272 ps: (csr_utils_pkg.sv:431) [csr_utils::csr_rd_check] Check failed obs == exp (26 [0x1a] vs 10 [0xa]) Regname: flash_ctrl_core_reg_block.status
UVM_INFO @ 10916272 ps: (uvm_report_server.svh:901) [UVM/REPORT/SERVER]
--- UVM Report Summary ---
Quit count reached!
... and 11 more failures.
UVM_ERROR (csr_utils_pkg.sv:431) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.phy_status has 7 failures:
2.flash_ctrl_csr_mem_rw_with_rand_reset.2089514053
Line 51, in log /usr/local/google/home/chencindy/nightly_openTitan/master/flash_ctrl_wrapper-sim-vcs/2.flash_ctrl_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 4184492 ps: (csr_utils_pkg.sv:431) [csr_utils::csr_rd_check] Check failed obs == exp (7 [0x7] vs 6 [0x6]) Regname: flash_ctrl_core_reg_block.phy_status
UVM_INFO @ 4184492 ps: (uvm_report_server.svh:901) [UVM/REPORT/SERVER]
--- UVM Report Summary ---
Quit count reached!
3.flash_ctrl_csr_mem_rw_with_rand_reset.185227745
Line 51, in log /usr/local/google/home/chencindy/nightly_openTitan/master/flash_ctrl_wrapper-sim-vcs/3.flash_ctrl_csr_mem_rw_with_rand_reset/out/run.log
UVM_ERROR @ 18229371 ps: (csr_utils_pkg.sv:431) [csr_utils::csr_rd_check] Check failed obs == exp (7 [0x7] vs 6 [0x6]) Regname: flash_ctrl_core_reg_block.phy_status
UVM_INFO @ 18229371 ps: (uvm_report_server.svh:901) [UVM/REPORT/SERVER]
--- UVM Report Summary ---
Quit count reached!
... and 5 more failures.
UVM_ERROR (cip_base_vseq__shadow_reg_errors.svh:130) [flash_ctrl_common_vseq] Check failed cfg.m_alert_agent_cfg[alert_name].vif.get_alert() == * (* [*] vs * [*]) Unexpected alert: recov_err fired has 1 failures:
3.flash_ctrl_shadow_reg_errors_with_csr_rw.1645749452
Line 1207, in log /usr/local/google/home/chencindy/nightly_openTitan/master/flash_ctrl_wrapper-sim-vcs/3.flash_ctrl_shadow_reg_errors_with_csr_rw/out/run.log
UVM_ERROR @ 6021349002 ps: (cip_base_vseq__shadow_reg_errors.svh:130) [uvm_test_top.env.virtual_sequencer.flash_ctrl_common_vseq] Check failed cfg.m_alert_agent_cfg[alert_name].vif.get_alert() == 0 (1 [0x1] vs 0 [0x0]) Unexpected alert: recov_err fired
UVM_INFO @ 6021349002 ps: (uvm_report_server.svh:901) [UVM/REPORT/SERVER]
--- UVM Report Summary ---
Quit count reached!