Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 50.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_eflash_tl_agent.cov::m_tl_a_chan_cov_cg 0.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_eflash_tl_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
0.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_eflash_tl_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 134 0 0.00
Crosses 3 3 0 0.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_eflash_tl_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 1 0 0.00 100 1 1 0
cp_opcode 3 3 0 0.00 100 1 1 0
cp_size 1 1 0 0.00 100 1 1 0
cp_source 129 129 0 0.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_eflash_tl_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 3 0 0.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for cp_mask

Uncovered bins
NAMECOUNTAT LEASTNUMBER
all_enables 0 1 1


Excluded/Illegal bins
NAMECOUNTSTATUS
others 0 Excluded



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 3 0 0.00


User Defined Bins for cp_opcode

Uncovered bins
NAMECOUNTAT LEASTNUMBER
values_4 0 1 1
values_0 0 1 1
values_1 0 1 1



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for cp_size

Uncovered bins
NAMECOUNTAT LEASTNUMBER
biggest_size 0 1 1


Excluded/Illegal bins
NAMECOUNTSTATUS
others 0 Excluded



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 129 0 0.00


User Defined Bins for cp_source

Uncovered bins
NAMECOUNTAT LEASTNUMBER
valid_sources_00 0 1 1
valid_sources_01 0 1 1
valid_sources_02 0 1 1
valid_sources_03 0 1 1
valid_sources_04 0 1 1
valid_sources_05 0 1 1
valid_sources_06 0 1 1
valid_sources_07 0 1 1
valid_sources_08 0 1 1
valid_sources_09 0 1 1
valid_sources_0a 0 1 1
valid_sources_0b 0 1 1
valid_sources_0c 0 1 1
valid_sources_0d 0 1 1
valid_sources_0e 0 1 1
valid_sources_0f 0 1 1
valid_sources_10 0 1 1
valid_sources_11 0 1 1
valid_sources_12 0 1 1
valid_sources_13 0 1 1
valid_sources_14 0 1 1
valid_sources_15 0 1 1
valid_sources_16 0 1 1
valid_sources_17 0 1 1
valid_sources_18 0 1 1
valid_sources_19 0 1 1
valid_sources_1a 0 1 1
valid_sources_1b 0 1 1
valid_sources_1c 0 1 1
valid_sources_1d 0 1 1
valid_sources_1e 0 1 1
valid_sources_1f 0 1 1
valid_sources_20 0 1 1
valid_sources_21 0 1 1
valid_sources_22 0 1 1
valid_sources_23 0 1 1
valid_sources_24 0 1 1
valid_sources_25 0 1 1
valid_sources_26 0 1 1
valid_sources_27 0 1 1
valid_sources_28 0 1 1
valid_sources_29 0 1 1
valid_sources_2a 0 1 1
valid_sources_2b 0 1 1
valid_sources_2c 0 1 1
valid_sources_2d 0 1 1
valid_sources_2e 0 1 1
valid_sources_2f 0 1 1
valid_sources_30 0 1 1
valid_sources_31 0 1 1
valid_sources_32 0 1 1
valid_sources_33 0 1 1
valid_sources_34 0 1 1
valid_sources_35 0 1 1
valid_sources_36 0 1 1
valid_sources_37 0 1 1
valid_sources_38 0 1 1
valid_sources_39 0 1 1
valid_sources_3a 0 1 1
valid_sources_3b 0 1 1
valid_sources_3c 0 1 1
valid_sources_3d 0 1 1
valid_sources_3e 0 1 1
valid_sources_3f 0 1 1
valid_sources_40 0 1 1
valid_sources_41 0 1 1
valid_sources_42 0 1 1
valid_sources_43 0 1 1
valid_sources_44 0 1 1
valid_sources_45 0 1 1
valid_sources_46 0 1 1
valid_sources_47 0 1 1
valid_sources_48 0 1 1
valid_sources_49 0 1 1
valid_sources_4a 0 1 1
valid_sources_4b 0 1 1
valid_sources_4c 0 1 1
valid_sources_4d 0 1 1
valid_sources_4e 0 1 1
valid_sources_4f 0 1 1
valid_sources_50 0 1 1
valid_sources_51 0 1 1
valid_sources_52 0 1 1
valid_sources_53 0 1 1
valid_sources_54 0 1 1
valid_sources_55 0 1 1
valid_sources_56 0 1 1
valid_sources_57 0 1 1
valid_sources_58 0 1 1
valid_sources_59 0 1 1
valid_sources_5a 0 1 1
valid_sources_5b 0 1 1
valid_sources_5c 0 1 1
valid_sources_5d 0 1 1
valid_sources_5e 0 1 1
valid_sources_5f 0 1 1
valid_sources_60 0 1 1
valid_sources_61 0 1 1
valid_sources_62 0 1 1
valid_sources_63 0 1 1
valid_sources_64 0 1 1
valid_sources_65 0 1 1
valid_sources_66 0 1 1
valid_sources_67 0 1 1
valid_sources_68 0 1 1
valid_sources_69 0 1 1
valid_sources_6a 0 1 1
valid_sources_6b 0 1 1
valid_sources_6c 0 1 1
valid_sources_6d 0 1 1
valid_sources_6e 0 1 1
valid_sources_6f 0 1 1
valid_sources_70 0 1 1
valid_sources_71 0 1 1
valid_sources_72 0 1 1
valid_sources_73 0 1 1
valid_sources_74 0 1 1
valid_sources_75 0 1 1
valid_sources_76 0 1 1
valid_sources_77 0 1 1
valid_sources_78 0 1 1
valid_sources_79 0 1 1
valid_sources_7a 0 1 1
valid_sources_7b 0 1 1
valid_sources_7c 0 1 1
valid_sources_7d 0 1 1
valid_sources_7e 0 1 1
valid_sources_7f 0 1 1
valid_sources_80 0 1 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 3 0 0.00 3


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Uncovered bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTNUMBER
* * * -- -- 3


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1173439 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 705704 1 T1 1332 T2 313 T3 901



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values_4 1405919 1 T1 2124 T2 263 T3 1316
values_0 235220 1 T1 257 T2 138 T3 196
values_1 238004 1 T1 182 T2 144 T3 200



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 844383 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 1034760 1 T1 1596 T2 372 T3 1100



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources_00 7727 1 T4 51 T5 12 T6 20
valid_sources_01 6974 1 T4 50 T5 11 T6 48
valid_sources_02 6894 1 T4 77 T5 11 T6 40
valid_sources_03 6427 1 T4 37 T5 13 T6 40
valid_sources_04 6623 1 T4 35 T5 4 T6 46
valid_sources_05 6142 1 T4 60 T5 8 T6 26
valid_sources_06 6623 1 T4 53 T5 17 T6 21
valid_sources_07 6968 1 T4 51 T5 8 T6 27
valid_sources_08 6952 1 T4 55 T5 19 T6 55
valid_sources_09 6203 1 T4 50 T5 7 T6 38
valid_sources_0a 7274 1 T4 42 T5 5 T6 6
valid_sources_0b 7341 1 T4 50 T5 9 T6 42
valid_sources_0c 6545 1 T4 64 T5 11 T6 41
valid_sources_0d 6233 1 T4 43 T5 11 T6 46
valid_sources_0e 6960 1 T4 39 T5 11 T6 8
valid_sources_0f 6409 1 T4 44 T5 6 T6 10
valid_sources_10 6325 1 T4 31 T5 12 T6 23
valid_sources_11 6099 1 T4 47 T5 11 T6 8
valid_sources_12 7170 1 T4 31 T5 11 T6 3
valid_sources_13 6470 1 T4 59 T5 14 T6 15
valid_sources_14 6533 1 T4 88 T5 19 T6 6
valid_sources_15 6717 1 T4 61 T5 5 T6 55
valid_sources_16 6588 1 T4 63 T5 20 T6 19
valid_sources_17 6057 1 T4 33 T5 19 T6 36
valid_sources_18 6982 1 T4 23 T5 3 T6 38
valid_sources_19 6828 1 T4 50 T5 8 T6 19
valid_sources_1a 6791 1 T4 51 T5 13 T6 10
valid_sources_1b 6625 1 T4 47 T5 7 T6 15
valid_sources_1c 6733 1 T4 68 T5 6 T6 54
valid_sources_1d 8030 1 T4 44 T5 14 T6 25
valid_sources_1e 7537 1 T4 46 T5 3 T6 14
valid_sources_1f 7268 1 T4 38 T5 20 T6 48
valid_sources_20 6530 1 T4 56 T5 7 T6 14
valid_sources_21 7509 1 T4 48 T5 10 T6 30
valid_sources_22 7914 1 T4 36 T5 5 T6 20
valid_sources_23 8014 1 T4 55 T5 10 T6 14
valid_sources_24 7299 1 T4 53 T5 20 T6 47
valid_sources_25 6052 1 T4 32 T5 16 T6 23
valid_sources_26 7240 1 T4 34 T5 4 T6 45
valid_sources_27 6481 1 T4 50 T5 13 T6 12
valid_sources_28 6915 1 T4 47 T5 15 T6 12
valid_sources_29 7248 1 T4 37 T5 4 T6 61
valid_sources_2a 6824 1 T4 34 T5 10 T6 46
valid_sources_2b 8685 1 T4 66 T5 7 T6 25
valid_sources_2c 6729 1 T4 43 T5 7 T6 15
valid_sources_2d 6925 1 T4 73 T5 29 T6 14
valid_sources_2e 6534 1 T4 19 T5 5 T6 37
valid_sources_2f 6292 1 T4 59 T5 4 T6 43
valid_sources_30 6664 1 T4 45 T5 15 T6 21
valid_sources_31 5876 1 T4 32 T5 19 T6 12
valid_sources_32 8052 1 T4 57 T5 10 T6 13
valid_sources_33 7830 1 T4 30 T5 8 T6 12
valid_sources_34 7378 1 T4 63 T5 18 T6 45
valid_sources_35 7933 1 T4 44 T5 8 T6 15
valid_sources_36 7393 1 T4 43 T5 16 T6 30
valid_sources_37 6815 1 T4 50 T5 8 T6 12
valid_sources_38 5979 1 T4 38 T5 17 T6 33
valid_sources_39 6740 1 T4 34 T5 3 T6 50
valid_sources_3a 7477 1 T4 58 T5 1 T6 39
valid_sources_3b 6434 1 T4 51 T5 18 T6 68
valid_sources_3c 8897 1 T4 32 T5 10 T6 31
valid_sources_3d 6726 1 T4 44 T5 18 T6 34
valid_sources_3e 7141 1 T4 67 T5 23 T6 63
valid_sources_3f 6164 1 T4 66 T5 9 T6 26
valid_sources_40 5427 1 T4 44 T5 21 T6 29
valid_sources_41 7407 1 T4 39 T5 16 T6 5
valid_sources_42 6448 1 T4 62 T5 11 T6 2
valid_sources_43 7454 1 T4 19 T5 12 T6 35
valid_sources_44 6567 1 T4 46 T5 21 T6 23
valid_sources_45 7222 1 T4 47 T5 13 T6 28
valid_sources_46 6579 1 T4 40 T5 8 T6 17
valid_sources_47 6481 1 T4 46 T5 16 T6 41
valid_sources_48 6414 1 T4 59 T5 11 T6 36
valid_sources_49 6862 1 T4 52 T5 26 T6 27
valid_sources_4a 6702 1 T4 46 T5 13 T6 46
valid_sources_4b 7807 1 T4 41 T5 13 T6 78
valid_sources_4c 6834 1 T4 39 T5 16 T6 6
valid_sources_4d 6380 1 T4 22 T5 7 T6 50
valid_sources_4e 6962 1 T4 49 T5 11 T6 11
valid_sources_4f 6662 1 T4 43 T5 21 T6 52
valid_sources_50 7298 1 T4 29 T5 13 T6 40
valid_sources_51 6606 1 T4 57 T5 13 T6 44
valid_sources_52 9692 1 T4 40 T5 10 T6 38
valid_sources_53 6912 1 T4 47 T5 16 T6 79
valid_sources_54 6586 1 T4 33 T5 15 T6 88
valid_sources_55 7006 1 T4 56 T5 7 T6 1
valid_sources_56 6447 1 T4 44 T5 2 T6 18
valid_sources_57 6538 1 T4 30 T5 6 T6 39
valid_sources_58 6773 1 T4 64 T5 3 T6 94
valid_sources_59 8624 1 T4 53 T5 4 T6 20
valid_sources_5a 6097 1 T4 44 T5 27 T6 34
valid_sources_5b 7000 1 T4 39 T5 9 T6 44
valid_sources_5c 7238 1 T4 57 T5 17 T6 38
valid_sources_5d 10917 1 T4 47 T5 11 T6 3
valid_sources_5e 6129 1 T4 38 T5 16 T6 43
valid_sources_5f 6576 1 T4 61 T5 23 T6 57
valid_sources_60 5915 1 T4 84 T5 20 T6 18
valid_sources_61 6169 1 T4 54 T5 22 T6 34
valid_sources_62 6284 1 T4 66 T5 2 T6 21
valid_sources_63 6874 1 T4 41 T5 16 T6 54
valid_sources_64 6766 1 T4 53 T5 11 T6 25
valid_sources_65 6405 1 T4 84 T5 13 T6 21
valid_sources_66 6769 1 T4 45 T5 21 T6 33
valid_sources_67 6231 1 T4 48 T5 6 T6 3
valid_sources_68 6037 1 T4 31 T5 7 T6 80
valid_sources_69 17174 1 T4 37 T5 2 T6 9
valid_sources_6a 6375 1 T4 35 T5 10 T6 17
valid_sources_6b 7136 1 T4 80 T5 5 T6 57
valid_sources_6c 6416 1 T4 44 T5 10 T6 21
valid_sources_6d 6422 1 T4 78 T6 54 T7 259
valid_sources_6e 7027 1 T4 49 T5 12 T6 19
valid_sources_6f 6441 1 T4 46 T5 8 T6 37
valid_sources_70 6520 1 T4 34 T5 16 T6 37
valid_sources_71 7230 1 T4 69 T5 18 T6 30
valid_sources_72 6628 1 T4 42 T5 11 T6 37
valid_sources_73 6084 1 T4 40 T5 5 T6 9
valid_sources_74 6605 1 T4 44 T5 16 T6 19
valid_sources_75 6599 1 T4 57 T5 13 T6 24
valid_sources_76 7726 1 T4 64 T5 15 T6 1
valid_sources_77 6275 1 T4 64 T5 13 T6 28
valid_sources_78 6588 1 T4 53 T5 8 T6 46
valid_sources_79 6634 1 T4 46 T5 5 T6 41
valid_sources_7a 6850 1 T4 85 T5 10 T6 25
valid_sources_7b 7353 1 T4 54 T5 6 T6 37
valid_sources_7c 8483 1 T4 63 T5 16 T6 20
valid_sources_7d 6883 1 T4 48 T5 13 T6 49
valid_sources_7e 7390 1 T4 36 T5 12 T6 31
valid_sources_7f 7398 1 T4 35 T5 10 T6 42
valid_sources_80 6277 1 T4 40 T5 17 T6 29



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values_4 all_enables biggest_size 525367 1 T1 1046 T2 141 T3 676
values_0 all_enables biggest_size 109285 1 T1 184 T2 97 T3 123
values_1 all_enables biggest_size 71052 1 T1 102 T2 75 T3 102

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%