Group : dv_lib_pkg::bit_toggle_cg_wrap::bit_toggle_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : dv_lib_pkg::bit_toggle_cg_wrap::bit_toggle_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 44.64 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv

14 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
uvm_test_top.env.m_eflash_tl_agent.cov::PutFullData_mask_not_match_size 0.00 1 100 1 64 64
uvm_test_top.env.m_eflash_tl_agent.cov::addr_not_align_mask 0.00 1 100 1 64 64
uvm_test_top.env.m_eflash_tl_agent.cov::addr_not_align_size 0.00 1 100 1 64 64
uvm_test_top.env.m_eflash_tl_agent.cov::invalid_a_opcode 0.00 1 100 1 64 64
uvm_test_top.env.m_eflash_tl_agent.cov::m_outstanding_item_w_same_addr_cov_obj 0.00 1 100 1 64 64
uvm_test_top.env.m_eflash_tl_agent.cov::mask_not_in_enabled_lanes 0.00 1 100 1 64 64
uvm_test_top.env.m_eflash_tl_agent.cov::size_over_max 0.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::m_outstanding_item_w_same_addr_cov_obj 25.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::PutFullData_mask_not_match_size 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::addr_not_align_mask 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::addr_not_align_size 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::invalid_a_opcode 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::mask_not_in_enabled_lanes 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::size_over_max 100.00 1 100 1 64 64




Group Instance : uvm_test_top.env.m_eflash_tl_agent.cov::PutFullData_mask_not_match_size
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
0.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_eflash_tl_agent.cov::PutFullData_mask_not_match_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 4 0 0.00


Variables for Group Instance uvm_test_top.env.m_eflash_tl_agent.cov::PutFullData_mask_not_match_size
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 2 0 0.00 100 1 1 0
cp_value 2 2 0 0.00 100 1 1 2



Group Instance : uvm_test_top.env.m_eflash_tl_agent.cov::addr_not_align_mask
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
0.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_eflash_tl_agent.cov::addr_not_align_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 4 0 0.00


Variables for Group Instance uvm_test_top.env.m_eflash_tl_agent.cov::addr_not_align_mask
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 2 0 0.00 100 1 1 0
cp_value 2 2 0 0.00 100 1 1 2



Group Instance : uvm_test_top.env.m_eflash_tl_agent.cov::addr_not_align_size
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
0.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_eflash_tl_agent.cov::addr_not_align_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 4 0 0.00


Variables for Group Instance uvm_test_top.env.m_eflash_tl_agent.cov::addr_not_align_size
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 2 0 0.00 100 1 1 0
cp_value 2 2 0 0.00 100 1 1 2



Group Instance : uvm_test_top.env.m_eflash_tl_agent.cov::invalid_a_opcode
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
0.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_eflash_tl_agent.cov::invalid_a_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 4 0 0.00


Variables for Group Instance uvm_test_top.env.m_eflash_tl_agent.cov::invalid_a_opcode
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 2 0 0.00 100 1 1 0
cp_value 2 2 0 0.00 100 1 1 2



Group Instance : uvm_test_top.env.m_eflash_tl_agent.cov::m_outstanding_item_w_same_addr_cov_obj
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
0.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_eflash_tl_agent.cov::m_outstanding_item_w_same_addr_cov_obj

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 4 0 0.00


Variables for Group Instance uvm_test_top.env.m_eflash_tl_agent.cov::m_outstanding_item_w_same_addr_cov_obj
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 2 0 0.00 100 1 1 0
cp_value 2 2 0 0.00 100 1 1 2



Group Instance : uvm_test_top.env.m_eflash_tl_agent.cov::mask_not_in_enabled_lanes
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
0.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_eflash_tl_agent.cov::mask_not_in_enabled_lanes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 4 0 0.00


Variables for Group Instance uvm_test_top.env.m_eflash_tl_agent.cov::mask_not_in_enabled_lanes
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 2 0 0.00 100 1 1 0
cp_value 2 2 0 0.00 100 1 1 2



Group Instance : uvm_test_top.env.m_eflash_tl_agent.cov::size_over_max
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
0.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_eflash_tl_agent.cov::size_over_max

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 4 0 0.00


Variables for Group Instance uvm_test_top.env.m_eflash_tl_agent.cov::size_over_max
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 2 0 0.00 100 1 1 0
cp_value 2 2 0 0.00 100 1 1 2



Group Instance : uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::m_outstanding_item_w_same_addr_cov_obj
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
25.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::m_outstanding_item_w_same_addr_cov_obj

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 3 1 25.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::m_outstanding_item_w_same_addr_cov_obj
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 2 0 0.00 100 1 1 0
cp_value 2 1 1 50.00 100 1 1 2



Group Instance : uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::PutFullData_mask_not_match_size
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::PutFullData_mask_not_match_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::PutFullData_mask_not_match_size
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::addr_not_align_mask
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::addr_not_align_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::addr_not_align_mask
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::addr_not_align_size
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::addr_not_align_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::addr_not_align_size
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::invalid_a_opcode
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::invalid_a_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::invalid_a_opcode
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::mask_not_in_enabled_lanes
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::mask_not_in_enabled_lanes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::mask_not_in_enabled_lanes
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::size_over_max
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::size_over_max

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::size_over_max
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 2 0 0.00


User Defined Bins for cp_transitions

Uncovered bins
NAMECOUNTAT LEASTNUMBER
falling 0 1 1
rising 0 1 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[0] - auto[1]] -- -- 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 2 0 0.00


User Defined Bins for cp_transitions

Uncovered bins
NAMECOUNTAT LEASTNUMBER
falling 0 1 1
rising 0 1 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[0] - auto[1]] -- -- 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 2 0 0.00


User Defined Bins for cp_transitions

Uncovered bins
NAMECOUNTAT LEASTNUMBER
falling 0 1 1
rising 0 1 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[0] - auto[1]] -- -- 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 2 0 0.00


User Defined Bins for cp_transitions

Uncovered bins
NAMECOUNTAT LEASTNUMBER
falling 0 1 1
rising 0 1 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[0] - auto[1]] -- -- 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 2 0 0.00


User Defined Bins for cp_transitions

Uncovered bins
NAMECOUNTAT LEASTNUMBER
falling 0 1 1
rising 0 1 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[0] - auto[1]] -- -- 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 2 0 0.00


User Defined Bins for cp_transitions

Uncovered bins
NAMECOUNTAT LEASTNUMBER
falling 0 1 1
rising 0 1 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[0] - auto[1]] -- -- 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 2 0 0.00


User Defined Bins for cp_transitions

Uncovered bins
NAMECOUNTAT LEASTNUMBER
falling 0 1 1
rising 0 1 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[0] - auto[1]] -- -- 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 2 0 0.00


User Defined Bins for cp_transitions

Uncovered bins
NAMECOUNTAT LEASTNUMBER
falling 0 1 1
rising 0 1 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1900828 1 T1 2563 T2 545 T3 1712


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
falling 4274 1 T16 209 T17 214 T18 135
rising 4277 1 T16 209 T17 213 T18 136



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 15486 1 T16 906 T17 1040 T18 419
auto[1] 6199 1 T16 274 T17 270 T18 183


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
falling 4689 1 T16 258 T17 309 T18 127
rising 4690 1 T16 259 T17 309 T18 127



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 14631 1 T16 794 T17 823 T18 417
auto[1] 7054 1 T16 386 T17 487 T18 185


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
falling 4689 1 T16 258 T17 309 T18 127
rising 4690 1 T16 259 T17 309 T18 127



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 14631 1 T16 794 T17 823 T18 417
auto[1] 7054 1 T16 386 T17 487 T18 185


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
falling 4190 1 T16 265 T17 299 T18 117
rising 4184 1 T16 265 T17 299 T18 116



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 15938 1 T16 816 T17 814 T18 463
auto[1] 5747 1 T16 364 T17 496 T18 139


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
falling 4856 1 T16 262 T17 281 T18 131
rising 4858 1 T16 261 T17 281 T18 130



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 14198 1 T16 800 T17 926 T18 409
auto[1] 7487 1 T16 380 T17 384 T18 193


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
falling 4205 1 T16 213 T17 253 T18 124
rising 4210 1 T16 213 T17 253 T18 125



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 15796 1 T16 887 T17 974 T18 423
auto[1] 5889 1 T16 293 T17 336 T18 179

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%