Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : flash_ctrl_prog
SCORELINECONDTOGGLEFSMBRANCHASSERT
77.37 98.25 48.15 85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_prog.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_flash_ctrl_prog 77.37 98.25 48.15 85.71



Module Instance : tb.dut.u_flash_ctrl_prog

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
77.37 98.25 48.15 85.71


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
77.37 98.25 48.15 85.71


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
66.65 91.74 69.23 13.94 75.00 83.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : flash_ctrl_prog
Line No.TotalCoveredPercent
TOTAL575698.25
ALWAYS5433100.00
ALWAYS6266100.00
ALWAYS724375.00
CONT_ASSIGN7911100.00
CONT_ASSIGN8011100.00
ALWAYS8355100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10711100.00
CONT_ASSIGN10811100.00
ALWAYS1142424100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16511100.00
CONT_ASSIGN17011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_prog.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
55 1 1
57 1 1
62 1 1
63 1 1
64 1 1
65 1 1
66 1 1
67 1 1
MISSING_ELSE
72 1 1
73 1 1
74 1 1
75 0 1
MISSING_ELSE
79 1 1
80 1 1
83 1 1
84 1 1
85 1 1
86 1 1
88 1 1
94 1 1
104 1 1
105 1 1
106 1 1
107 1 1
108 1 1
114 1 1
115 1 1
116 1 1
117 1 1
118 1 1
120 1 1
126 1 1
127 1 1
129 1 1
130 1 1
131 1 1
132 1 1
134 1 1
135 1 1
137 1 1
MISSING_ELSE
141 1 1
142 1 1
143 1 1
144 1 1
145 1 1
MISSING_ELSE
149 1 1
151 1 1
152 1 1
153 1 1
MISSING_ELSE
160 1 1
161 1 1
162 1 1
163 1 1
164 1 1
165 1 1
170 1 1


Cond Coverage for Module : flash_ctrl_prog
TotalCoveredPercent
Conditions271348.15
Logical271348.15
Non-Logical00
Event00

 LINE       64
 EXPRESSION (op_start_i && op_done_o)
             -----1----    ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       74
 EXPRESSION (((~|op_err_q)) && ((|op_err_d)))
             -------1------    ------2------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       79
 EXPRESSION (flash_req_o && flash_done_i)
             -----1-----    ------2-----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       85
 EXPRESSION (op_start_i && op_done_o)
             -----1----    ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       126
 EXPRESSION (op_start_i && prog_type_avail && ((!win_err)))
             -----1----    -------2-------    ------3-----
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T3

 LINE       137
 EXPRESSION (((|op_err_d)) ? StErr : StNorm)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       141
 EXPRESSION (op_start_i && (((!prog_type_avail)) || win_err))
             -----1----    ----------------2----------------
-1--2-StatusTests
01CoveredT1,T4,T5
10Not Covered
11Not Covered

 LINE       141
 SUB-EXPRESSION (((!prog_type_avail)) || win_err)
                 ----------1---------    ---2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T4,T5
10Not Covered

 LINE       151
 EXPRESSION (data_rdy_i && cnt_hit)
             -----1----    ---2---
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

Branch Coverage for Module : flash_ctrl_prog
Line No.TotalCoveredPercent
Branches 21 18 85.71
IF 54 2 2 100.00
IF 62 4 4 100.00
IF 72 3 2 66.67
IF 83 3 3 100.00
CASE 120 9 7 77.78

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 54 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 62 if ((!rst_ni)) -2-: 64 if ((op_start_i && op_done_o)) -3-: 66 if (data_rd_o)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 72 if ((!rst_ni)) -2-: 74 if (((~|op_err_q) && (|op_err_d)))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 83 if ((!rst_ni)) -2-: 85 if ((op_start_i && op_done_o))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 120 case (st_q) -2-: 126 if (((op_start_i && prog_type_avail) && (!win_err))) -3-: 129 if (txn_done) -4-: 134 if (cnt_hit) -5-: 137 ((|op_err_d)) ? -6-: 141 if ((op_start_i && ((!prog_type_avail) || win_err))) -7-: 151 if ((data_rdy_i && cnt_hit))

Branches:
-1--2--3--4--5--6--7-StatusTests
StNorm 1 1 1 - - - Covered T1,T2,T3
StNorm 1 1 0 1 - - Not Covered
StNorm 1 1 0 0 - - Covered T1,T2,T3
StNorm 1 0 - - - - Covered T1,T2,T3
StNorm 0 - - - 1 - Covered T1,T2,T3
StNorm 0 - - - 0 - Covered T1,T2,T3
StErr - - - - - 1 Covered T1,T2,T3
StErr - - - - - 0 Covered T1,T2,T3
default - - - - - - Not Covered

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%