SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
52.02 | 50.00 | 100.00 | 6.06 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
16.88 | 14.29 | 33.33 | 3.03 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
16.88 | 14.29 | 33.33 | 3.03 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_cfg_ram |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
32.54 | 14.29 | 33.33 | 50.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
32.54 | 14.29 | 33.33 | 50.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_info_types[0].u_info_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
32.54 | 14.29 | 33.33 | 50.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
32.54 | 14.29 | 33.33 | 50.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_info_types[0].u_info_mem_meta |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
32.54 | 14.29 | 33.33 | 50.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
32.54 | 14.29 | 33.33 | 50.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_info_types[1].u_info_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
32.54 | 14.29 | 33.33 | 50.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
32.54 | 14.29 | 33.33 | 50.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_info_types[1].u_info_mem_meta |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
32.54 | 14.29 | 33.33 | 50.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
32.54 | 14.29 | 33.33 | 50.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_info_types[2].u_info_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
32.54 | 14.29 | 33.33 | 50.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
32.54 | 14.29 | 33.33 | 50.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_info_types[2].u_info_mem_meta |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
32.54 | 14.29 | 33.33 | 50.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
32.54 | 14.29 | 33.33 | 50.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_info_types[0].u_info_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
32.54 | 14.29 | 33.33 | 50.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
32.54 | 14.29 | 33.33 | 50.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_info_types[0].u_info_mem_meta |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
32.54 | 14.29 | 33.33 | 50.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
32.54 | 14.29 | 33.33 | 50.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_info_types[1].u_info_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
32.54 | 14.29 | 33.33 | 50.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
32.54 | 14.29 | 33.33 | 50.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_info_types[1].u_info_mem_meta |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
32.54 | 14.29 | 33.33 | 50.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
32.54 | 14.29 | 33.33 | 50.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_info_types[2].u_info_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
32.54 | 14.29 | 33.33 | 50.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
32.54 | 14.29 | 33.33 | 50.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_info_types[2].u_info_mem_meta |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_mem_meta |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_mem_meta |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE |
16.88 | 14.29 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 1 | 14.29 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 1 | 16.67 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 0 | 1 | |
65 | 0 | 1 | |
66 | 0 | 1 | |
67 | 0 | 1 | |
==> MISSING_ELSE | |||
72 | 0 | 1 | |
MISSING_ELSE |
SCORE | LINE |
95.24 | 85.71 |
SCORE | LINE |
95.24 | 85.71 |
SCORE | LINE |
32.54 | 14.29 |
SCORE | LINE |
32.54 | 14.29 |
SCORE | LINE |
32.54 | 14.29 |
SCORE | LINE |
32.54 | 14.29 |
SCORE | LINE |
32.54 | 14.29 |
SCORE | LINE |
32.54 | 14.29 |
SCORE | LINE |
95.24 | 85.71 |
SCORE | LINE |
95.24 | 85.71 |
SCORE | LINE |
32.54 | 14.29 |
SCORE | LINE |
32.54 | 14.29 |
SCORE | LINE |
32.54 | 14.29 |
SCORE | LINE |
32.54 | 14.29 |
SCORE | LINE |
32.54 | 14.29 |
SCORE | LINE |
32.54 | 14.29 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 33 | 33 | 100.00 | 2 | 6.06 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 33 | 33 | 100.00 | 2 | 6.06 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 935 | 935 | 0 | 0 |
T1 | 17 | 17 | 0 | 0 |
T2 | 17 | 17 | 0 | 0 |
T3 | 17 | 17 | 0 | 0 |
T4 | 17 | 17 | 0 | 0 |
T5 | 17 | 17 | 0 | 0 |
T6 | 17 | 17 | 0 | 0 |
T7 | 17 | 17 | 0 | 0 |
T8 | 17 | 17 | 0 | 0 |
T9 | 17 | 17 | 0 | 0 |
T10 | 17 | 17 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 25426322 | 2390268 | 0 | 0 |
T1 | 22412 | 7300 | 0 | 0 |
T2 | 12566 | 5100 | 0 | 0 |
T3 | 14752 | 4400 | 0 | 0 |
T4 | 344696 | 152344 | 0 | 0 |
T5 | 118340 | 29000 | 0 | 0 |
T6 | 63968 | 23100 | 0 | 0 |
T7 | 555476 | 273740 | 0 | 0 |
T8 | 875400 | 416236 | 0 | 0 |
T9 | 5822 | 700 | 0 | 0 |
T10 | 75520 | 26600 | 0 | 0 |
T11 | 8658 | 3500 | 0 | 0 |
T12 | 14884 | 1200 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 1 | 14.29 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 1 | 16.67 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 0 | 1 | |
65 | 0 | 1 | |
66 | 0 | 1 | |
67 | 0 | 1 | |
==> MISSING_ELSE | |||
72 | 0 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 1 | 33.33 | |
IF | 63 | 3 | 1 | 33.33 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Not Covered | |
1 | 0 | Not Covered | |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 33 | 33 | 100.00 | 1 | 3.03 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 33 | 33 | 100.00 | 1 | 3.03 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 55 | 55 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 1 | 14.29 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 1 | 16.67 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 0 | 1 | |
65 | 0 | 1 | |
66 | 0 | 1 | |
67 | 0 | 1 | |
==> MISSING_ELSE | |||
72 | 0 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 1 | 33.33 | |
IF | 63 | 3 | 1 | 33.33 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Not Covered | |
1 | 0 | Not Covered | |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 1 | 50.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 1 | 50.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 55 | 55 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 55 | 55 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 1 | 14.29 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 1 | 16.67 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 0 | 1 | |
65 | 0 | 1 | |
66 | 0 | 1 | |
67 | 0 | 1 | |
==> MISSING_ELSE | |||
72 | 0 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 1 | 33.33 | |
IF | 63 | 3 | 1 | 33.33 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Not Covered | |
1 | 0 | Not Covered | |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 1 | 50.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 1 | 50.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 55 | 55 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 55 | 55 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 1 | 14.29 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 1 | 16.67 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 0 | 1 | |
65 | 0 | 1 | |
66 | 0 | 1 | |
67 | 0 | 1 | |
==> MISSING_ELSE | |||
72 | 0 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 1 | 33.33 | |
IF | 63 | 3 | 1 | 33.33 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Not Covered | |
1 | 0 | Not Covered | |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 1 | 50.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 1 | 50.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 55 | 55 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 55 | 55 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 1 | 14.29 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 1 | 16.67 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 0 | 1 | |
65 | 0 | 1 | |
66 | 0 | 1 | |
67 | 0 | 1 | |
==> MISSING_ELSE | |||
72 | 0 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 1 | 33.33 | |
IF | 63 | 3 | 1 | 33.33 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Not Covered | |
1 | 0 | Not Covered | |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 1 | 50.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 1 | 50.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 55 | 55 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 55 | 55 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 1 | 14.29 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 1 | 16.67 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 0 | 1 | |
65 | 0 | 1 | |
66 | 0 | 1 | |
67 | 0 | 1 | |
==> MISSING_ELSE | |||
72 | 0 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 1 | 33.33 | |
IF | 63 | 3 | 1 | 33.33 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Not Covered | |
1 | 0 | Not Covered | |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 1 | 50.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 1 | 50.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 55 | 55 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 55 | 55 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 1 | 14.29 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 1 | 16.67 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 0 | 1 | |
65 | 0 | 1 | |
66 | 0 | 1 | |
67 | 0 | 1 | |
==> MISSING_ELSE | |||
72 | 0 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 1 | 33.33 | |
IF | 63 | 3 | 1 | 33.33 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Not Covered | |
1 | 0 | Not Covered | |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 1 | 50.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 1 | 50.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 55 | 55 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 55 | 55 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 1 | 14.29 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 1 | 16.67 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 0 | 1 | |
65 | 0 | 1 | |
66 | 0 | 1 | |
67 | 0 | 1 | |
==> MISSING_ELSE | |||
72 | 0 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 1 | 33.33 | |
IF | 63 | 3 | 1 | 33.33 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Not Covered | |
1 | 0 | Not Covered | |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 1 | 50.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 1 | 50.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 55 | 55 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 55 | 55 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 1 | 14.29 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 1 | 16.67 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 0 | 1 | |
65 | 0 | 1 | |
66 | 0 | 1 | |
67 | 0 | 1 | |
==> MISSING_ELSE | |||
72 | 0 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 1 | 33.33 | |
IF | 63 | 3 | 1 | 33.33 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Not Covered | |
1 | 0 | Not Covered | |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 1 | 50.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 1 | 50.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 55 | 55 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 55 | 55 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 1 | 14.29 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 1 | 16.67 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 0 | 1 | |
65 | 0 | 1 | |
66 | 0 | 1 | |
67 | 0 | 1 | |
==> MISSING_ELSE | |||
72 | 0 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 1 | 33.33 | |
IF | 63 | 3 | 1 | 33.33 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Not Covered | |
1 | 0 | Not Covered | |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 1 | 50.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 1 | 50.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 55 | 55 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 55 | 55 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 1 | 14.29 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 1 | 16.67 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 0 | 1 | |
65 | 0 | 1 | |
66 | 0 | 1 | |
67 | 0 | 1 | |
==> MISSING_ELSE | |||
72 | 0 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 1 | 33.33 | |
IF | 63 | 3 | 1 | 33.33 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Not Covered | |
1 | 0 | Not Covered | |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 1 | 50.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 1 | 50.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 55 | 55 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 55 | 55 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 1 | 14.29 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 1 | 16.67 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 0 | 1 | |
65 | 0 | 1 | |
66 | 0 | 1 | |
67 | 0 | 1 | |
==> MISSING_ELSE | |||
72 | 0 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 1 | 33.33 | |
IF | 63 | 3 | 1 | 33.33 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Not Covered | |
1 | 0 | Not Covered | |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 1 | 50.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 1 | 50.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 55 | 55 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 55 | 55 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 1 | 14.29 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 1 | 16.67 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 0 | 1 | |
65 | 0 | 1 | |
66 | 0 | 1 | |
67 | 0 | 1 | |
==> MISSING_ELSE | |||
72 | 0 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 1 | 33.33 | |
IF | 63 | 3 | 1 | 33.33 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Not Covered | |
1 | 0 | Not Covered | |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 1 | 50.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 1 | 50.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 55 | 55 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 1495666 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 55 | 55 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 0 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 55 | 55 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 1495666 | 655198 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 55 | 55 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 655198 | 0 | 0 |
T1 | 5603 | 2150 | 0 | 0 |
T2 | 6283 | 2550 | 0 | 0 |
T3 | 3688 | 1850 | 0 | 0 |
T4 | 86174 | 4850 | 0 | 0 |
T5 | 29585 | 6100 | 0 | 0 |
T6 | 15992 | 3100 | 0 | 0 |
T7 | 138869 | 133470 | 0 | 0 |
T8 | 218850 | 4250 | 0 | 0 |
T10 | 18880 | 6050 | 0 | 0 |
T12 | 7442 | 600 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 55 | 55 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 1495666 | 655198 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 55 | 55 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 655198 | 0 | 0 |
T1 | 5603 | 2150 | 0 | 0 |
T2 | 6283 | 2550 | 0 | 0 |
T3 | 3688 | 1850 | 0 | 0 |
T4 | 86174 | 4850 | 0 | 0 |
T5 | 29585 | 6100 | 0 | 0 |
T6 | 15992 | 3100 | 0 | 0 |
T7 | 138869 | 133470 | 0 | 0 |
T8 | 218850 | 4250 | 0 | 0 |
T10 | 18880 | 6050 | 0 | 0 |
T12 | 7442 | 600 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 55 | 55 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 1495666 | 539936 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 55 | 55 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 539936 | 0 | 0 |
T1 | 5603 | 1500 | 0 | 0 |
T3 | 3688 | 350 | 0 | 0 |
T4 | 86174 | 71322 | 0 | 0 |
T5 | 29585 | 8400 | 0 | 0 |
T6 | 15992 | 8450 | 0 | 0 |
T7 | 138869 | 3400 | 0 | 0 |
T8 | 218850 | 203868 | 0 | 0 |
T9 | 2911 | 350 | 0 | 0 |
T10 | 18880 | 7250 | 0 | 0 |
T11 | 4329 | 1750 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 55 | 55 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 1495666 | 539936 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 55 | 55 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1495666 | 539936 | 0 | 0 |
T1 | 5603 | 1500 | 0 | 0 |
T3 | 3688 | 350 | 0 | 0 |
T4 | 86174 | 71322 | 0 | 0 |
T5 | 29585 | 8400 | 0 | 0 |
T6 | 15992 | 8450 | 0 | 0 |
T7 | 138869 | 3400 | 0 | 0 |
T8 | 218850 | 203868 | 0 | 0 |
T9 | 2911 | 350 | 0 | 0 |
T10 | 18880 | 7250 | 0 | 0 |
T11 | 4329 | 1750 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |