Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.i_valid_random

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.51 100.00 50.00 54.55 37.50


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.51 100.00 50.00 54.55 37.50


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
77.93 98.23 55.00 67.57 90.91 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.i_valid_random

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.51 100.00 50.00 54.55 37.50


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.51 100.00 50.00 54.55 37.50


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
77.93 98.23 55.00 67.57 90.91 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_arbiter_tree
Line No.TotalCoveredPercent
TOTAL4848100.00
CONT_ASSIGN6200
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16300
CONT_ASSIGN16300
CONT_ASSIGN16311100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
ALWAYS19133100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 unreachable
112 4 4
118 4 4
126 4 4
128 4 4
148 3 3
150 3 3
151 3 3
155 3 3
156 3 3
160 3 3
161 3 3
163 1 1(2 unreachable)
164 3 3
171 1 1
180 1 1
182 1 1
183 1 1
191 1 1
192 1 1
194 1 1


Cond Coverage for Module : prim_arbiter_tree
TotalCoveredPercent
Conditions201050.00
Logical201050.00
Non-Logical00
Event00

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? ((gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & (~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? ((gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & (~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? ((gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & (~ready_i)))) : gen_normal_case.prio_mask_q[2])
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? ((gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & (~ready_i)))) : gen_normal_case.prio_mask_q[3])
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Branch Coverage for Module : prim_arbiter_tree
Line No.TotalCoveredPercent
Branches 22 12 54.55
TERNARY 155 2 1 50.00
TERNARY 156 2 1 50.00
TERNARY 155 2 1 50.00
TERNARY 156 2 1 50.00
TERNARY 155 2 1 50.00
TERNARY 156 2 1 50.00
TERNARY 128 2 1 50.00
TERNARY 128 2 1 50.00
TERNARY 128 2 1 50.00
TERNARY 128 2 1 50.00
IF 191 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 191 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_arbiter_tree
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 6 37.50
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 6 37.50




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 2991332 2982830 0 0
CheckNGreaterZero_A 110 110 0 0
GntImpliesReady_A 2991332 0 0 0
GntImpliesValid_A 2991332 0 0 0
GrantKnown_A 2991332 2982830 0 0
IdxKnown_A 2991332 2982830 0 0
IndexIsCorrect_A 2991332 0 0 0
LockArbDecision_A 2991332 0 0 0
NoReadyValidNoGrant_A 2991332 2973271 0 0
ReadyAndValidImplyGrant_A 2991332 0 0 0
ReqAndReadyImplyGrant_A 2991332 0 0 0
ReqImpliesValid_A 2991332 0 0 0
ReqStaysHighUntilGranted0_M 2991332 0 0 0
RoundRobin_A 2991332 0 0 110
ValidKnown_A 2991332 2982830 0 0
gen_data_port_assertion.DataFlow_A 2991332 0 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2991332 2982830 0 0
T1 11206 11026 0 0
T2 12566 12400 0 0
T3 7376 7192 0 0
T4 172348 172192 0 0
T5 59170 59038 0 0
T6 31984 31822 0 0
T7 277738 277594 0 0
T8 437700 437592 0 0
T9 5822 5648 0 0
T10 37760 37568 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 110 110 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T6 2 2 0 0
T7 2 2 0 0
T8 2 2 0 0
T9 2 2 0 0
T10 2 2 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2991332 0 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2991332 0 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2991332 2982830 0 0
T1 11206 11026 0 0
T2 12566 12400 0 0
T3 7376 7192 0 0
T4 172348 172192 0 0
T5 59170 59038 0 0
T6 31984 31822 0 0
T7 277738 277594 0 0
T8 437700 437592 0 0
T9 5822 5648 0 0
T10 37760 37568 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2991332 2982830 0 0
T1 11206 11026 0 0
T2 12566 12400 0 0
T3 7376 7192 0 0
T4 172348 172192 0 0
T5 59170 59038 0 0
T6 31984 31822 0 0
T7 277738 277594 0 0
T8 437700 437592 0 0
T9 5822 5648 0 0
T10 37760 37568 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2991332 0 0 0

LockArbDecision_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2991332 0 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2991332 2973271 0 0
T1 11206 10897 0 0
T2 12566 12354 0 0
T3 7376 7155 0 0
T4 172348 171949 0 0
T5 59170 58644 0 0
T6 31984 31450 0 0
T7 277738 277497 0 0
T8 437700 437301 0 0
T9 5822 5636 0 0
T10 37760 37101 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2991332 0 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2991332 0 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2991332 0 0 0

ReqStaysHighUntilGranted0_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2991332 0 0 0

RoundRobin_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2991332 0 0 110

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2991332 2982830 0 0
T1 11206 11026 0 0
T2 12566 12400 0 0
T3 7376 7192 0 0
T4 172348 172192 0 0
T5 59170 59038 0 0
T6 31984 31822 0 0
T7 277738 277594 0 0
T8 437700 437592 0 0
T9 5822 5648 0 0
T10 37760 37568 0 0

gen_data_port_assertion.DataFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2991332 0 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.i_valid_random
Line No.TotalCoveredPercent
TOTAL4848100.00
CONT_ASSIGN6200
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16300
CONT_ASSIGN16300
CONT_ASSIGN16311100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
ALWAYS19133100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 unreachable
112 4 4
118 4 4
126 4 4
128 4 4
148 3 3
150 3 3
151 3 3
155 3 3
156 3 3
160 3 3
161 3 3
163 1 1(2 unreachable)
164 3 3
171 1 1
180 1 1
182 1 1
183 1 1
191 1 1
192 1 1
194 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.i_valid_random
TotalCoveredPercent
Conditions201050.00
Logical201050.00
Non-Logical00
Event00

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? ((gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & (~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? ((gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & (~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? ((gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & (~ready_i)))) : gen_normal_case.prio_mask_q[2])
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? ((gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & (~ready_i)))) : gen_normal_case.prio_mask_q[3])
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.i_valid_random
Line No.TotalCoveredPercent
Branches 22 12 54.55
TERNARY 155 2 1 50.00
TERNARY 156 2 1 50.00
TERNARY 155 2 1 50.00
TERNARY 156 2 1 50.00
TERNARY 155 2 1 50.00
TERNARY 156 2 1 50.00
TERNARY 128 2 1 50.00
TERNARY 128 2 1 50.00
TERNARY 128 2 1 50.00
TERNARY 128 2 1 50.00
IF 191 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 191 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.i_valid_random
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 6 37.50
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 6 37.50




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 1495666 1491415 0 0
CheckNGreaterZero_A 55 55 0 0
GntImpliesReady_A 1495666 0 0 0
GntImpliesValid_A 1495666 0 0 0
GrantKnown_A 1495666 1491415 0 0
IdxKnown_A 1495666 1491415 0 0
IndexIsCorrect_A 1495666 0 0 0
LockArbDecision_A 1495666 0 0 0
NoReadyValidNoGrant_A 1495666 1486828 0 0
ReadyAndValidImplyGrant_A 1495666 0 0 0
ReqAndReadyImplyGrant_A 1495666 0 0 0
ReqImpliesValid_A 1495666 0 0 0
ReqStaysHighUntilGranted0_M 1495666 0 0 0
RoundRobin_A 1495666 0 0 55
ValidKnown_A 1495666 1491415 0 0
gen_data_port_assertion.DataFlow_A 1495666 0 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 1491415 0 0
T1 5603 5513 0 0
T2 6283 6200 0 0
T3 3688 3596 0 0
T4 86174 86096 0 0
T5 29585 29519 0 0
T6 15992 15911 0 0
T7 138869 138797 0 0
T8 218850 218796 0 0
T9 2911 2824 0 0
T10 18880 18784 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 0 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 0 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 1491415 0 0
T1 5603 5513 0 0
T2 6283 6200 0 0
T3 3688 3596 0 0
T4 86174 86096 0 0
T5 29585 29519 0 0
T6 15992 15911 0 0
T7 138869 138797 0 0
T8 218850 218796 0 0
T9 2911 2824 0 0
T10 18880 18784 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 1491415 0 0
T1 5603 5513 0 0
T2 6283 6200 0 0
T3 3688 3596 0 0
T4 86174 86096 0 0
T5 29585 29519 0 0
T6 15992 15911 0 0
T7 138869 138797 0 0
T8 218850 218796 0 0
T9 2911 2824 0 0
T10 18880 18784 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 0 0 0

LockArbDecision_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 0 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 1486828 0 0
T1 5603 5494 0 0
T2 6283 6154 0 0
T3 3688 3571 0 0
T4 86174 85940 0 0
T5 29585 29347 0 0
T6 15992 15839 0 0
T7 138869 138789 0 0
T8 218850 218678 0 0
T9 2911 2824 0 0
T10 18880 18569 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 0 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 0 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 0 0 0

ReqStaysHighUntilGranted0_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 0 0 0

RoundRobin_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 0 0 55

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 1491415 0 0
T1 5603 5513 0 0
T2 6283 6200 0 0
T3 3688 3596 0 0
T4 86174 86096 0 0
T5 29585 29519 0 0
T6 15992 15911 0 0
T7 138869 138797 0 0
T8 218850 218796 0 0
T9 2911 2824 0 0
T10 18880 18784 0 0

gen_data_port_assertion.DataFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 0 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.i_valid_random
Line No.TotalCoveredPercent
TOTAL4848100.00
CONT_ASSIGN6200
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16300
CONT_ASSIGN16300
CONT_ASSIGN16311100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
ALWAYS19133100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 unreachable
112 4 4
118 4 4
126 4 4
128 4 4
148 3 3
150 3 3
151 3 3
155 3 3
156 3 3
160 3 3
161 3 3
163 1 1(2 unreachable)
164 3 3
171 1 1
180 1 1
182 1 1
183 1 1
191 1 1
192 1 1
194 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.i_valid_random
TotalCoveredPercent
Conditions201050.00
Logical201050.00
Non-Logical00
Event00

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? ((gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & (~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? ((gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & (~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? ((gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & (~ready_i)))) : gen_normal_case.prio_mask_q[2])
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? ((gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & (~ready_i)))) : gen_normal_case.prio_mask_q[3])
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.i_valid_random
Line No.TotalCoveredPercent
Branches 22 12 54.55
TERNARY 155 2 1 50.00
TERNARY 156 2 1 50.00
TERNARY 155 2 1 50.00
TERNARY 156 2 1 50.00
TERNARY 155 2 1 50.00
TERNARY 156 2 1 50.00
TERNARY 128 2 1 50.00
TERNARY 128 2 1 50.00
TERNARY 128 2 1 50.00
TERNARY 128 2 1 50.00
IF 191 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 191 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.i_valid_random
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 6 37.50
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 6 37.50




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 1495666 1491415 0 0
CheckNGreaterZero_A 55 55 0 0
GntImpliesReady_A 1495666 0 0 0
GntImpliesValid_A 1495666 0 0 0
GrantKnown_A 1495666 1491415 0 0
IdxKnown_A 1495666 1491415 0 0
IndexIsCorrect_A 1495666 0 0 0
LockArbDecision_A 1495666 0 0 0
NoReadyValidNoGrant_A 1495666 1486443 0 0
ReadyAndValidImplyGrant_A 1495666 0 0 0
ReqAndReadyImplyGrant_A 1495666 0 0 0
ReqImpliesValid_A 1495666 0 0 0
ReqStaysHighUntilGranted0_M 1495666 0 0 0
RoundRobin_A 1495666 0 0 55
ValidKnown_A 1495666 1491415 0 0
gen_data_port_assertion.DataFlow_A 1495666 0 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 1491415 0 0
T1 5603 5513 0 0
T2 6283 6200 0 0
T3 3688 3596 0 0
T4 86174 86096 0 0
T5 29585 29519 0 0
T6 15992 15911 0 0
T7 138869 138797 0 0
T8 218850 218796 0 0
T9 2911 2824 0 0
T10 18880 18784 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 0 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 0 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 1491415 0 0
T1 5603 5513 0 0
T2 6283 6200 0 0
T3 3688 3596 0 0
T4 86174 86096 0 0
T5 29585 29519 0 0
T6 15992 15911 0 0
T7 138869 138797 0 0
T8 218850 218796 0 0
T9 2911 2824 0 0
T10 18880 18784 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 1491415 0 0
T1 5603 5513 0 0
T2 6283 6200 0 0
T3 3688 3596 0 0
T4 86174 86096 0 0
T5 29585 29519 0 0
T6 15992 15911 0 0
T7 138869 138797 0 0
T8 218850 218796 0 0
T9 2911 2824 0 0
T10 18880 18784 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 0 0 0

LockArbDecision_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 0 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 1486443 0 0
T1 5603 5403 0 0
T2 6283 6200 0 0
T3 3688 3584 0 0
T4 86174 86009 0 0
T5 29585 29297 0 0
T6 15992 15611 0 0
T7 138869 138708 0 0
T8 218850 218623 0 0
T9 2911 2812 0 0
T10 18880 18532 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 0 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 0 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 0 0 0

ReqStaysHighUntilGranted0_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 0 0 0

RoundRobin_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 0 0 55

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 1491415 0 0
T1 5603 5513 0 0
T2 6283 6200 0 0
T3 3688 3596 0 0
T4 86174 86096 0 0
T5 29585 29519 0 0
T6 15992 15911 0 0
T7 138869 138797 0 0
T8 218850 218796 0 0
T9 2911 2824 0 0
T10 18880 18784 0 0

gen_data_port_assertion.DataFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%