Module Definition
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Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_erase

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.68 100.00 83.33 85.71


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.68 100.00 83.33 85.71


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
69.44 98.61 58.33 60.00 70.27 60.00 gen_flash_cores[0].u_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_erase

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.68 100.00 83.33 85.71


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.68 100.00 83.33 85.71


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
69.44 98.61 58.33 60.00 70.27 60.00 gen_flash_cores[1].u_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : flash_phy_erase
Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS3533100.00
ALWAYS431010100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_erase.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_erase.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
35 1 1
36 1 1
38 1 1
43 1 1
44 1 1
45 1 1
47 1 1
49 1 1
51 1 1
52 1 1
MISSING_ELSE
57 1 1
58 1 1
59 1 1
MISSING_ELSE
67 1 1
68 1 1


Cond Coverage for Module : flash_phy_erase
TotalCoveredPercent
Conditions6583.33
Logical6583.33
Non-Logical00
Event00

 LINE       51
 EXPRESSION ((pg_erase_req_o || bk_erase_req_o) && ack_i)
             -----------------1----------------    --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT4,T7,T8

 LINE       51
 SUB-EXPRESSION (pg_erase_req_o || bk_erase_req_o)
                 -------1------    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T7,T8
10CoveredT4,T7,T8

Branch Coverage for Module : flash_phy_erase
Line No.TotalCoveredPercent
Branches 7 6 85.71
IF 35 2 2 100.00
CASE 47 5 4 80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_erase.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_erase.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 35 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 47 case (state_q) -2-: 51 if (((pg_erase_req_o || bk_erase_req_o) && ack_i)) -3-: 57 if (done_i)

Branches:
-1--2--3-StatusTests
StEraseIdle 1 - Covered T1,T2,T3
StEraseIdle 0 - Covered T1,T2,T3
StEraseBusy - 1 Covered T1,T2,T3
StEraseBusy - 0 Covered T1,T2,T3
default - - Not Covered

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_erase
Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS3533100.00
ALWAYS431010100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_erase.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_erase.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
35 1 1
36 1 1
38 1 1
43 1 1
44 1 1
45 1 1
47 1 1
49 1 1
51 1 1
52 1 1
MISSING_ELSE
57 1 1
58 1 1
59 1 1
MISSING_ELSE
67 1 1
68 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_erase
TotalCoveredPercent
Conditions6583.33
Logical6583.33
Non-Logical00
Event00

 LINE       51
 EXPRESSION ((pg_erase_req_o || bk_erase_req_o) && ack_i)
             -----------------1----------------    --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT7,T25,T26

 LINE       51
 SUB-EXPRESSION (pg_erase_req_o || bk_erase_req_o)
                 -------1------    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT7,T25,T26
10CoveredT7,T25,T26

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_erase
Line No.TotalCoveredPercent
Branches 7 6 85.71
IF 35 2 2 100.00
CASE 47 5 4 80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_erase.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_erase.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 35 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 47 case (state_q) -2-: 51 if (((pg_erase_req_o || bk_erase_req_o) && ack_i)) -3-: 57 if (done_i)

Branches:
-1--2--3-StatusTests
StEraseIdle 1 - Covered T1,T2,T3
StEraseIdle 0 - Covered T1,T2,T3
StEraseBusy - 1 Covered T1,T2,T3
StEraseBusy - 0 Covered T1,T2,T3
default - - Not Covered

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_erase
Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS3533100.00
ALWAYS431010100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_erase.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_erase.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
35 1 1
36 1 1
38 1 1
43 1 1
44 1 1
45 1 1
47 1 1
49 1 1
51 1 1
52 1 1
MISSING_ELSE
57 1 1
58 1 1
59 1 1
MISSING_ELSE
67 1 1
68 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_erase
TotalCoveredPercent
Conditions6583.33
Logical6583.33
Non-Logical00
Event00

 LINE       51
 EXPRESSION ((pg_erase_req_o || bk_erase_req_o) && ack_i)
             -----------------1----------------    --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT4,T8,T27

 LINE       51
 SUB-EXPRESSION (pg_erase_req_o || bk_erase_req_o)
                 -------1------    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T8,T27
10CoveredT4,T8,T27

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_erase
Line No.TotalCoveredPercent
Branches 7 6 85.71
IF 35 2 2 100.00
CASE 47 5 4 80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_erase.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_erase.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 35 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 47 case (state_q) -2-: 51 if (((pg_erase_req_o || bk_erase_req_o) && ack_i)) -3-: 57 if (done_i)

Branches:
-1--2--3-StatusTests
StEraseIdle 1 - Covered T1,T2,T3
StEraseIdle 0 - Covered T1,T2,T3
StEraseBusy - 1 Covered T1,T2,T3
StEraseBusy - 0 Covered T1,T2,T3
default - - Not Covered

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