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Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
fifo_h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
fifo_h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dfifo[0].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dfifo[0].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dfifo[1].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dfifo[1].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dfifo[2].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dfifo[2].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo
Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5100
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 1 1
43 1 1
46 1 1
47 1 1
51 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 11870838 3016641 0 0
DepthKnown_A 11870838 11422025 0 0
RvalidKnown_A 11870838 11422025 0 0
WreadyKnown_A 11870838 11422025 0 0
gen_passthru_fifo.paramCheckPass 280 280 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11870838 3016641 0 0
T1 5603 2698 0 0
T2 6283 545 0 0
T3 3688 1758 0 0
T4 86174 12296 0 0
T5 29585 2794 0 0
T6 15992 8064 0 0
T7 138869 69390 0 0
T8 218850 31218 0 0
T9 2911 214 0 0
T10 18880 9404 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11870838 11422025 0 0
T1 5603 5513 0 0
T2 6283 6200 0 0
T3 3688 3596 0 0
T4 86174 86096 0 0
T5 29585 29519 0 0
T6 15992 15911 0 0
T7 138869 138797 0 0
T8 218850 218796 0 0
T9 2911 2824 0 0
T10 18880 18784 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11870838 11422025 0 0
T1 5603 5513 0 0
T2 6283 6200 0 0
T3 3688 3596 0 0
T4 86174 86096 0 0
T5 29585 29519 0 0
T6 15992 15911 0 0
T7 138869 138797 0 0
T8 218850 218796 0 0
T9 2911 2824 0 0
T10 18880 18784 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11870838 11422025 0 0
T1 5603 5513 0 0
T2 6283 6200 0 0
T3 3688 3596 0 0
T4 86174 86096 0 0
T5 29585 29519 0 0
T6 15992 15911 0 0
T7 138869 138797 0 0
T8 218850 218796 0 0
T9 2911 2824 0 0
T10 18880 18784 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 280 280 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5100
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 1 1
43 1 1
46 1 1
47 1 1
51 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 11870838 4228554 0 0
DepthKnown_A 11870838 11422025 0 0
RvalidKnown_A 11870838 11422025 0 0
WreadyKnown_A 11870838 11422025 0 0
gen_passthru_fifo.paramCheckPass 280 280 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11870838 4228554 0 0
T1 5603 2563 0 0
T2 6283 2364 0 0
T3 3688 1712 0 0
T4 86174 12281 0 0
T5 29585 12680 0 0
T6 15992 7683 0 0
T7 138869 69281 0 0
T8 218850 31203 0 0
T9 2911 985 0 0
T10 18880 8879 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11870838 11422025 0 0
T1 5603 5513 0 0
T2 6283 6200 0 0
T3 3688 3596 0 0
T4 86174 86096 0 0
T5 29585 29519 0 0
T6 15992 15911 0 0
T7 138869 138797 0 0
T8 218850 218796 0 0
T9 2911 2824 0 0
T10 18880 18784 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11870838 11422025 0 0
T1 5603 5513 0 0
T2 6283 6200 0 0
T3 3688 3596 0 0
T4 86174 86096 0 0
T5 29585 29519 0 0
T6 15992 15911 0 0
T7 138869 138797 0 0
T8 218850 218796 0 0
T9 2911 2824 0 0
T10 18880 18784 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11870838 11422025 0 0
T1 5603 5513 0 0
T2 6283 6200 0 0
T3 3688 3596 0 0
T4 86174 86096 0 0
T5 29585 29519 0 0
T6 15992 15911 0 0
T7 138869 138797 0 0
T8 218850 218796 0 0
T9 2911 2824 0 0
T10 18880 18784 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 280 280 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5100
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 1 1
43 1 1
46 1 1
47 1 1
51 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 11870838 14210 0 0
DepthKnown_A 11870838 11422025 0 0
RvalidKnown_A 11870838 11422025 0 0
WreadyKnown_A 11870838 11422025 0 0
gen_passthru_fifo.paramCheckPass 280 280 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11870838 14210 0 0
T1 5603 123 0 0
T2 6283 92 0 0
T3 3688 71 0 0
T4 86174 327 0 0
T5 29585 522 0 0
T6 15992 420 0 0
T7 138869 128 0 0
T8 218850 315 0 0
T9 2911 14 0 0
T10 18880 488 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11870838 11422025 0 0
T1 5603 5513 0 0
T2 6283 6200 0 0
T3 3688 3596 0 0
T4 86174 86096 0 0
T5 29585 29519 0 0
T6 15992 15911 0 0
T7 138869 138797 0 0
T8 218850 218796 0 0
T9 2911 2824 0 0
T10 18880 18784 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11870838 11422025 0 0
T1 5603 5513 0 0
T2 6283 6200 0 0
T3 3688 3596 0 0
T4 86174 86096 0 0
T5 29585 29519 0 0
T6 15992 15911 0 0
T7 138869 138797 0 0
T8 218850 218796 0 0
T9 2911 2824 0 0
T10 18880 18784 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11870838 11422025 0 0
T1 5603 5513 0 0
T2 6283 6200 0 0
T3 3688 3596 0 0
T4 86174 86096 0 0
T5 29585 29519 0 0
T6 15992 15911 0 0
T7 138869 138797 0 0
T8 218850 218796 0 0
T9 2911 2824 0 0
T10 18880 18784 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 280 280 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5100
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 1 1
43 1 1
46 1 1
47 1 1
51 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 11870838 31259 0 0
DepthKnown_A 11870838 11422025 0 0
RvalidKnown_A 11870838 11422025 0 0
WreadyKnown_A 11870838 11422025 0 0
gen_passthru_fifo.paramCheckPass 280 280 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11870838 31259 0 0
T1 5603 123 0 0
T2 6283 411 0 0
T3 3688 71 0 0
T4 86174 327 0 0
T5 29585 2372 0 0
T6 15992 420 0 0
T7 138869 128 0 0
T8 218850 315 0 0
T9 2911 79 0 0
T10 18880 488 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11870838 11422025 0 0
T1 5603 5513 0 0
T2 6283 6200 0 0
T3 3688 3596 0 0
T4 86174 86096 0 0
T5 29585 29519 0 0
T6 15992 15911 0 0
T7 138869 138797 0 0
T8 218850 218796 0 0
T9 2911 2824 0 0
T10 18880 18784 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11870838 11422025 0 0
T1 5603 5513 0 0
T2 6283 6200 0 0
T3 3688 3596 0 0
T4 86174 86096 0 0
T5 29585 29519 0 0
T6 15992 15911 0 0
T7 138869 138797 0 0
T8 218850 218796 0 0
T9 2911 2824 0 0
T10 18880 18784 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11870838 11422025 0 0
T1 5603 5513 0 0
T2 6283 6200 0 0
T3 3688 3596 0 0
T4 86174 86096 0 0
T5 29585 29519 0 0
T6 15992 15911 0 0
T7 138869 138797 0 0
T8 218850 218796 0 0
T9 2911 2824 0 0
T10 18880 18784 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 280 280 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5100
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 1 1
43 1 1
46 1 1
47 1 1
51 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 11870838 18543 0 0
DepthKnown_A 11870838 11422025 0 0
RvalidKnown_A 11870838 11422025 0 0
WreadyKnown_A 11870838 11422025 0 0
gen_passthru_fifo.paramCheckPass 280 280 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11870838 18543 0 0
T1 5603 264 0 0
T2 6283 46 0 0
T3 3688 83 0 0
T4 86174 258 0 0
T5 29585 394 0 0
T6 15992 753 0 0
T7 138869 206 0 0
T8 218850 306 0 0
T9 2911 12 0 0
T10 18880 992 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11870838 11422025 0 0
T1 5603 5513 0 0
T2 6283 6200 0 0
T3 3688 3596 0 0
T4 86174 86096 0 0
T5 29585 29519 0 0
T6 15992 15911 0 0
T7 138869 138797 0 0
T8 218850 218796 0 0
T9 2911 2824 0 0
T10 18880 18784 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11870838 11422025 0 0
T1 5603 5513 0 0
T2 6283 6200 0 0
T3 3688 3596 0 0
T4 86174 86096 0 0
T5 29585 29519 0 0
T6 15992 15911 0 0
T7 138869 138797 0 0
T8 218850 218796 0 0
T9 2911 2824 0 0
T10 18880 18784 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11870838 11422025 0 0
T1 5603 5513 0 0
T2 6283 6200 0 0
T3 3688 3596 0 0
T4 86174 86096 0 0
T5 29585 29519 0 0
T6 15992 15911 0 0
T7 138869 138797 0 0
T8 218850 218796 0 0
T9 2911 2824 0 0
T10 18880 18784 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 280 280 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5100
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 1 1
43 1 1
46 1 1
47 1 1
51 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 11870838 32651 0 0
DepthKnown_A 11870838 11422025 0 0
RvalidKnown_A 11870838 11422025 0 0
WreadyKnown_A 11870838 11422025 0 0
gen_passthru_fifo.paramCheckPass 280 280 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11870838 32651 0 0
T1 5603 129 0 0
T2 6283 201 0 0
T3 3688 37 0 0
T4 86174 243 0 0
T5 29585 1727 0 0
T6 15992 372 0 0
T7 138869 97 0 0
T8 218850 291 0 0
T9 2911 48 0 0
T10 18880 467 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11870838 11422025 0 0
T1 5603 5513 0 0
T2 6283 6200 0 0
T3 3688 3596 0 0
T4 86174 86096 0 0
T5 29585 29519 0 0
T6 15992 15911 0 0
T7 138869 138797 0 0
T8 218850 218796 0 0
T9 2911 2824 0 0
T10 18880 18784 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11870838 11422025 0 0
T1 5603 5513 0 0
T2 6283 6200 0 0
T3 3688 3596 0 0
T4 86174 86096 0 0
T5 29585 29519 0 0
T6 15992 15911 0 0
T7 138869 138797 0 0
T8 218850 218796 0 0
T9 2911 2824 0 0
T10 18880 18784 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11870838 11422025 0 0
T1 5603 5513 0 0
T2 6283 6200 0 0
T3 3688 3596 0 0
T4 86174 86096 0 0
T5 29585 29519 0 0
T6 15992 15911 0 0
T7 138869 138797 0 0
T8 218850 218796 0 0
T9 2911 2824 0 0
T10 18880 18784 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 280 280 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5100
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 1 1
43 1 1
46 1 1
47 1 1
51 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 11870838 2974284 0 0
DepthKnown_A 11870838 11422025 0 0
RvalidKnown_A 11870838 11422025 0 0
WreadyKnown_A 11870838 11422025 0 0
gen_passthru_fifo.paramCheckPass 280 280 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11870838 2974284 0 0
T1 5603 2311 0 0
T2 6283 407 0 0
T3 3688 1604 0 0
T4 86174 11711 0 0
T5 29585 1878 0 0
T6 15992 6891 0 0
T7 138869 69056 0 0
T8 218850 30597 0 0
T9 2911 188 0 0
T10 18880 7924 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11870838 11422025 0 0
T1 5603 5513 0 0
T2 6283 6200 0 0
T3 3688 3596 0 0
T4 86174 86096 0 0
T5 29585 29519 0 0
T6 15992 15911 0 0
T7 138869 138797 0 0
T8 218850 218796 0 0
T9 2911 2824 0 0
T10 18880 18784 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11870838 11422025 0 0
T1 5603 5513 0 0
T2 6283 6200 0 0
T3 3688 3596 0 0
T4 86174 86096 0 0
T5 29585 29519 0 0
T6 15992 15911 0 0
T7 138869 138797 0 0
T8 218850 218796 0 0
T9 2911 2824 0 0
T10 18880 18784 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11870838 11422025 0 0
T1 5603 5513 0 0
T2 6283 6200 0 0
T3 3688 3596 0 0
T4 86174 86096 0 0
T5 29585 29519 0 0
T6 15992 15911 0 0
T7 138869 138797 0 0
T8 218850 218796 0 0
T9 2911 2824 0 0
T10 18880 18784 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 280 280 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5100
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 1 1
43 1 1
46 1 1
47 1 1
51 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 11870838 4164644 0 0
DepthKnown_A 11870838 11422025 0 0
RvalidKnown_A 11870838 11422025 0 0
WreadyKnown_A 11870838 11422025 0 0
gen_passthru_fifo.paramCheckPass 280 280 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11870838 4164644 0 0
T1 5603 2311 0 0
T2 6283 1752 0 0
T3 3688 1604 0 0
T4 86174 11711 0 0
T5 29585 8581 0 0
T6 15992 6891 0 0
T7 138869 69056 0 0
T8 218850 30597 0 0
T9 2911 858 0 0
T10 18880 7924 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11870838 11422025 0 0
T1 5603 5513 0 0
T2 6283 6200 0 0
T3 3688 3596 0 0
T4 86174 86096 0 0
T5 29585 29519 0 0
T6 15992 15911 0 0
T7 138869 138797 0 0
T8 218850 218796 0 0
T9 2911 2824 0 0
T10 18880 18784 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11870838 11422025 0 0
T1 5603 5513 0 0
T2 6283 6200 0 0
T3 3688 3596 0 0
T4 86174 86096 0 0
T5 29585 29519 0 0
T6 15992 15911 0 0
T7 138869 138797 0 0
T8 218850 218796 0 0
T9 2911 2824 0 0
T10 18880 18784 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11870838 11422025 0 0
T1 5603 5513 0 0
T2 6283 6200 0 0
T3 3688 3596 0 0
T4 86174 86096 0 0
T5 29585 29519 0 0
T6 15992 15911 0 0
T7 138869 138797 0 0
T8 218850 218796 0 0
T9 2911 2824 0 0
T10 18880 18784 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 280 280 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%