Unified Coverage Report :: Module Instance :: tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_reqfifo

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
59.44	77.78	50.00			50.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
59.44	77.78	50.00			50.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
62.46	63.16	33.33			70.00	83.33	u_cfg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
59.44	77.78	50.00			50.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
59.44	77.78	50.00			50.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
62.46	63.16	33.33			70.00	83.33	u_cfg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
59.00	80.56	45.45			50.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
59.00	80.56	45.45			50.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
62.46	63.16	33.33			70.00	83.33	u_cfg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.50	100.00	100.00			90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.50	100.00	100.00			90.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.46	99.29	77.78		61.54	95.24		gen_prim_flash_banks[0].u_prim_flash_bank

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.50	100.00	100.00			90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.50	100.00	100.00			90.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.46	99.29	77.78		61.54	95.24		gen_prim_flash_banks[1].u_prim_flash_bank

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
58.31	77.78	45.45			50.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
58.31	77.78	45.45			50.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
65.48	96.43	50.00			50.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.i_rsp_order_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.08	100.00	83.33			85.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.08	100.00	83.33			85.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
77.93	98.23	55.00			67.57	90.91	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.08	100.00	83.33			85.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.08	100.00	83.33			85.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
77.93	98.23	55.00			67.57	90.91	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		36	28	77.78
ALWAYS	65	4	4	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
ALWAYS	98	7	4	57.14
ALWAYS	112	7	4	57.14
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
ALWAYS	137	2	1	50.00
CONT_ASSIGN	155	1	0	0.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	162	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
66	1	1
67	1	1
68	1	1
			MISSING_ELSE
79	1	1
80	1	1
81	1	1
82	1	1
83	1	1
87	1	1
88	1	1
93	1	1
94	1	1
95	1	1
98	1	1
99	1	1
100	1	1
101		unreachable
102	1	1
103	0	1
104	0	1
106	0	1
			MISSING_ELSE
112	1	1
113	1	1
114	1	1
115		unreachable
116	1	1
117	0	1
118	0	1
120	0	1
			MISSING_ELSE
125	1	1
126	1	1
134	1	1
137	1	1
138	0	1
			MISSING_ELSE
155	0	1
156	1	1
162	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_reqfifo

	Total	Covered	Percent
Conditions	6	3	50.00
Logical	6	3	50.00
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       83
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		20	10	50.00
TERNARY	83	3	1	33.33
TERNARY	160	2	1	50.00
IF	65	3	3	100.00
IF	98	5	2	40.00
IF	112	5	2	40.00
IF	137	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	83	(gen_normal_fifo.full) ? 
-2-:	83	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T3
0	0	Not Covered

	LineNo.	Expression
-1-:	160	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	65	if ((!rst_ni))
-2-:	67	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	98	if ((!rst_ni))
-2-:	100	if (clr_i)
-3-:	102	if (gen_normal_fifo.fifo_incr_wptr)
-4-:	103	if ((gen_normal_fifo.fifo_wptr[0] == 1'((Depth - 1))))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	1	Not Covered
0	0	1	0	Not Covered
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	112	if ((!rst_ni))
-2-:	114	if (clr_i)
-3-:	116	if (gen_normal_fifo.fifo_incr_rptr)
-4-:	117	if ((gen_normal_fifo.fifo_rptr[0] == 1'((Depth - 1))))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	1	Not Covered
0	0	1	0	Not Covered
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	137	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1495666	0	0	0
DepthKnown_A	1495666	1491415	0	0
RvalidKnown_A	1495666	1491415	0	0
WreadyKnown_A	1495666	1491415	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	1495666	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495666	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495666	1491415	0	0
T1	5603	5513	0	0
T2	6283	6200	0	0
T3	3688	3596	0	0
T4	86174	86096	0	0
T5	29585	29519	0	0
T6	15992	15911	0	0
T7	138869	138797	0	0
T8	218850	218796	0	0
T9	2911	2824	0	0
T10	18880	18784	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495666	1491415	0	0
T1	5603	5513	0	0
T2	6283	6200	0	0
T3	3688	3596	0	0
T4	86174	86096	0	0
T5	29585	29519	0	0
T6	15992	15911	0	0
T7	138869	138797	0	0
T8	218850	218796	0	0
T9	2911	2824	0	0
T10	18880	18784	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495666	1491415	0	0
T1	5603	5513	0	0
T2	6283	6200	0	0
T3	3688	3596	0	0
T4	86174	86096	0	0
T5	29585	29519	0	0
T6	15992	15911	0	0
T7	138869	138797	0	0
T8	218850	218796	0	0
T9	2911	2824	0	0
T10	18880	18784	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495666	0	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		36	28	77.78
ALWAYS	65	4	4	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
ALWAYS	98	7	4	57.14
ALWAYS	112	7	4	57.14
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
ALWAYS	137	2	1	50.00
CONT_ASSIGN	155	1	0	0.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	162	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
66	1	1
67	1	1
68	1	1
			MISSING_ELSE
79	1	1
80	1	1
81	1	1
82	1	1
83	1	1
87	1	1
88	1	1
93	1	1
94	1	1
95	1	1
98	1	1
99	1	1
100	1	1
101		unreachable
102	1	1
103	0	1
104	0	1
106	0	1
			MISSING_ELSE
112	1	1
113	1	1
114	1	1
115		unreachable
116	1	1
117	0	1
118	0	1
120	0	1
			MISSING_ELSE
125	1	1
126	1	1
134	1	1
137	1	1
138	0	1
			MISSING_ELSE
155	0	1
156	1	1
162	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_sramreqfifo

	Total	Covered	Percent
Conditions	6	3	50.00
Logical	6	3	50.00
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       83
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		20	10	50.00
TERNARY	83	3	1	33.33
TERNARY	160	2	1	50.00
IF	65	3	3	100.00
IF	98	5	2	40.00
IF	112	5	2	40.00
IF	137	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	83	(gen_normal_fifo.full) ? 
-2-:	83	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T3
0	0	Not Covered

	LineNo.	Expression
-1-:	160	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	65	if ((!rst_ni))
-2-:	67	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	98	if ((!rst_ni))
-2-:	100	if (clr_i)
-3-:	102	if (gen_normal_fifo.fifo_incr_wptr)
-4-:	103	if ((gen_normal_fifo.fifo_wptr[0] == 1'((Depth - 1))))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	1	Not Covered
0	0	1	0	Not Covered
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	112	if ((!rst_ni))
-2-:	114	if (clr_i)
-3-:	116	if (gen_normal_fifo.fifo_incr_rptr)
-4-:	117	if ((gen_normal_fifo.fifo_rptr[0] == 1'((Depth - 1))))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	1	Not Covered
0	0	1	0	Not Covered
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	137	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1495666	0	0	0
DepthKnown_A	1495666	1491415	0	0
RvalidKnown_A	1495666	1491415	0	0
WreadyKnown_A	1495666	1491415	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	1495666	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495666	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495666	1491415	0	0
T1	5603	5513	0	0
T2	6283	6200	0	0
T3	3688	3596	0	0
T4	86174	86096	0	0
T5	29585	29519	0	0
T6	15992	15911	0	0
T7	138869	138797	0	0
T8	218850	218796	0	0
T9	2911	2824	0	0
T10	18880	18784	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495666	1491415	0	0
T1	5603	5513	0	0
T2	6283	6200	0	0
T3	3688	3596	0	0
T4	86174	86096	0	0
T5	29585	29519	0	0
T6	15992	15911	0	0
T7	138869	138797	0	0
T8	218850	218796	0	0
T9	2911	2824	0	0
T10	18880	18784	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495666	1491415	0	0
T1	5603	5513	0	0
T2	6283	6200	0	0
T3	3688	3596	0	0
T4	86174	86096	0	0
T5	29585	29519	0	0
T6	15992	15911	0	0
T7	138869	138797	0	0
T8	218850	218796	0	0
T9	2911	2824	0	0
T10	18880	18784	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495666	0	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		36	29	80.56
ALWAYS	65	4	4	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
ALWAYS	98	7	4	57.14
ALWAYS	112	7	4	57.14
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
ALWAYS	137	2	1	50.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	162	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
66	1	1
67	1	1
68	1	1
			MISSING_ELSE
79	1	1
80	1	1
81	1	1
82	1	1
83	1	1
87	1	1
88	1	1
93	1	1
94	1	1
95	1	1
98	1	1
99	1	1
100	1	1
101		unreachable
102	1	1
103	0	1
104	0	1
106	0	1
			MISSING_ELSE
112	1	1
113	1	1
114	1	1
115		unreachable
116	1	1
117	0	1
118	0	1
120	0	1
			MISSING_ELSE
125	1	1
126	1	1
134	1	1
137	1	1
138	0	1
			MISSING_ELSE
155	1	1
156	1	1
162	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_rspfifo

	Total	Covered	Percent
Conditions	11	5	45.45
Logical	11	5	45.45
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       83
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       152
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       152
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       160
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		22	11	50.00
TERNARY	83	3	1	33.33
TERNARY	152	2	1	50.00
TERNARY	160	2	1	50.00
IF	65	3	3	100.00
IF	98	5	2	40.00
IF	112	5	2	40.00
IF	137	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	83	(gen_normal_fifo.full) ? 
-2-:	83	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T3
0	0	Not Covered

	LineNo.	Expression
-1-:	152	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	160	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	65	if ((!rst_ni))
-2-:	67	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	98	if ((!rst_ni))
-2-:	100	if (clr_i)
-3-:	102	if (gen_normal_fifo.fifo_incr_wptr)
-4-:	103	if ((gen_normal_fifo.fifo_wptr[0] == 1'((Depth - 1))))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	1	Not Covered
0	0	1	0	Not Covered
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	112	if ((!rst_ni))
-2-:	114	if (clr_i)
-3-:	116	if (gen_normal_fifo.fifo_incr_rptr)
-4-:	117	if ((gen_normal_fifo.fifo_rptr[0] == 1'((Depth - 1))))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	1	Not Covered
0	0	1	0	Not Covered
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	137	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1495666	0	0	0
DepthKnown_A	1495666	1491415	0	0
RvalidKnown_A	1495666	1491415	0	0
WreadyKnown_A	1495666	1491415	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	1495666	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495666	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495666	1491415	0	0
T1	5603	5513	0	0
T2	6283	6200	0	0
T3	3688	3596	0	0
T4	86174	86096	0	0
T5	29585	29519	0	0
T6	15992	15911	0	0
T7	138869	138797	0	0
T8	218850	218796	0	0
T9	2911	2824	0	0
T10	18880	18784	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495666	1491415	0	0
T1	5603	5513	0	0
T2	6283	6200	0	0
T3	3688	3596	0	0
T4	86174	86096	0	0
T5	29585	29519	0	0
T6	15992	15911	0	0
T7	138869	138797	0	0
T8	218850	218796	0	0
T9	2911	2824	0	0
T10	18880	18784	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495666	1491415	0	0
T1	5603	5513	0	0
T2	6283	6200	0	0
T3	3688	3596	0	0
T4	86174	86096	0	0
T5	29585	29519	0	0
T6	15992	15911	0	0
T7	138869	138797	0	0
T8	218850	218796	0	0
T9	2911	2824	0	0
T10	18880	18784	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495666	0	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo

	Line No.	Total	Covered	Percent
TOTAL		36	36	100.00
ALWAYS	65	4	4	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
ALWAYS	98	7	7	100.00
ALWAYS	112	7	7	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
ALWAYS	137	2	2	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	162	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
66	1	1
67	1	1
68	1	1
			MISSING_ELSE
79	1	1
80	1	1
81	1	1
82	1	1
83	1	1
87	1	1
88	1	1
93	1	1
94	1	1
95	1	1
98	1	1
99	1	1
100	1	1
101		unreachable
102	1	1
103	1	1
104	1	1
106	1	1
			MISSING_ELSE
112	1	1
113	1	1
114	1	1
115		unreachable
116	1	1
117	1	1
118	1	1
120	1	1
			MISSING_ELSE
125	1	1
126	1	1
134	1	1
137	1	1
138	1	1
			MISSING_ELSE
155	1	1
156	1	1
162	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       83
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	83	3	3	100.00
TERNARY	160	2	2	100.00
IF	65	3	3	100.00
IF	98	5	4	80.00
IF	112	5	4	80.00
IF	137	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	83	(gen_normal_fifo.full) ? 
-2-:	83	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	160	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	65	if ((!rst_ni))
-2-:	67	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	98	if ((!rst_ni))
-2-:	100	if (clr_i)
-3-:	102	if (gen_normal_fifo.fifo_incr_wptr)
-4-:	103	if ((gen_normal_fifo.fifo_wptr[0] == 1'((Depth - 1))))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	1	Covered	T1,T2,T3
0	0	1	0	Covered	T1,T2,T3
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	112	if ((!rst_ni))
-2-:	114	if (clr_i)
-3-:	116	if (gen_normal_fifo.fifo_incr_rptr)
-4-:	117	if ((gen_normal_fifo.fifo_rptr[0] == 1'((Depth - 1))))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	1	Covered	T1,T2,T3
0	0	1	0	Covered	T1,T2,T3
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	137	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1495666	669627	0	0
DepthKnown_A	1495666	1491415	0	0
RvalidKnown_A	1495666	1491415	0	0
WreadyKnown_A	1495666	1491415	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	1495666	669627	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495666	669627	0	0
T1	5603	2341	0	0
T2	6283	2800	0	0
T3	3688	2023	0	0
T4	86174	5394	0	0
T5	29585	6760	0	0
T6	15992	3420	0	0
T7	138869	133526	0	0
T8	218850	4708	0	0
T10	18880	6749	0	0
T12	7442	648	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495666	1491415	0	0
T1	5603	5513	0	0
T2	6283	6200	0	0
T3	3688	3596	0	0
T4	86174	86096	0	0
T5	29585	29519	0	0
T6	15992	15911	0	0
T7	138869	138797	0	0
T8	218850	218796	0	0
T9	2911	2824	0	0
T10	18880	18784	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495666	1491415	0	0
T1	5603	5513	0	0
T2	6283	6200	0	0
T3	3688	3596	0	0
T4	86174	86096	0	0
T5	29585	29519	0	0
T6	15992	15911	0	0
T7	138869	138797	0	0
T8	218850	218796	0	0
T9	2911	2824	0	0
T10	18880	18784	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495666	1491415	0	0
T1	5603	5513	0	0
T2	6283	6200	0	0
T3	3688	3596	0	0
T4	86174	86096	0	0
T5	29585	29519	0	0
T6	15992	15911	0	0
T7	138869	138797	0	0
T8	218850	218796	0	0
T9	2911	2824	0	0
T10	18880	18784	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495666	669627	0	0
T1	5603	2341	0	0
T2	6283	2800	0	0
T3	3688	2023	0	0
T4	86174	5394	0	0
T5	29585	6760	0	0
T6	15992	3420	0	0
T7	138869	133526	0	0
T8	218850	4708	0	0
T10	18880	6749	0	0
T12	7442	648	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo

	Line No.	Total	Covered	Percent
TOTAL		36	36	100.00
ALWAYS	65	4	4	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
ALWAYS	98	7	7	100.00
ALWAYS	112	7	7	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
ALWAYS	137	2	2	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	162	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
66	1	1
67	1	1
68	1	1
			MISSING_ELSE
79	1	1
80	1	1
81	1	1
82	1	1
83	1	1
87	1	1
88	1	1
93	1	1
94	1	1
95	1	1
98	1	1
99	1	1
100	1	1
101		unreachable
102	1	1
103	1	1
104	1	1
106	1	1
			MISSING_ELSE
112	1	1
113	1	1
114	1	1
115		unreachable
116	1	1
117	1	1
118	1	1
120	1	1
			MISSING_ELSE
125	1	1
126	1	1
134	1	1
137	1	1
138	1	1
			MISSING_ELSE
155	1	1
156	1	1
162	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       83
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	83	3	3	100.00
TERNARY	160	2	2	100.00
IF	65	3	3	100.00
IF	98	5	4	80.00
IF	112	5	4	80.00
IF	137	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	83	(gen_normal_fifo.full) ? 
-2-:	83	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	160	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	65	if ((!rst_ni))
-2-:	67	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	98	if ((!rst_ni))
-2-:	100	if (clr_i)
-3-:	102	if (gen_normal_fifo.fifo_incr_wptr)
-4-:	103	if ((gen_normal_fifo.fifo_wptr[0] == 1'((Depth - 1))))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	1	Covered	T1,T3,T4
0	0	1	0	Covered	T1,T3,T4
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	112	if ((!rst_ni))
-2-:	114	if (clr_i)
-3-:	116	if (gen_normal_fifo.fifo_incr_rptr)
-4-:	117	if ((gen_normal_fifo.fifo_rptr[0] == 1'((Depth - 1))))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	1	Covered	T1,T3,T4
0	0	1	0	Covered	T1,T3,T4
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	137	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1495666	556288	0	0
DepthKnown_A	1495666	1491415	0	0
RvalidKnown_A	1495666	1491415	0	0
WreadyKnown_A	1495666	1491415	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	1495666	556288	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495666	556288	0	0
T1	5603	1730	0	0
T3	3688	390	0	0
T4	86174	71763	0	0
T5	29585	9294	0	0
T6	15992	9426	0	0
T7	138869	3761	0	0
T8	218850	204443	0	0
T9	2911	390	0	0
T10	18880	8082	0	0
T11	4329	1950	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495666	1491415	0	0
T1	5603	5513	0	0
T2	6283	6200	0	0
T3	3688	3596	0	0
T4	86174	86096	0	0
T5	29585	29519	0	0
T6	15992	15911	0	0
T7	138869	138797	0	0
T8	218850	218796	0	0
T9	2911	2824	0	0
T10	18880	18784	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495666	1491415	0	0
T1	5603	5513	0	0
T2	6283	6200	0	0
T3	3688	3596	0	0
T4	86174	86096	0	0
T5	29585	29519	0	0
T6	15992	15911	0	0
T7	138869	138797	0	0
T8	218850	218796	0	0
T9	2911	2824	0	0
T10	18880	18784	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495666	1491415	0	0
T1	5603	5513	0	0
T2	6283	6200	0	0
T3	3688	3596	0	0
T4	86174	86096	0	0
T5	29585	29519	0	0
T6	15992	15911	0	0
T7	138869	138797	0	0
T8	218850	218796	0	0
T9	2911	2824	0	0
T10	18880	18784	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495666	556288	0	0
T1	5603	1730	0	0
T3	3688	390	0	0
T4	86174	71763	0	0
T5	29585	9294	0	0
T6	15992	9426	0	0
T7	138869	3761	0	0
T8	218850	204443	0	0
T9	2911	390	0	0
T10	18880	8082	0	0
T11	4329	1950	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo

	Line No.	Total	Covered	Percent
TOTAL		36	28	77.78
ALWAYS	65	4	4	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
ALWAYS	98	7	4	57.14
ALWAYS	112	7	4	57.14
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	134	1	0	0.00
ALWAYS	137	2	1	50.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	162	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
66	1	1
67	1	1
68	1	1
			MISSING_ELSE
79	1	1
80	1	1
81	1	1
82	1	1
83	1	1
87	1	1
88	1	1
93	1	1
94	1	1
95	1	1
98	1	1
99	1	1
100	1	1
101		unreachable
102	1	1
103	0	1
104	0	1
106	0	1
			MISSING_ELSE
112	1	1
113	1	1
114	1	1
115		unreachable
116	1	1
117	0	1
118	0	1
120	0	1
			MISSING_ELSE
125	1	1
126	1	1
134	0	1
137	1	1
138	0	1
			MISSING_ELSE
155	1	1
156	1	1
162	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo

	Total	Covered	Percent
Conditions	11	5	45.45
Logical	11	5	45.45
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       83
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       152
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       152
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       160
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo

	Line No.	Total	Covered	Percent
Branches		22	11	50.00
TERNARY	83	3	1	33.33
TERNARY	152	2	1	50.00
TERNARY	160	2	1	50.00
IF	65	3	3	100.00
IF	98	5	2	40.00
IF	112	5	2	40.00
IF	137	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	83	(gen_normal_fifo.full) ? 
-2-:	83	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T3
0	0	Not Covered

	LineNo.	Expression
-1-:	152	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	160	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	65	if ((!rst_ni))
-2-:	67	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	98	if ((!rst_ni))
-2-:	100	if (clr_i)
-3-:	102	if (gen_normal_fifo.fifo_incr_wptr)
-4-:	103	if ((gen_normal_fifo.fifo_wptr[0] == 1'((Depth - 1))))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	1	Not Covered
0	0	1	0	Not Covered
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	112	if ((!rst_ni))
-2-:	114	if (clr_i)
-3-:	116	if (gen_normal_fifo.fifo_incr_rptr)
-4-:	117	if ((gen_normal_fifo.fifo_rptr[0] == 1'((Depth - 1))))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	1	Not Covered
0	0	1	0	Not Covered
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	137	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1495666	0	0	0
DepthKnown_A	1495666	1491415	0	0
RvalidKnown_A	1495666	1491415	0	0
WreadyKnown_A	1495666	1491415	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	1495666	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495666	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495666	1491415	0	0
T1	5603	5513	0	0
T2	6283	6200	0	0
T3	3688	3596	0	0
T4	86174	86096	0	0
T5	29585	29519	0	0
T6	15992	15911	0	0
T7	138869	138797	0	0
T8	218850	218796	0	0
T9	2911	2824	0	0
T10	18880	18784	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495666	1491415	0	0
T1	5603	5513	0	0
T2	6283	6200	0	0
T3	3688	3596	0	0
T4	86174	86096	0	0
T5	29585	29519	0	0
T6	15992	15911	0	0
T7	138869	138797	0	0
T8	218850	218796	0	0
T9	2911	2824	0	0
T10	18880	18784	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495666	1491415	0	0
T1	5603	5513	0	0
T2	6283	6200	0	0
T3	3688	3596	0	0
T4	86174	86096	0	0
T5	29585	29519	0	0
T6	15992	15911	0	0
T7	138869	138797	0	0
T8	218850	218796	0	0
T9	2911	2824	0	0
T10	18880	18784	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495666	0	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.i_rsp_order_fifo

	Line No.	Total	Covered	Percent
TOTAL		36	36	100.00
ALWAYS	65	4	4	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
ALWAYS	98	7	7	100.00
ALWAYS	112	7	7	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
ALWAYS	137	2	2	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	162	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
66	1	1
67	1	1
68	1	1
			MISSING_ELSE
79	1	1
80	1	1
81	1	1
82	1	1
83	1	1
87	1	1
88	1	1
93	1	1
94	1	1
95	1	1
98	1	1
99	1	1
100	1	1
101		unreachable
102	1	1
103	1	1
104	1	1
106	1	1
			MISSING_ELSE
112	1	1
113	1	1
114	1	1
115		unreachable
116	1	1
117	1	1
118	1	1
120	1	1
			MISSING_ELSE
125	1	1
126	1	1
134	1	1
137	1	1
138	1	1
			MISSING_ELSE
155	1	1
156	1	1
162	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.i_rsp_order_fifo

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       83
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.i_rsp_order_fifo

	Line No.	Total	Covered	Percent
Branches		20	17	85.00
TERNARY	83	3	2	66.67
TERNARY	160	2	2	100.00
IF	65	3	3	100.00
IF	98	5	4	80.00
IF	112	5	4	80.00
IF	137	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	83	(gen_normal_fifo.full) ? 
-2-:	83	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	160	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	65	if ((!rst_ni))
-2-:	67	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	98	if ((!rst_ni))
-2-:	100	if (clr_i)
-3-:	102	if (gen_normal_fifo.fifo_incr_wptr)
-4-:	103	if ((gen_normal_fifo.fifo_wptr[0] == 1'((Depth - 1))))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	1	Covered	T1,T2,T3
0	0	1	0	Covered	T1,T2,T3
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	112	if ((!rst_ni))
-2-:	114	if (clr_i)
-3-:	116	if (gen_normal_fifo.fifo_incr_rptr)
-4-:	117	if ((gen_normal_fifo.fifo_rptr[0] == 1'((Depth - 1))))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	1	Covered	T1,T2,T3
0	0	1	0	Covered	T1,T2,T3
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	137	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.i_rsp_order_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1495666	9174	0	0
DepthKnown_A	1495666	1491415	0	0
RvalidKnown_A	1495666	1491415	0	0
WreadyKnown_A	1495666	1491415	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	1495666	9174	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495666	9174	0	0
T1	5603	38	0	0
T2	6283	92	0	0
T3	3688	50	0	0
T4	86174	312	0	0
T5	29585	344	0	0
T6	15992	144	0	0
T7	138869	16	0	0
T8	218850	236	0	0
T10	18880	430	0	0
T28	13782	170	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495666	1491415	0	0
T1	5603	5513	0	0
T2	6283	6200	0	0
T3	3688	3596	0	0
T4	86174	86096	0	0
T5	29585	29519	0	0
T6	15992	15911	0	0
T7	138869	138797	0	0
T8	218850	218796	0	0
T9	2911	2824	0	0
T10	18880	18784	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495666	1491415	0	0
T1	5603	5513	0	0
T2	6283	6200	0	0
T3	3688	3596	0	0
T4	86174	86096	0	0
T5	29585	29519	0	0
T6	15992	15911	0	0
T7	138869	138797	0	0
T8	218850	218796	0	0
T9	2911	2824	0	0
T10	18880	18784	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495666	1491415	0	0
T1	5603	5513	0	0
T2	6283	6200	0	0
T3	3688	3596	0	0
T4	86174	86096	0	0
T5	29585	29519	0	0
T6	15992	15911	0	0
T7	138869	138797	0	0
T8	218850	218796	0	0
T9	2911	2824	0	0
T10	18880	18784	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495666	9174	0	0
T1	5603	38	0	0
T2	6283	92	0	0
T3	3688	50	0	0
T4	86174	312	0	0
T5	29585	344	0	0
T6	15992	144	0	0
T7	138869	16	0	0
T8	218850	236	0	0
T10	18880	430	0	0
T28	13782	170	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage

	Line No.	Total	Covered	Percent
TOTAL		36	36	100.00
ALWAYS	65	4	4	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
ALWAYS	98	7	7	100.00
ALWAYS	112	7	7	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
ALWAYS	137	2	2	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	162	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
66	1	1
67	1	1
68	1	1
			MISSING_ELSE
79	1	1
80	1	1
81	1	1
82	1	1
83	1	1
87	1	1
88	1	1
93	1	1
94	1	1
95	1	1
98	1	1
99	1	1
100	1	1
101		unreachable
102	1	1
103	1	1
104	1	1
106	1	1
			MISSING_ELSE
112	1	1
113	1	1
114	1	1
115		unreachable
116	1	1
117	1	1
118	1	1
120	1	1
			MISSING_ELSE
125	1	1
126	1	1
134	1	1
137	1	1
138	1	1
			MISSING_ELSE
155	1	1
156	1	1
162	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       83
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage

	Line No.	Total	Covered	Percent
Branches		20	17	85.00
TERNARY	83	3	2	66.67
TERNARY	160	2	2	100.00
IF	65	3	3	100.00
IF	98	5	4	80.00
IF	112	5	4	80.00
IF	137	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	83	(gen_normal_fifo.full) ? 
-2-:	83	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	160	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	65	if ((!rst_ni))
-2-:	67	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	98	if ((!rst_ni))
-2-:	100	if (clr_i)
-3-:	102	if (gen_normal_fifo.fifo_incr_wptr)
-4-:	103	if ((gen_normal_fifo.fifo_wptr[0] == 1'((Depth - 1))))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	1	Covered	T1,T2,T3
0	0	1	0	Covered	T1,T2,T3
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	112	if ((!rst_ni))
-2-:	114	if (clr_i)
-3-:	116	if (gen_normal_fifo.fifo_incr_rptr)
-4-:	117	if ((gen_normal_fifo.fifo_rptr[0] == 1'((Depth - 1))))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	1	Covered	T1,T2,T3
0	0	1	0	Covered	T1,T2,T3
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	137	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1495666	4587	0	0
DepthKnown_A	1495666	1491415	0	0
RvalidKnown_A	1495666	1491415	0	0
WreadyKnown_A	1495666	1491415	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	1495666	4587	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495666	4587	0	0
T1	5603	19	0	0
T2	6283	46	0	0
T3	3688	25	0	0
T4	86174	156	0	0
T5	29585	172	0	0
T6	15992	72	0	0
T7	138869	8	0	0
T8	218850	118	0	0
T10	18880	215	0	0
T28	13782	85	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495666	1491415	0	0
T1	5603	5513	0	0
T2	6283	6200	0	0
T3	3688	3596	0	0
T4	86174	86096	0	0
T5	29585	29519	0	0
T6	15992	15911	0	0
T7	138869	138797	0	0
T8	218850	218796	0	0
T9	2911	2824	0	0
T10	18880	18784	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495666	1491415	0	0
T1	5603	5513	0	0
T2	6283	6200	0	0
T3	3688	3596	0	0
T4	86174	86096	0	0
T5	29585	29519	0	0
T6	15992	15911	0	0
T7	138869	138797	0	0
T8	218850	218796	0	0
T9	2911	2824	0	0
T10	18880	18784	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495666	1491415	0	0
T1	5603	5513	0	0
T2	6283	6200	0	0
T3	3688	3596	0	0
T4	86174	86096	0	0
T5	29585	29519	0	0
T6	15992	15911	0	0
T7	138869	138797	0	0
T8	218850	218796	0	0
T9	2911	2824	0	0
T10	18880	18784	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	1495666	4587	0	0
T1	5603	19	0	0
T2	6283	46	0	0
T3	3688	25	0	0
T4	86174	156	0	0
T5	29585	172	0	0
T6	15992	72	0	0
T7	138869	8	0	0
T8	218850	118	0	0
T10	18880	215	0	0
T28	13782	85	0	0