Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
77.93 98.23 55.00 67.57 90.91


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
65.09 90.19 38.89 62.24 69.05


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
69.44 98.61 58.33 60.00 70.27 60.00 gen_flash_cores[0].u_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_bufs[0].u_rd_buf 32.41 55.56 8.33 33.33
gen_bufs[1].u_rd_buf 32.41 55.56 8.33 33.33
gen_bufs[2].u_rd_buf 32.41 55.56 8.33 33.33
gen_bufs[3].u_rd_buf 32.41 55.56 8.33 33.33
i_rsp_order_fifo 92.08 100.00 83.33 85.00 100.00
i_valid_random 60.51 100.00 50.00 54.55 37.50
u_dec 100.00 100.00
u_mask_storage 59.44 77.78 50.00 50.00 60.00
u_plain_enc 100.00 100.00
u_rd_storage 92.08 100.00 83.33 85.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
77.93 98.23 55.00 67.57 90.91


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
65.09 90.19 38.89 62.24 69.05


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
69.44 98.61 58.33 60.00 70.27 60.00 gen_flash_cores[1].u_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_bufs[0].u_rd_buf 32.41 55.56 8.33 33.33
gen_bufs[1].u_rd_buf 32.41 55.56 8.33 33.33
gen_bufs[2].u_rd_buf 32.41 55.56 8.33 33.33
gen_bufs[3].u_rd_buf 32.41 55.56 8.33 33.33
i_rsp_order_fifo 92.08 100.00 83.33 85.00 100.00
i_valid_random 60.51 100.00 50.00 54.55 37.50
u_dec 100.00 100.00
u_mask_storage 59.44 77.78 50.00 50.00 60.00
u_plain_enc 100.00 100.00
u_rd_storage 92.08 100.00 83.33 85.00 100.00

Line Coverage for Module : flash_phy_rd
Line No.TotalCoveredPercent
TOTAL11311198.23
CONT_ASSIGN12611100.00
CONT_ASSIGN12911100.00
CONT_ASSIGN12911100.00
CONT_ASSIGN12911100.00
CONT_ASSIGN12911100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16911100.00
CONT_ASSIGN16911100.00
CONT_ASSIGN16911100.00
CONT_ASSIGN16911100.00
CONT_ASSIGN17011100.00
CONT_ASSIGN17011100.00
CONT_ASSIGN17011100.00
CONT_ASSIGN17011100.00
CONT_ASSIGN17211100.00
CONT_ASSIGN17211100.00
CONT_ASSIGN17211100.00
CONT_ASSIGN17211100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19711100.00
CONT_ASSIGN19711100.00
CONT_ASSIGN19711100.00
CONT_ASSIGN19711100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20711100.00
ALWAYS23144100.00
CONT_ASSIGN26411100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27711100.00
CONT_ASSIGN28211100.00
ALWAYS3091313100.00
CONT_ASSIGN32611100.00
CONT_ASSIGN33111100.00
CONT_ASSIGN33511100.00
CONT_ASSIGN33911100.00
CONT_ASSIGN35811100.00
CONT_ASSIGN36211100.00
CONT_ASSIGN37511100.00
CONT_ASSIGN38311100.00
CONT_ASSIGN38711100.00
CONT_ASSIGN39011100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN41511100.00
CONT_ASSIGN42111100.00
CONT_ASSIGN42511100.00
CONT_ASSIGN42911100.00
CONT_ASSIGN44611100.00
CONT_ASSIGN45011100.00
CONT_ASSIGN45311100.00
CONT_ASSIGN45411100.00
ALWAYS4996466.67
CONT_ASSIGN50911100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51611100.00
CONT_ASSIGN52311100.00
CONT_ASSIGN52711100.00
CONT_ASSIGN53411100.00
CONT_ASSIGN54911100.00
CONT_ASSIGN55411100.00
CONT_ASSIGN55911100.00
CONT_ASSIGN55911100.00
CONT_ASSIGN55911100.00
CONT_ASSIGN55911100.00
ALWAYS56544100.00
CONT_ASSIGN57411100.00
CONT_ASSIGN58511100.00
CONT_ASSIGN58611100.00
CONT_ASSIGN60111100.00
CONT_ASSIGN60611100.00
CONT_ASSIGN60711100.00
CONT_ASSIGN61011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
126 1 1
129 4 4
130 4 4
131 4 4
134 1 1
136 3 3
162 1 1
169 4 4
170 4 4
172 4 4
187 4 4
193 4 4
197 4 4
204 1 1
207 1 1
231 1 1
232 1 1
233 1 1
234 1 1
MISSING_ELSE
264 1 1
271 1 1
277 1 1
282 1 1
309 1 1
310 1 1
311 1 1
312 1 1
313 1 1
314 1 1
315 1 1
316 1 1
317 1 1
318 1 1
319 1 1
320 1 1
321 1 1
MISSING_ELSE
326 1 1
331 1 1
335 1 1
339 1 1
358 1 1
362 1 1
375 1 1
383 1 1
387 1 1
390 1 1
393 1 1
415 1 1
421 1 1
425 1 1
429 1 1
446 1 1
450 1 1
453 1 1
454 1 1
499 1 1
500 1 1
501 1 1
502 0 1
503 1 1
504 0 1
MISSING_ELSE
509 1 1
513 1 1
516 1 1
523 1 1
527 1 1
534 1 1
549 1 1
554 1 1
559 4 4
565 1 1
566 1 1
567 1 1
568 1 1
MISSING_ELSE
574 1 1
585 1 1
586 1 1
601 1 1
606 1 1
607 1 1
610 1 1


Cond Coverage for Module : flash_phy_rd
TotalCoveredPercent
Conditions402255.00
Logical402255.00
Non-Logical00
Event00

 LINE       162
 EXPRESSION (((|buf_invalid_alloc)) ? buf_invalid_alloc : buf_valid_alloc)
             -----------1----------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       207
 EXPRESSION (no_match ? (({flash_phy_pkg::NumBuf {(req_i & buf_en_q)}} & buf_alloc)) : '0)
             ----1---
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       271
 EXPRESSION (((|alloc)) ? buf_alloc : buf_match)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       313
 EXPRESSION (req_o && ack_i)
             --1--    --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       335
 EXPRESSION (no_match ? (((ack_i & flash_rdy) & rd_stages_rdy)) : rd_stages_rdy)
             ----1---
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       358
 EXPRESSION (rd_done && rd_attrs.ecc)
             ---1---    ------2-----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       383
 EXPRESSION (((data_err | ecc_single_err_o)) ? data_ecc_chk : data_i[(flash_phy_pkg::PlainDataWidth - 1):0])
             ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       421
 EXPRESSION (hint_descram ? ((descramble_req_o & descramble_ack_i)) : fifo_data_valid)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       501
 EXPRESSION (req_o && descramble_i)
             --1--    ------2-----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       503
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       523
 EXPRESSION 
 Number  Term
      1  forward ? data_int : (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       523
 SUB-EXPRESSION (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data)
                 ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       527
 EXPRESSION (forward ? data_err : data_err_q)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       549
 EXPRESSION (forward ? alloc_q : (fifo_data_ready ? alloc_q2 : '0))
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       549
 SUB-EXPRESSION (fifo_data_ready ? alloc_q2 : '0)
                 -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       574
 EXPRESSION (((|buf_rsp_match)) ? buf_rsp_data : muxed_data)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       586
 EXPRESSION (data_err_o ? ({flash_phy_pkg::BusWidth {1'b1}}) : gen_rd.bus_words_packed[rsp_fifo_rdata.word_sel])
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       601
 EXPRESSION (rsp_fifo_rdata.intg_ecc_en ? (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth]) : '0)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

Branch Coverage for Module : flash_phy_rd
Line No.TotalCoveredPercent
Branches 37 25 67.57
TERNARY 162 2 1 50.00
TERNARY 207 2 1 50.00
TERNARY 271 2 1 50.00
TERNARY 335 2 1 50.00
TERNARY 383 2 1 50.00
TERNARY 421 2 1 50.00
TERNARY 523 3 2 66.67
TERNARY 527 2 2 100.00
TERNARY 549 3 3 100.00
TERNARY 574 2 1 50.00
TERNARY 601 2 1 50.00
TERNARY 586 2 1 50.00
IF 231 3 3 100.00
IF 309 4 4 100.00
IF 499 4 2 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 162 ((|buf_invalid_alloc)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 207 (no_match) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 271 ((|alloc)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 335 (no_match) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 383 ((data_err | ecc_single_err_o)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 421 (hint_descram) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 523 (forward) ? -2-: 523 (hint_descram) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 527 (forward) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 549 (forward) ? -2-: 549 (fifo_data_ready) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 574 ((|buf_rsp_match)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 601 (rsp_fifo_rdata.intg_ecc_en) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 586 (data_err_o) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 231 if ((!rst_ni)) -2-: 233 if (idle_o)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 309 if ((!rst_ni)) -2-: 313 if ((req_o && ack_i)) -3-: 320 if (rd_done)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 499 if ((!rst_ni)) -2-: 501 if ((req_o && descramble_i)) -3-: 503 if ((calc_req_o && calc_ack_i))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


Assert Coverage for Module : flash_phy_rd
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 11 11 100.00 10 90.91
Cover properties 0 0 0
Cover sequences 0 0 0
Total 11 11 100.00 10 90.91




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BufferMatchEcc_A 2991332 0 0 0
ExclusiveOps_A 2991332 2982830 0 0
ExclusiveProgHazard_A 2991332 2982830 0 0
ExclusiveState_A 2991332 2982830 0 0
FifoSameDepth_A 2991332 9559 0 0
ForwardCheck_A 2991332 9559 0 0
IdleCheck_A 2991332 19118 0 0
MaxBufs_A 110 110 0 0
OneHotAlloc_A 2991332 2982830 0 0
OneHotMatch_A 2991332 2982830 0 0
OneHotUpdate_A 2991332 2982830 0 0


BufferMatchEcc_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2991332 0 0 0

ExclusiveOps_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2991332 2982830 0 0
T1 11206 11026 0 0
T2 12566 12400 0 0
T3 7376 7192 0 0
T4 172348 172192 0 0
T5 59170 59038 0 0
T6 31984 31822 0 0
T7 277738 277594 0 0
T8 437700 437592 0 0
T9 5822 5648 0 0
T10 37760 37568 0 0

ExclusiveProgHazard_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2991332 2982830 0 0
T1 11206 11026 0 0
T2 12566 12400 0 0
T3 7376 7192 0 0
T4 172348 172192 0 0
T5 59170 59038 0 0
T6 31984 31822 0 0
T7 277738 277594 0 0
T8 437700 437592 0 0
T9 5822 5648 0 0
T10 37760 37568 0 0

ExclusiveState_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2991332 2982830 0 0
T1 11206 11026 0 0
T2 12566 12400 0 0
T3 7376 7192 0 0
T4 172348 172192 0 0
T5 59170 59038 0 0
T6 31984 31822 0 0
T7 277738 277594 0 0
T8 437700 437592 0 0
T9 5822 5648 0 0
T10 37760 37568 0 0

FifoSameDepth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2991332 9559 0 0
T1 11206 129 0 0
T2 6283 46 0 0
T3 7376 37 0 0
T4 172348 243 0 0
T5 59170 394 0 0
T6 31984 372 0 0
T7 277738 97 0 0
T8 437700 291 0 0
T9 2911 12 0 0
T10 37760 467 0 0
T11 4329 60 0 0
T28 13782 85 0 0

ForwardCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2991332 9559 0 0
T1 11206 129 0 0
T2 6283 46 0 0
T3 7376 37 0 0
T4 172348 243 0 0
T5 59170 394 0 0
T6 31984 372 0 0
T7 277738 97 0 0
T8 437700 291 0 0
T9 2911 12 0 0
T10 37760 467 0 0
T11 4329 60 0 0
T28 13782 85 0 0

IdleCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2991332 19118 0 0
T1 11206 258 0 0
T2 6283 92 0 0
T3 7376 74 0 0
T4 172348 486 0 0
T5 59170 788 0 0
T6 31984 744 0 0
T7 277738 194 0 0
T8 437700 582 0 0
T9 2911 24 0 0
T10 37760 934 0 0
T11 4329 120 0 0
T28 13782 170 0 0

MaxBufs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 110 110 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T6 2 2 0 0
T7 2 2 0 0
T8 2 2 0 0
T9 2 2 0 0
T10 2 2 0 0

OneHotAlloc_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2991332 2982830 0 0
T1 11206 11026 0 0
T2 12566 12400 0 0
T3 7376 7192 0 0
T4 172348 172192 0 0
T5 59170 59038 0 0
T6 31984 31822 0 0
T7 277738 277594 0 0
T8 437700 437592 0 0
T9 5822 5648 0 0
T10 37760 37568 0 0

OneHotMatch_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2991332 2982830 0 0
T1 11206 11026 0 0
T2 12566 12400 0 0
T3 7376 7192 0 0
T4 172348 172192 0 0
T5 59170 59038 0 0
T6 31984 31822 0 0
T7 277738 277594 0 0
T8 437700 437592 0 0
T9 5822 5648 0 0
T10 37760 37568 0 0

OneHotUpdate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2991332 2982830 0 0
T1 11206 11026 0 0
T2 12566 12400 0 0
T3 7376 7192 0 0
T4 172348 172192 0 0
T5 59170 59038 0 0
T6 31984 31822 0 0
T7 277738 277594 0 0
T8 437700 437592 0 0
T9 5822 5648 0 0
T10 37760 37568 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd
Line No.TotalCoveredPercent
TOTAL11311198.23
CONT_ASSIGN12611100.00
CONT_ASSIGN12911100.00
CONT_ASSIGN12911100.00
CONT_ASSIGN12911100.00
CONT_ASSIGN12911100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16911100.00
CONT_ASSIGN16911100.00
CONT_ASSIGN16911100.00
CONT_ASSIGN16911100.00
CONT_ASSIGN17011100.00
CONT_ASSIGN17011100.00
CONT_ASSIGN17011100.00
CONT_ASSIGN17011100.00
CONT_ASSIGN17211100.00
CONT_ASSIGN17211100.00
CONT_ASSIGN17211100.00
CONT_ASSIGN17211100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19711100.00
CONT_ASSIGN19711100.00
CONT_ASSIGN19711100.00
CONT_ASSIGN19711100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20711100.00
ALWAYS23144100.00
CONT_ASSIGN26411100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27711100.00
CONT_ASSIGN28211100.00
ALWAYS3091313100.00
CONT_ASSIGN32611100.00
CONT_ASSIGN33111100.00
CONT_ASSIGN33511100.00
CONT_ASSIGN33911100.00
CONT_ASSIGN35811100.00
CONT_ASSIGN36211100.00
CONT_ASSIGN37511100.00
CONT_ASSIGN38311100.00
CONT_ASSIGN38711100.00
CONT_ASSIGN39011100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN41511100.00
CONT_ASSIGN42111100.00
CONT_ASSIGN42511100.00
CONT_ASSIGN42911100.00
CONT_ASSIGN44611100.00
CONT_ASSIGN45011100.00
CONT_ASSIGN45311100.00
CONT_ASSIGN45411100.00
ALWAYS4996466.67
CONT_ASSIGN50911100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51611100.00
CONT_ASSIGN52311100.00
CONT_ASSIGN52711100.00
CONT_ASSIGN53411100.00
CONT_ASSIGN54911100.00
CONT_ASSIGN55411100.00
CONT_ASSIGN55911100.00
CONT_ASSIGN55911100.00
CONT_ASSIGN55911100.00
CONT_ASSIGN55911100.00
ALWAYS56544100.00
CONT_ASSIGN57411100.00
CONT_ASSIGN58511100.00
CONT_ASSIGN58611100.00
CONT_ASSIGN60111100.00
CONT_ASSIGN60611100.00
CONT_ASSIGN60711100.00
CONT_ASSIGN61011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
126 1 1
129 4 4
130 4 4
131 4 4
134 1 1
136 3 3
162 1 1
169 4 4
170 4 4
172 4 4
187 4 4
193 4 4
197 4 4
204 1 1
207 1 1
231 1 1
232 1 1
233 1 1
234 1 1
MISSING_ELSE
264 1 1
271 1 1
277 1 1
282 1 1
309 1 1
310 1 1
311 1 1
312 1 1
313 1 1
314 1 1
315 1 1
316 1 1
317 1 1
318 1 1
319 1 1
320 1 1
321 1 1
MISSING_ELSE
326 1 1
331 1 1
335 1 1
339 1 1
358 1 1
362 1 1
375 1 1
383 1 1
387 1 1
390 1 1
393 1 1
415 1 1
421 1 1
425 1 1
429 1 1
446 1 1
450 1 1
453 1 1
454 1 1
499 1 1
500 1 1
501 1 1
502 0 1
503 1 1
504 0 1
MISSING_ELSE
509 1 1
513 1 1
516 1 1
523 1 1
527 1 1
534 1 1
549 1 1
554 1 1
559 4 4
565 1 1
566 1 1
567 1 1
568 1 1
MISSING_ELSE
574 1 1
585 1 1
586 1 1
601 1 1
606 1 1
607 1 1
610 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd
TotalCoveredPercent
Conditions402255.00
Logical402255.00
Non-Logical00
Event00

 LINE       162
 EXPRESSION (((|buf_invalid_alloc)) ? buf_invalid_alloc : buf_valid_alloc)
             -----------1----------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       207
 EXPRESSION (no_match ? (({flash_phy_pkg::NumBuf {(req_i & buf_en_q)}} & buf_alloc)) : '0)
             ----1---
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       271
 EXPRESSION (((|alloc)) ? buf_alloc : buf_match)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       313
 EXPRESSION (req_o && ack_i)
             --1--    --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       335
 EXPRESSION (no_match ? (((ack_i & flash_rdy) & rd_stages_rdy)) : rd_stages_rdy)
             ----1---
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       358
 EXPRESSION (rd_done && rd_attrs.ecc)
             ---1---    ------2-----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       383
 EXPRESSION (((data_err | ecc_single_err_o)) ? data_ecc_chk : data_i[(flash_phy_pkg::PlainDataWidth - 1):0])
             ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       421
 EXPRESSION (hint_descram ? ((descramble_req_o & descramble_ack_i)) : fifo_data_valid)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       501
 EXPRESSION (req_o && descramble_i)
             --1--    ------2-----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       503
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       523
 EXPRESSION 
 Number  Term
      1  forward ? data_int : (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       523
 SUB-EXPRESSION (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data)
                 ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       527
 EXPRESSION (forward ? data_err : data_err_q)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       549
 EXPRESSION (forward ? alloc_q : (fifo_data_ready ? alloc_q2 : '0))
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       549
 SUB-EXPRESSION (fifo_data_ready ? alloc_q2 : '0)
                 -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       574
 EXPRESSION (((|buf_rsp_match)) ? buf_rsp_data : muxed_data)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       586
 EXPRESSION (data_err_o ? ({flash_phy_pkg::BusWidth {1'b1}}) : gen_rd.bus_words_packed[rsp_fifo_rdata.word_sel])
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       601
 EXPRESSION (rsp_fifo_rdata.intg_ecc_en ? (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth]) : '0)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd
Line No.TotalCoveredPercent
Branches 37 25 67.57
TERNARY 162 2 1 50.00
TERNARY 207 2 1 50.00
TERNARY 271 2 1 50.00
TERNARY 335 2 1 50.00
TERNARY 383 2 1 50.00
TERNARY 421 2 1 50.00
TERNARY 523 3 2 66.67
TERNARY 527 2 2 100.00
TERNARY 549 3 3 100.00
TERNARY 574 2 1 50.00
TERNARY 601 2 1 50.00
TERNARY 586 2 1 50.00
IF 231 3 3 100.00
IF 309 4 4 100.00
IF 499 4 2 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 162 ((|buf_invalid_alloc)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 207 (no_match) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 271 ((|alloc)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 335 (no_match) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 383 ((data_err | ecc_single_err_o)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 421 (hint_descram) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 523 (forward) ? -2-: 523 (hint_descram) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 527 (forward) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 549 (forward) ? -2-: 549 (fifo_data_ready) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 574 ((|buf_rsp_match)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 601 (rsp_fifo_rdata.intg_ecc_en) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 586 (data_err_o) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 231 if ((!rst_ni)) -2-: 233 if (idle_o)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 309 if ((!rst_ni)) -2-: 313 if ((req_o && ack_i)) -3-: 320 if (rd_done)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 499 if ((!rst_ni)) -2-: 501 if ((req_o && descramble_i)) -3-: 503 if ((calc_req_o && calc_ack_i))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 11 11 100.00 10 90.91
Cover properties 0 0 0
Cover sequences 0 0 0
Total 11 11 100.00 10 90.91




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BufferMatchEcc_A 1495666 0 0 0
ExclusiveOps_A 1495666 1491415 0 0
ExclusiveProgHazard_A 1495666 1491415 0 0
ExclusiveState_A 1495666 1491415 0 0
FifoSameDepth_A 1495666 4587 0 0
ForwardCheck_A 1495666 4587 0 0
IdleCheck_A 1495666 9174 0 0
MaxBufs_A 55 55 0 0
OneHotAlloc_A 1495666 1491415 0 0
OneHotMatch_A 1495666 1491415 0 0
OneHotUpdate_A 1495666 1491415 0 0


BufferMatchEcc_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 0 0 0

ExclusiveOps_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 1491415 0 0
T1 5603 5513 0 0
T2 6283 6200 0 0
T3 3688 3596 0 0
T4 86174 86096 0 0
T5 29585 29519 0 0
T6 15992 15911 0 0
T7 138869 138797 0 0
T8 218850 218796 0 0
T9 2911 2824 0 0
T10 18880 18784 0 0

ExclusiveProgHazard_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 1491415 0 0
T1 5603 5513 0 0
T2 6283 6200 0 0
T3 3688 3596 0 0
T4 86174 86096 0 0
T5 29585 29519 0 0
T6 15992 15911 0 0
T7 138869 138797 0 0
T8 218850 218796 0 0
T9 2911 2824 0 0
T10 18880 18784 0 0

ExclusiveState_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 1491415 0 0
T1 5603 5513 0 0
T2 6283 6200 0 0
T3 3688 3596 0 0
T4 86174 86096 0 0
T5 29585 29519 0 0
T6 15992 15911 0 0
T7 138869 138797 0 0
T8 218850 218796 0 0
T9 2911 2824 0 0
T10 18880 18784 0 0

FifoSameDepth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 4587 0 0
T1 5603 19 0 0
T2 6283 46 0 0
T3 3688 25 0 0
T4 86174 156 0 0
T5 29585 172 0 0
T6 15992 72 0 0
T7 138869 8 0 0
T8 218850 118 0 0
T10 18880 215 0 0
T28 13782 85 0 0

ForwardCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 4587 0 0
T1 5603 19 0 0
T2 6283 46 0 0
T3 3688 25 0 0
T4 86174 156 0 0
T5 29585 172 0 0
T6 15992 72 0 0
T7 138869 8 0 0
T8 218850 118 0 0
T10 18880 215 0 0
T28 13782 85 0 0

IdleCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 9174 0 0
T1 5603 38 0 0
T2 6283 92 0 0
T3 3688 50 0 0
T4 86174 312 0 0
T5 29585 344 0 0
T6 15992 144 0 0
T7 138869 16 0 0
T8 218850 236 0 0
T10 18880 430 0 0
T28 13782 170 0 0

MaxBufs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OneHotAlloc_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 1491415 0 0
T1 5603 5513 0 0
T2 6283 6200 0 0
T3 3688 3596 0 0
T4 86174 86096 0 0
T5 29585 29519 0 0
T6 15992 15911 0 0
T7 138869 138797 0 0
T8 218850 218796 0 0
T9 2911 2824 0 0
T10 18880 18784 0 0

OneHotMatch_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 1491415 0 0
T1 5603 5513 0 0
T2 6283 6200 0 0
T3 3688 3596 0 0
T4 86174 86096 0 0
T5 29585 29519 0 0
T6 15992 15911 0 0
T7 138869 138797 0 0
T8 218850 218796 0 0
T9 2911 2824 0 0
T10 18880 18784 0 0

OneHotUpdate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 1491415 0 0
T1 5603 5513 0 0
T2 6283 6200 0 0
T3 3688 3596 0 0
T4 86174 86096 0 0
T5 29585 29519 0 0
T6 15992 15911 0 0
T7 138869 138797 0 0
T8 218850 218796 0 0
T9 2911 2824 0 0
T10 18880 18784 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd
Line No.TotalCoveredPercent
TOTAL11311198.23
CONT_ASSIGN12611100.00
CONT_ASSIGN12911100.00
CONT_ASSIGN12911100.00
CONT_ASSIGN12911100.00
CONT_ASSIGN12911100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16911100.00
CONT_ASSIGN16911100.00
CONT_ASSIGN16911100.00
CONT_ASSIGN16911100.00
CONT_ASSIGN17011100.00
CONT_ASSIGN17011100.00
CONT_ASSIGN17011100.00
CONT_ASSIGN17011100.00
CONT_ASSIGN17211100.00
CONT_ASSIGN17211100.00
CONT_ASSIGN17211100.00
CONT_ASSIGN17211100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19711100.00
CONT_ASSIGN19711100.00
CONT_ASSIGN19711100.00
CONT_ASSIGN19711100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20711100.00
ALWAYS23144100.00
CONT_ASSIGN26411100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27711100.00
CONT_ASSIGN28211100.00
ALWAYS3091313100.00
CONT_ASSIGN32611100.00
CONT_ASSIGN33111100.00
CONT_ASSIGN33511100.00
CONT_ASSIGN33911100.00
CONT_ASSIGN35811100.00
CONT_ASSIGN36211100.00
CONT_ASSIGN37511100.00
CONT_ASSIGN38311100.00
CONT_ASSIGN38711100.00
CONT_ASSIGN39011100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN41511100.00
CONT_ASSIGN42111100.00
CONT_ASSIGN42511100.00
CONT_ASSIGN42911100.00
CONT_ASSIGN44611100.00
CONT_ASSIGN45011100.00
CONT_ASSIGN45311100.00
CONT_ASSIGN45411100.00
ALWAYS4996466.67
CONT_ASSIGN50911100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51611100.00
CONT_ASSIGN52311100.00
CONT_ASSIGN52711100.00
CONT_ASSIGN53411100.00
CONT_ASSIGN54911100.00
CONT_ASSIGN55411100.00
CONT_ASSIGN55911100.00
CONT_ASSIGN55911100.00
CONT_ASSIGN55911100.00
CONT_ASSIGN55911100.00
ALWAYS56544100.00
CONT_ASSIGN57411100.00
CONT_ASSIGN58511100.00
CONT_ASSIGN58611100.00
CONT_ASSIGN60111100.00
CONT_ASSIGN60611100.00
CONT_ASSIGN60711100.00
CONT_ASSIGN61011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
126 1 1
129 4 4
130 4 4
131 4 4
134 1 1
136 3 3
162 1 1
169 4 4
170 4 4
172 4 4
187 4 4
193 4 4
197 4 4
204 1 1
207 1 1
231 1 1
232 1 1
233 1 1
234 1 1
MISSING_ELSE
264 1 1
271 1 1
277 1 1
282 1 1
309 1 1
310 1 1
311 1 1
312 1 1
313 1 1
314 1 1
315 1 1
316 1 1
317 1 1
318 1 1
319 1 1
320 1 1
321 1 1
MISSING_ELSE
326 1 1
331 1 1
335 1 1
339 1 1
358 1 1
362 1 1
375 1 1
383 1 1
387 1 1
390 1 1
393 1 1
415 1 1
421 1 1
425 1 1
429 1 1
446 1 1
450 1 1
453 1 1
454 1 1
499 1 1
500 1 1
501 1 1
502 0 1
503 1 1
504 0 1
MISSING_ELSE
509 1 1
513 1 1
516 1 1
523 1 1
527 1 1
534 1 1
549 1 1
554 1 1
559 4 4
565 1 1
566 1 1
567 1 1
568 1 1
MISSING_ELSE
574 1 1
585 1 1
586 1 1
601 1 1
606 1 1
607 1 1
610 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd
TotalCoveredPercent
Conditions402255.00
Logical402255.00
Non-Logical00
Event00

 LINE       162
 EXPRESSION (((|buf_invalid_alloc)) ? buf_invalid_alloc : buf_valid_alloc)
             -----------1----------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       207
 EXPRESSION (no_match ? (({flash_phy_pkg::NumBuf {(req_i & buf_en_q)}} & buf_alloc)) : '0)
             ----1---
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       271
 EXPRESSION (((|alloc)) ? buf_alloc : buf_match)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       313
 EXPRESSION (req_o && ack_i)
             --1--    --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T3,T4

 LINE       335
 EXPRESSION (no_match ? (((ack_i & flash_rdy) & rd_stages_rdy)) : rd_stages_rdy)
             ----1---
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       358
 EXPRESSION (rd_done && rd_attrs.ecc)
             ---1---    ------2-----
-1--2-StatusTests
01Not Covered
10CoveredT1,T3,T4
11Not Covered

 LINE       383
 EXPRESSION (((data_err | ecc_single_err_o)) ? data_ecc_chk : data_i[(flash_phy_pkg::PlainDataWidth - 1):0])
             ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       421
 EXPRESSION (hint_descram ? ((descramble_req_o & descramble_ack_i)) : fifo_data_valid)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       501
 EXPRESSION (req_o && descramble_i)
             --1--    ------2-----
-1--2-StatusTests
01Not Covered
10CoveredT1,T3,T4
11Not Covered

 LINE       503
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       523
 EXPRESSION 
 Number  Term
      1  forward ? data_int : (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       523
 SUB-EXPRESSION (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data)
                 ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       527
 EXPRESSION (forward ? data_err : data_err_q)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       549
 EXPRESSION (forward ? alloc_q : (fifo_data_ready ? alloc_q2 : '0))
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       549
 SUB-EXPRESSION (fifo_data_ready ? alloc_q2 : '0)
                 -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       574
 EXPRESSION (((|buf_rsp_match)) ? buf_rsp_data : muxed_data)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       586
 EXPRESSION (data_err_o ? ({flash_phy_pkg::BusWidth {1'b1}}) : gen_rd.bus_words_packed[rsp_fifo_rdata.word_sel])
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       601
 EXPRESSION (rsp_fifo_rdata.intg_ecc_en ? (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth]) : '0)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd
Line No.TotalCoveredPercent
Branches 37 25 67.57
TERNARY 162 2 1 50.00
TERNARY 207 2 1 50.00
TERNARY 271 2 1 50.00
TERNARY 335 2 1 50.00
TERNARY 383 2 1 50.00
TERNARY 421 2 1 50.00
TERNARY 523 3 2 66.67
TERNARY 527 2 2 100.00
TERNARY 549 3 3 100.00
TERNARY 574 2 1 50.00
TERNARY 601 2 1 50.00
TERNARY 586 2 1 50.00
IF 231 3 3 100.00
IF 309 4 4 100.00
IF 499 4 2 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 162 ((|buf_invalid_alloc)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 207 (no_match) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 271 ((|alloc)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 335 (no_match) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 383 ((data_err | ecc_single_err_o)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 421 (hint_descram) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 523 (forward) ? -2-: 523 (hint_descram) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T3,T4
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 527 (forward) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 549 (forward) ? -2-: 549 (fifo_data_ready) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T3,T4
0 1 Covered T1,T3,T4
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 574 ((|buf_rsp_match)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 601 (rsp_fifo_rdata.intg_ecc_en) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 586 (data_err_o) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 231 if ((!rst_ni)) -2-: 233 if (idle_o)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T3,T4


LineNo. Expression -1-: 309 if ((!rst_ni)) -2-: 313 if ((req_o && ack_i)) -3-: 320 if (rd_done)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T3,T4
0 0 1 Covered T1,T3,T4
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 499 if ((!rst_ni)) -2-: 501 if ((req_o && descramble_i)) -3-: 503 if ((calc_req_o && calc_ack_i))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 11 11 100.00 10 90.91
Cover properties 0 0 0
Cover sequences 0 0 0
Total 11 11 100.00 10 90.91




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BufferMatchEcc_A 1495666 0 0 0
ExclusiveOps_A 1495666 1491415 0 0
ExclusiveProgHazard_A 1495666 1491415 0 0
ExclusiveState_A 1495666 1491415 0 0
FifoSameDepth_A 1495666 4972 0 0
ForwardCheck_A 1495666 4972 0 0
IdleCheck_A 1495666 9944 0 0
MaxBufs_A 55 55 0 0
OneHotAlloc_A 1495666 1491415 0 0
OneHotMatch_A 1495666 1491415 0 0
OneHotUpdate_A 1495666 1491415 0 0


BufferMatchEcc_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 0 0 0

ExclusiveOps_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 1491415 0 0
T1 5603 5513 0 0
T2 6283 6200 0 0
T3 3688 3596 0 0
T4 86174 86096 0 0
T5 29585 29519 0 0
T6 15992 15911 0 0
T7 138869 138797 0 0
T8 218850 218796 0 0
T9 2911 2824 0 0
T10 18880 18784 0 0

ExclusiveProgHazard_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 1491415 0 0
T1 5603 5513 0 0
T2 6283 6200 0 0
T3 3688 3596 0 0
T4 86174 86096 0 0
T5 29585 29519 0 0
T6 15992 15911 0 0
T7 138869 138797 0 0
T8 218850 218796 0 0
T9 2911 2824 0 0
T10 18880 18784 0 0

ExclusiveState_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 1491415 0 0
T1 5603 5513 0 0
T2 6283 6200 0 0
T3 3688 3596 0 0
T4 86174 86096 0 0
T5 29585 29519 0 0
T6 15992 15911 0 0
T7 138869 138797 0 0
T8 218850 218796 0 0
T9 2911 2824 0 0
T10 18880 18784 0 0

FifoSameDepth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 4972 0 0
T1 5603 110 0 0
T3 3688 12 0 0
T4 86174 87 0 0
T5 29585 222 0 0
T6 15992 300 0 0
T7 138869 89 0 0
T8 218850 173 0 0
T9 2911 12 0 0
T10 18880 252 0 0
T11 4329 60 0 0

ForwardCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 4972 0 0
T1 5603 110 0 0
T3 3688 12 0 0
T4 86174 87 0 0
T5 29585 222 0 0
T6 15992 300 0 0
T7 138869 89 0 0
T8 218850 173 0 0
T9 2911 12 0 0
T10 18880 252 0 0
T11 4329 60 0 0

IdleCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 9944 0 0
T1 5603 220 0 0
T3 3688 24 0 0
T4 86174 174 0 0
T5 29585 444 0 0
T6 15992 600 0 0
T7 138869 178 0 0
T8 218850 346 0 0
T9 2911 24 0 0
T10 18880 504 0 0
T11 4329 120 0 0

MaxBufs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OneHotAlloc_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 1491415 0 0
T1 5603 5513 0 0
T2 6283 6200 0 0
T3 3688 3596 0 0
T4 86174 86096 0 0
T5 29585 29519 0 0
T6 15992 15911 0 0
T7 138869 138797 0 0
T8 218850 218796 0 0
T9 2911 2824 0 0
T10 18880 18784 0 0

OneHotMatch_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 1491415 0 0
T1 5603 5513 0 0
T2 6283 6200 0 0
T3 3688 3596 0 0
T4 86174 86096 0 0
T5 29585 29519 0 0
T6 15992 15911 0 0
T7 138869 138797 0 0
T8 218850 218796 0 0
T9 2911 2824 0 0
T10 18880 18784 0 0

OneHotUpdate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1495666 1491415 0 0
T1 5603 5513 0 0
T2 6283 6200 0 0
T3 3688 3596 0 0
T4 86174 86096 0 0
T5 29585 29519 0 0
T6 15992 15911 0 0
T7 138869 138797 0 0
T8 218850 218796 0 0
T9 2911 2824 0 0
T10 18880 18784 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%