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ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.RvalidKnown_A	0	0	9520791	9130038	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.WreadyKnown_A	0	0	9520791	9130038	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	279	279	0	0
tb.dut.u_reg_core.u_socket.maxN	0	0	279	279	0	0
tb.dut.u_reg_core.wePulse	0	0	9520791	417569	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.InfoNoBiggerThanData_A	0	0	55	55	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.InfoNoBiggerThanData_A	0	0	55	55	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.InfoNoBiggerThanData_A	0	0	55	55	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.InfoNoBiggerThanData_A	0	0	55	55	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.InfoNoBiggerThanData_A	0	0	55	55	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.InfoNoBiggerThanData_A	0	0	55	55	0	0
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.NumCopiesMustBeGreaterZero_A	0	0	55	55	0	0
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.OutputsKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.NumCopiesMustBeGreaterZero_A	0	0	55	55	0	0
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.OutputsKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.NumCopiesMustBeGreaterZero_A	0	0	55	55	0	0
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.OutputsKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.NumCopiesMustBeGreaterZero_A	0	0	55	55	0	0
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.OutputsKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_tl_adapter_eflash.AddrOutKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_tl_adapter_eflash.DataIntgOptions_A	0	0	55	55	0	0
tb.dut.u_tl_adapter_eflash.ReqOutKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_tl_adapter_eflash.SramDwHasByteGranularity_A	0	0	55	55	0	0
tb.dut.u_tl_adapter_eflash.SramDwIsMultipleOfTlulWidth_A	0	0	55	55	0	0
tb.dut.u_tl_adapter_eflash.TlOutKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_tl_adapter_eflash.WdataOutKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_tl_adapter_eflash.WeOutKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_tl_adapter_eflash.WmaskOutKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_tl_adapter_eflash.adapterNoReadOrWrite	0	0	55	55	0	0
tb.dut.u_tl_adapter_eflash.gen_cmd_intg_check.u_cmd_intg_chk.PayLoadWidthCheck	0	0	55	55	0	0
tb.dut.u_tl_adapter_eflash.u_err.dataWidthOnly32_A	0	0	55	55	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.DepthKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.RvalidKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.WreadyKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_tl_adapter_eflash.u_rsp_gen.DataWidthCheck_A	0	0	55	55	0	0
tb.dut.u_tl_adapter_eflash.u_rsp_gen.PayLoadWidthCheck	0	0	55	55	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.DepthKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.RvalidKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.WreadyKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_tl_adapter_eflash.u_sram_byte.gen_non_intg_asserts.StableSignals_A	0	0	1812518	1808370	0	0
tb.dut.u_tl_adapter_eflash.u_sram_byte.u_intg_gen.PayMaxWidthCheck_A	0	0	55	55	0	0
tb.dut.u_tl_adapter_eflash.u_sram_byte.u_sync_fifo.DepthKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_tl_adapter_eflash.u_sram_byte.u_sync_fifo.RvalidKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_tl_adapter_eflash.u_sram_byte.u_sync_fifo.WreadyKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.DepthKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.RvalidKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.WreadyKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_to_prog_fifo.AddrOutKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_to_prog_fifo.DataIntgOptions_A	0	0	55	55	0	0
tb.dut.u_to_prog_fifo.ReqOutKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_to_prog_fifo.SramDwHasByteGranularity_A	0	0	55	55	0	0
tb.dut.u_to_prog_fifo.SramDwIsMultipleOfTlulWidth_A	0	0	55	55	0	0
tb.dut.u_to_prog_fifo.TlOutKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_to_prog_fifo.WdataOutKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_to_prog_fifo.WeOutKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_to_prog_fifo.WmaskOutKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_to_prog_fifo.adapterNoReadOrWrite	0	0	55	55	0	0
tb.dut.u_to_prog_fifo.u_err.dataWidthOnly32_A	0	0	55	55	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.DataKnown_A	0	0	1812518	20077	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.DepthKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.RvalidKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.WreadyKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	1812518	20077	0	0
tb.dut.u_to_prog_fifo.u_rsp_gen.DataWidthCheck_A	0	0	55	55	0	0
tb.dut.u_to_prog_fifo.u_rsp_gen.PayLoadWidthCheck	0	0	55	55	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.DepthKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.RvalidKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.WreadyKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_to_prog_fifo.u_sram_byte.gen_non_intg_asserts.StableSignals_A	0	0	1812518	1808370	0	0
tb.dut.u_to_prog_fifo.u_sram_byte.u_intg_gen.PayMaxWidthCheck_A	0	0	55	55	0	0
tb.dut.u_to_prog_fifo.u_sram_byte.u_sync_fifo.DepthKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_to_prog_fifo.u_sram_byte.u_sync_fifo.RvalidKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_to_prog_fifo.u_sram_byte.u_sync_fifo.WreadyKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.DepthKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.RvalidKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.WreadyKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_to_rd_fifo.AddrOutKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_to_rd_fifo.DataIntgOptions_A	0	0	55	55	0	0
tb.dut.u_to_rd_fifo.ReqOutKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_to_rd_fifo.SramDwHasByteGranularity_A	0	0	55	55	0	0
tb.dut.u_to_rd_fifo.SramDwIsMultipleOfTlulWidth_A	0	0	55	55	0	0
tb.dut.u_to_rd_fifo.TlOutKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_to_rd_fifo.WdataOutKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_to_rd_fifo.WeOutKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_to_rd_fifo.WmaskOutKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_to_rd_fifo.adapterNoReadOrWrite	0	0	55	55	0	0
tb.dut.u_to_rd_fifo.rvalidHighReqFifoEmpty	0	0	1812518	8629	0	0
tb.dut.u_to_rd_fifo.rvalidHighWhenRspFifoFull	0	0	1812518	8629	0	0
tb.dut.u_to_rd_fifo.u_err.dataWidthOnly32_A	0	0	55	55	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.DataKnown_A	0	0	1812518	18903	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.DepthKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.RvalidKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.WreadyKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	1812518	18903	0	0
tb.dut.u_to_rd_fifo.u_rsp_gen.DataWidthCheck_A	0	0	55	55	0	0
tb.dut.u_to_rd_fifo.u_rsp_gen.PayLoadWidthCheck	0	0	55	55	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.DataKnown_A	0	0	1812518	18903	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.DepthKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.RvalidKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.WreadyKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	1812518	18903	0	0
tb.dut.u_to_rd_fifo.u_sram_byte.gen_non_intg_asserts.StableSignals_A	0	0	1812518	1808370	0	0
tb.dut.u_to_rd_fifo.u_sram_byte.u_intg_gen.PayMaxWidthCheck_A	0	0	55	55	0	0
tb.dut.u_to_rd_fifo.u_sram_byte.u_sync_fifo.DepthKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_to_rd_fifo.u_sram_byte.u_sync_fifo.RvalidKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_to_rd_fifo.u_sram_byte.u_sync_fifo.WreadyKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.DataKnown_A	0	0	1812518	8629	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.DepthKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.RvalidKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.WreadyKnown_A	0	0	1812518	1808370	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	1812518	8629	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.i_valid_random.RoundRobin_A	0	0	1812518	0	0	55
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.i_valid_random.RoundRobin_A	0	0	1812518	0	0	55
tb.dut.u_flash_hw_if.u_page_cnt.OutSet_A	0	0	1812518	0	0	55
tb.dut.u_flash_hw_if.u_word_cnt.OutSet_A	0	0	1812518	0	0	55

---

Detail Report for Cover Sequences

Cover Sequences Uncovered:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	1812556	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	1812556	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	1812556	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	1812556	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	1812556	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	1812556	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	1812556	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	1812556	0	0	0

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	1812556	93	93	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	1812556	150568	150568	55

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	1812556	93	93	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	1812556	150568	150568	55