Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 50.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_eflash_tl_agent.cov::m_tl_a_chan_cov_cg 0.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_eflash_tl_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
0.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_eflash_tl_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 134 0 0.00
Crosses 3 3 0 0.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_eflash_tl_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 1 0 0.00 100 1 1 0
cp_opcode 3 3 0 0.00 100 1 1 0
cp_size 1 1 0 0.00 100 1 1 0
cp_source 129 129 0 0.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_eflash_tl_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 3 0 0.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for cp_mask

Uncovered bins
NAMECOUNTAT LEASTNUMBER
all_enables 0 1 1


Excluded/Illegal bins
NAMECOUNTSTATUS
others 0 Excluded



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 3 0 0.00


User Defined Bins for cp_opcode

Uncovered bins
NAMECOUNTAT LEASTNUMBER
values_4 0 1 1
values_0 0 1 1
values_1 0 1 1



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for cp_size

Uncovered bins
NAMECOUNTAT LEASTNUMBER
biggest_size 0 1 1


Excluded/Illegal bins
NAMECOUNTSTATUS
others 0 Excluded



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 129 0 0.00


User Defined Bins for cp_source

Uncovered bins
NAMECOUNTAT LEASTNUMBER
valid_sources_00 0 1 1
valid_sources_01 0 1 1
valid_sources_02 0 1 1
valid_sources_03 0 1 1
valid_sources_04 0 1 1
valid_sources_05 0 1 1
valid_sources_06 0 1 1
valid_sources_07 0 1 1
valid_sources_08 0 1 1
valid_sources_09 0 1 1
valid_sources_0a 0 1 1
valid_sources_0b 0 1 1
valid_sources_0c 0 1 1
valid_sources_0d 0 1 1
valid_sources_0e 0 1 1
valid_sources_0f 0 1 1
valid_sources_10 0 1 1
valid_sources_11 0 1 1
valid_sources_12 0 1 1
valid_sources_13 0 1 1
valid_sources_14 0 1 1
valid_sources_15 0 1 1
valid_sources_16 0 1 1
valid_sources_17 0 1 1
valid_sources_18 0 1 1
valid_sources_19 0 1 1
valid_sources_1a 0 1 1
valid_sources_1b 0 1 1
valid_sources_1c 0 1 1
valid_sources_1d 0 1 1
valid_sources_1e 0 1 1
valid_sources_1f 0 1 1
valid_sources_20 0 1 1
valid_sources_21 0 1 1
valid_sources_22 0 1 1
valid_sources_23 0 1 1
valid_sources_24 0 1 1
valid_sources_25 0 1 1
valid_sources_26 0 1 1
valid_sources_27 0 1 1
valid_sources_28 0 1 1
valid_sources_29 0 1 1
valid_sources_2a 0 1 1
valid_sources_2b 0 1 1
valid_sources_2c 0 1 1
valid_sources_2d 0 1 1
valid_sources_2e 0 1 1
valid_sources_2f 0 1 1
valid_sources_30 0 1 1
valid_sources_31 0 1 1
valid_sources_32 0 1 1
valid_sources_33 0 1 1
valid_sources_34 0 1 1
valid_sources_35 0 1 1
valid_sources_36 0 1 1
valid_sources_37 0 1 1
valid_sources_38 0 1 1
valid_sources_39 0 1 1
valid_sources_3a 0 1 1
valid_sources_3b 0 1 1
valid_sources_3c 0 1 1
valid_sources_3d 0 1 1
valid_sources_3e 0 1 1
valid_sources_3f 0 1 1
valid_sources_40 0 1 1
valid_sources_41 0 1 1
valid_sources_42 0 1 1
valid_sources_43 0 1 1
valid_sources_44 0 1 1
valid_sources_45 0 1 1
valid_sources_46 0 1 1
valid_sources_47 0 1 1
valid_sources_48 0 1 1
valid_sources_49 0 1 1
valid_sources_4a 0 1 1
valid_sources_4b 0 1 1
valid_sources_4c 0 1 1
valid_sources_4d 0 1 1
valid_sources_4e 0 1 1
valid_sources_4f 0 1 1
valid_sources_50 0 1 1
valid_sources_51 0 1 1
valid_sources_52 0 1 1
valid_sources_53 0 1 1
valid_sources_54 0 1 1
valid_sources_55 0 1 1
valid_sources_56 0 1 1
valid_sources_57 0 1 1
valid_sources_58 0 1 1
valid_sources_59 0 1 1
valid_sources_5a 0 1 1
valid_sources_5b 0 1 1
valid_sources_5c 0 1 1
valid_sources_5d 0 1 1
valid_sources_5e 0 1 1
valid_sources_5f 0 1 1
valid_sources_60 0 1 1
valid_sources_61 0 1 1
valid_sources_62 0 1 1
valid_sources_63 0 1 1
valid_sources_64 0 1 1
valid_sources_65 0 1 1
valid_sources_66 0 1 1
valid_sources_67 0 1 1
valid_sources_68 0 1 1
valid_sources_69 0 1 1
valid_sources_6a 0 1 1
valid_sources_6b 0 1 1
valid_sources_6c 0 1 1
valid_sources_6d 0 1 1
valid_sources_6e 0 1 1
valid_sources_6f 0 1 1
valid_sources_70 0 1 1
valid_sources_71 0 1 1
valid_sources_72 0 1 1
valid_sources_73 0 1 1
valid_sources_74 0 1 1
valid_sources_75 0 1 1
valid_sources_76 0 1 1
valid_sources_77 0 1 1
valid_sources_78 0 1 1
valid_sources_79 0 1 1
valid_sources_7a 0 1 1
valid_sources_7b 0 1 1
valid_sources_7c 0 1 1
valid_sources_7d 0 1 1
valid_sources_7e 0 1 1
valid_sources_7f 0 1 1
valid_sources_80 0 1 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 3 0 0.00 3


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Uncovered bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTNUMBER
* * * -- -- 3


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1060076 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 614583 1 T1 1782 T2 638 T3 827



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values_4 1246743 1 T1 2836 T2 594 T3 802
values_0 212852 1 T1 211 T2 225 T3 279
values_1 215064 1 T1 211 T2 241 T3 246



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 759725 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 914934 1 T1 2084 T2 755 T3 938



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources_00 6900 1 T1 15 T2 5 T4 1
valid_sources_01 5988 1 T1 15 T2 2 T6 158
valid_sources_02 5363 1 T1 10 T2 3 T4 2
valid_sources_03 5547 1 T1 22 T2 2 T4 1
valid_sources_04 6570 1 T1 6 T2 4 T6 173
valid_sources_05 6084 1 T1 8 T2 3 T6 172
valid_sources_06 5876 1 T1 5 T2 1 T4 1
valid_sources_07 6201 1 T1 17 T2 3 T4 1
valid_sources_08 7054 1 T1 4 T2 5 T6 158
valid_sources_09 6781 1 T1 11 T2 4 T6 158
valid_sources_0a 5989 1 T1 15 T2 7 T4 1
valid_sources_0b 9609 1 T1 12 T2 4 T6 144
valid_sources_0c 6475 1 T1 6 T2 2 T6 150
valid_sources_0d 5668 1 T1 8 T2 2 T4 1
valid_sources_0e 7054 1 T1 10 T2 4 T4 1
valid_sources_0f 6997 1 T1 9 T2 3 T6 142
valid_sources_10 7080 1 T1 9 T2 4 T4 1
valid_sources_11 5970 1 T1 18 T2 2 T6 166
valid_sources_12 6944 1 T1 21 T2 4 T4 1
valid_sources_13 7466 1 T1 13 T2 7 T6 147
valid_sources_14 5443 1 T1 17 T2 7 T6 147
valid_sources_15 6949 1 T1 10 T2 2 T6 154
valid_sources_16 5879 1 T1 14 T2 1 T4 1
valid_sources_17 6553 1 T1 7 T2 3 T6 161
valid_sources_18 5861 1 T1 12 T2 5 T4 2
valid_sources_19 5867 1 T1 14 T2 7 T6 167
valid_sources_1a 6298 1 T1 18 T2 5 T4 2
valid_sources_1b 5993 1 T1 10 T2 4 T4 1
valid_sources_1c 9822 1 T1 26 T2 7 T6 148
valid_sources_1d 6089 1 T1 11 T2 8 T4 1
valid_sources_1e 6654 1 T1 10 T2 3 T6 147
valid_sources_1f 5780 1 T1 13 T2 5 T6 147
valid_sources_20 6587 1 T1 2 T2 3 T4 1
valid_sources_21 11461 1 T1 2 T2 1 T4 1
valid_sources_22 6357 1 T1 23 T2 6 T4 2
valid_sources_23 8010 1 T1 16 T2 3 T3 1327
valid_sources_24 6126 1 T1 8 T2 1 T6 152
valid_sources_25 5911 1 T1 5 T2 4 T6 159
valid_sources_26 6116 1 T1 11 T2 3 T6 135
valid_sources_27 7219 1 T1 19 T2 5 T4 5
valid_sources_28 5697 1 T1 8 T6 150 T9 16
valid_sources_29 6053 1 T1 29 T2 3 T6 172
valid_sources_2a 5468 1 T1 13 T2 5 T4 1
valid_sources_2b 6613 1 T1 9 T2 4 T4 1
valid_sources_2c 5928 1 T1 15 T2 4 T4 1
valid_sources_2d 6674 1 T1 7 T2 3 T6 149
valid_sources_2e 6645 1 T1 16 T2 2 T6 146
valid_sources_2f 5928 1 T1 7 T2 3 T6 137
valid_sources_30 6620 1 T1 11 T2 1 T6 150
valid_sources_31 9169 1 T1 6 T2 4 T4 2
valid_sources_32 6811 1 T1 20 T2 3 T6 152
valid_sources_33 6396 1 T1 6 T2 2 T6 150
valid_sources_34 5544 1 T1 13 T2 5 T6 158
valid_sources_35 6169 1 T1 13 T2 1 T6 163
valid_sources_36 6532 1 T1 8 T4 1 T6 172
valid_sources_37 5910 1 T1 13 T2 3 T6 146
valid_sources_38 5515 1 T1 16 T2 6 T6 155
valid_sources_39 5524 1 T1 20 T2 2 T4 1
valid_sources_3a 6151 1 T1 14 T2 6 T6 149
valid_sources_3b 6176 1 T1 9 T2 9 T4 1
valid_sources_3c 6028 1 T1 19 T2 5 T6 171
valid_sources_3d 5982 1 T1 8 T2 6 T4 1
valid_sources_3e 6500 1 T1 10 T2 5 T4 1
valid_sources_3f 6012 1 T1 15 T2 5 T4 2
valid_sources_40 5869 1 T1 8 T2 5 T4 3
valid_sources_41 5862 1 T1 17 T2 7 T6 169
valid_sources_42 6452 1 T1 12 T2 3 T4 1
valid_sources_43 6869 1 T1 8 T2 9 T6 147
valid_sources_44 6244 1 T1 18 T2 4 T4 1
valid_sources_45 6233 1 T1 6 T2 5 T4 1
valid_sources_46 6598 1 T1 19 T2 3 T6 155
valid_sources_47 6017 1 T1 15 T2 3 T6 160
valid_sources_48 6563 1 T1 4 T2 6 T6 155
valid_sources_49 6080 1 T1 14 T2 2 T6 150
valid_sources_4a 6024 1 T1 12 T2 6 T6 113
valid_sources_4b 5907 1 T1 14 T2 3 T4 1
valid_sources_4c 6362 1 T1 19 T2 4 T6 156
valid_sources_4d 5717 1 T1 20 T2 4 T6 168
valid_sources_4e 6557 1 T1 15 T2 6 T6 153
valid_sources_4f 6646 1 T1 17 T2 6 T6 164
valid_sources_50 6387 1 T1 11 T2 4 T4 1
valid_sources_51 6507 1 T1 17 T2 3 T6 137
valid_sources_52 5992 1 T1 12 T2 10 T6 143
valid_sources_53 5925 1 T1 8 T2 3 T6 131
valid_sources_54 7054 1 T1 12 T2 7 T6 152
valid_sources_55 6215 1 T1 13 T2 2 T4 1
valid_sources_56 6035 1 T1 18 T2 5 T6 159
valid_sources_57 7015 1 T1 8 T2 6 T6 160
valid_sources_58 5329 1 T1 18 T2 2 T6 154
valid_sources_59 8537 1 T1 11 T2 3 T4 1
valid_sources_5a 6109 1 T1 11 T2 5 T6 151
valid_sources_5b 6148 1 T1 15 T2 4 T6 155
valid_sources_5c 6373 1 T1 17 T2 3 T4 1
valid_sources_5d 5803 1 T1 10 T2 5 T6 155
valid_sources_5e 6131 1 T1 12 T2 3 T6 151
valid_sources_5f 5698 1 T1 13 T2 5 T4 1
valid_sources_60 6996 1 T1 11 T2 3 T6 155
valid_sources_61 5992 1 T1 13 T2 3 T6 150
valid_sources_62 6917 1 T1 10 T2 5 T6 149
valid_sources_63 6569 1 T1 17 T6 149 T9 15
valid_sources_64 5912 1 T1 10 T2 3 T4 1
valid_sources_65 6363 1 T1 6 T2 3 T6 149
valid_sources_66 6053 1 T1 8 T2 4 T6 153
valid_sources_67 5685 1 T1 10 T2 2 T6 139
valid_sources_68 33366 1 T1 17 T2 2 T4 3
valid_sources_69 6124 1 T1 20 T2 2 T6 177
valid_sources_6a 7084 1 T1 4 T2 3 T6 139
valid_sources_6b 9767 1 T1 9 T2 6 T6 165
valid_sources_6c 6549 1 T1 17 T2 2 T6 165
valid_sources_6d 7792 1 T1 23 T2 7 T4 1
valid_sources_6e 6365 1 T1 10 T2 7 T6 165
valid_sources_6f 6323 1 T1 10 T2 2 T6 160
valid_sources_70 6349 1 T1 9 T2 4 T4 1
valid_sources_71 5558 1 T1 16 T2 4 T6 176
valid_sources_72 6076 1 T1 19 T2 6 T6 122
valid_sources_73 6304 1 T1 11 T2 9 T4 2
valid_sources_74 5852 1 T1 17 T2 2 T6 160
valid_sources_75 6095 1 T1 5 T2 4 T6 131
valid_sources_76 5922 1 T1 17 T2 1 T6 157
valid_sources_77 6518 1 T1 3 T2 3 T6 173
valid_sources_78 6605 1 T1 23 T2 7 T4 1
valid_sources_79 5953 1 T1 17 T2 7 T6 155
valid_sources_7a 6627 1 T1 5 T2 2 T6 154
valid_sources_7b 6089 1 T1 12 T2 2 T6 141
valid_sources_7c 7080 1 T1 9 T2 1 T6 175
valid_sources_7d 5323 1 T1 11 T2 3 T6 155
valid_sources_7e 5362 1 T1 12 T2 5 T6 150
valid_sources_7f 5989 1 T1 20 T2 5 T4 1
valid_sources_80 6384 1 T1 17 T2 2 T6 146



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values_4 all_enables biggest_size 448102 1 T1 1479 T2 340 T3 471
values_0 all_enables biggest_size 100387 1 T1 162 T2 156 T3 190
values_1 all_enables biggest_size 66094 1 T1 141 T2 142 T3 166

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%