Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
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Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
35.29 35.29 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block] 35.29 1 100 1 64 64




Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
35.29 1 100 1 64 64




Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 11 3 8 72.73
Crosses 40 30 10 25.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 5 0 5 100.00 100 1 1 0
cp_tl_intg_err_type 4 3 1 25.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 40 30 10 25.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values_0 156412 1 T1 462 T2 91 T3 127
values_1 655035 1 T1 684 T2 181 T3 202
values_2 168177 1 T1 218 T2 87 T3 118
values_3 101416 1 T1 112 T2 63 T3 53
values_4 615450 1 T1 1782 T2 638 T3 827



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 3 1 25.00


Automatically Generated Bins for cp_tl_intg_err_type

Uncovered bins
NAMECOUNTAT LEASTNUMBER
auto_TlIntgErrCmd 0 1 1
auto_TlIntgErrData 0 1 1
auto_TlIntgErrBoth 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto_TlIntgErrNone 1696490 1 T1 3258 T2 1060 T3 1327



Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1249585 1 T1 2836 T2 594 T3 802
auto[1] 446905 1 T1 422 T2 466 T3 525



Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 40 30 10 25.00 30


Automatically Generated Cross Bins for cr_all

Element holes
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTNUMBER
[auto_TlIntgErrCmd , auto_TlIntgErrData , auto_TlIntgErrBoth] * * -- -- 30


Covered bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto_TlIntgErrNone values_0 auto[0] 154607 1 T1 462 T2 91 T3 127
auto_TlIntgErrNone values_0 auto[1] 1805 1 T16 66 T17 132 T18 90
auto_TlIntgErrNone values_1 auto[0] 558480 1 T1 643 T2 114 T3 143
auto_TlIntgErrNone values_1 auto[1] 96555 1 T1 41 T2 67 T3 59
auto_TlIntgErrNone values_2 auto[0] 56398 1 T1 171 T2 32 T3 46
auto_TlIntgErrNone values_2 auto[1] 111779 1 T1 47 T2 55 T3 72
auto_TlIntgErrNone values_3 auto[0] 31807 1 T1 81 T2 17 T3 15
auto_TlIntgErrNone values_3 auto[1] 69609 1 T1 31 T2 46 T3 38
auto_TlIntgErrNone values_4 auto[0] 448293 1 T1 1479 T2 340 T3 471
auto_TlIntgErrNone values_4 auto[1] 167157 1 T1 303 T2 298 T3 356

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