Group : dv_lib_pkg::bit_toggle_cg_wrap::bit_toggle_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : dv_lib_pkg::bit_toggle_cg_wrap::bit_toggle_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 44.64 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv

14 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
uvm_test_top.env.m_eflash_tl_agent.cov::PutFullData_mask_not_match_size 0.00 1 100 1 64 64
uvm_test_top.env.m_eflash_tl_agent.cov::addr_not_align_mask 0.00 1 100 1 64 64
uvm_test_top.env.m_eflash_tl_agent.cov::addr_not_align_size 0.00 1 100 1 64 64
uvm_test_top.env.m_eflash_tl_agent.cov::invalid_a_opcode 0.00 1 100 1 64 64
uvm_test_top.env.m_eflash_tl_agent.cov::m_outstanding_item_w_same_addr_cov_obj 0.00 1 100 1 64 64
uvm_test_top.env.m_eflash_tl_agent.cov::mask_not_in_enabled_lanes 0.00 1 100 1 64 64
uvm_test_top.env.m_eflash_tl_agent.cov::size_over_max 0.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::m_outstanding_item_w_same_addr_cov_obj 25.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::PutFullData_mask_not_match_size 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::addr_not_align_mask 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::addr_not_align_size 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::invalid_a_opcode 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::mask_not_in_enabled_lanes 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::size_over_max 100.00 1 100 1 64 64




Group Instance : uvm_test_top.env.m_eflash_tl_agent.cov::PutFullData_mask_not_match_size
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
0.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_eflash_tl_agent.cov::PutFullData_mask_not_match_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 4 0 0.00


Variables for Group Instance uvm_test_top.env.m_eflash_tl_agent.cov::PutFullData_mask_not_match_size
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 2 0 0.00 100 1 1 0
cp_value 2 2 0 0.00 100 1 1 2



Group Instance : uvm_test_top.env.m_eflash_tl_agent.cov::addr_not_align_mask
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
0.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_eflash_tl_agent.cov::addr_not_align_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 4 0 0.00


Variables for Group Instance uvm_test_top.env.m_eflash_tl_agent.cov::addr_not_align_mask
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 2 0 0.00 100 1 1 0
cp_value 2 2 0 0.00 100 1 1 2



Group Instance : uvm_test_top.env.m_eflash_tl_agent.cov::addr_not_align_size
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
0.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_eflash_tl_agent.cov::addr_not_align_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 4 0 0.00


Variables for Group Instance uvm_test_top.env.m_eflash_tl_agent.cov::addr_not_align_size
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 2 0 0.00 100 1 1 0
cp_value 2 2 0 0.00 100 1 1 2



Group Instance : uvm_test_top.env.m_eflash_tl_agent.cov::invalid_a_opcode
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
0.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_eflash_tl_agent.cov::invalid_a_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 4 0 0.00


Variables for Group Instance uvm_test_top.env.m_eflash_tl_agent.cov::invalid_a_opcode
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 2 0 0.00 100 1 1 0
cp_value 2 2 0 0.00 100 1 1 2



Group Instance : uvm_test_top.env.m_eflash_tl_agent.cov::m_outstanding_item_w_same_addr_cov_obj
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
0.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_eflash_tl_agent.cov::m_outstanding_item_w_same_addr_cov_obj

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 4 0 0.00


Variables for Group Instance uvm_test_top.env.m_eflash_tl_agent.cov::m_outstanding_item_w_same_addr_cov_obj
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 2 0 0.00 100 1 1 0
cp_value 2 2 0 0.00 100 1 1 2



Group Instance : uvm_test_top.env.m_eflash_tl_agent.cov::mask_not_in_enabled_lanes
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
0.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_eflash_tl_agent.cov::mask_not_in_enabled_lanes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 4 0 0.00


Variables for Group Instance uvm_test_top.env.m_eflash_tl_agent.cov::mask_not_in_enabled_lanes
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 2 0 0.00 100 1 1 0
cp_value 2 2 0 0.00 100 1 1 2



Group Instance : uvm_test_top.env.m_eflash_tl_agent.cov::size_over_max
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
0.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_eflash_tl_agent.cov::size_over_max

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 4 0 0.00


Variables for Group Instance uvm_test_top.env.m_eflash_tl_agent.cov::size_over_max
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 2 0 0.00 100 1 1 0
cp_value 2 2 0 0.00 100 1 1 2



Group Instance : uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::m_outstanding_item_w_same_addr_cov_obj
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
25.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::m_outstanding_item_w_same_addr_cov_obj

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 3 1 25.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::m_outstanding_item_w_same_addr_cov_obj
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 2 0 0.00 100 1 1 0
cp_value 2 1 1 50.00 100 1 1 2



Group Instance : uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::PutFullData_mask_not_match_size
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::PutFullData_mask_not_match_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::PutFullData_mask_not_match_size
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::addr_not_align_mask
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::addr_not_align_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::addr_not_align_mask
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::addr_not_align_size
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::addr_not_align_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::addr_not_align_size
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::invalid_a_opcode
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::invalid_a_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::invalid_a_opcode
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::mask_not_in_enabled_lanes
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::mask_not_in_enabled_lanes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::mask_not_in_enabled_lanes
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::size_over_max
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::size_over_max

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::size_over_max
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 2 0 0.00


User Defined Bins for cp_transitions

Uncovered bins
NAMECOUNTAT LEASTNUMBER
falling 0 1 1
rising 0 1 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[0] - auto[1]] -- -- 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 2 0 0.00


User Defined Bins for cp_transitions

Uncovered bins
NAMECOUNTAT LEASTNUMBER
falling 0 1 1
rising 0 1 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[0] - auto[1]] -- -- 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 2 0 0.00


User Defined Bins for cp_transitions

Uncovered bins
NAMECOUNTAT LEASTNUMBER
falling 0 1 1
rising 0 1 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[0] - auto[1]] -- -- 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 2 0 0.00


User Defined Bins for cp_transitions

Uncovered bins
NAMECOUNTAT LEASTNUMBER
falling 0 1 1
rising 0 1 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[0] - auto[1]] -- -- 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 2 0 0.00


User Defined Bins for cp_transitions

Uncovered bins
NAMECOUNTAT LEASTNUMBER
falling 0 1 1
rising 0 1 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[0] - auto[1]] -- -- 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 2 0 0.00


User Defined Bins for cp_transitions

Uncovered bins
NAMECOUNTAT LEASTNUMBER
falling 0 1 1
rising 0 1 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[0] - auto[1]] -- -- 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 2 0 0.00


User Defined Bins for cp_transitions

Uncovered bins
NAMECOUNTAT LEASTNUMBER
falling 0 1 1
rising 0 1 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[0] - auto[1]] -- -- 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 2 0 0.00


User Defined Bins for cp_transitions

Uncovered bins
NAMECOUNTAT LEASTNUMBER
falling 0 1 1
rising 0 1 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1696490 1 T1 3258 T2 1060 T3 1327


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
falling 4409 1 T16 164 T17 359 T18 196
rising 4407 1 T16 165 T17 359 T18 195



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 15512 1 T16 446 T17 1211 T18 691
auto[1] 6319 1 T16 226 T17 497 T18 274


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
falling 4671 1 T16 145 T17 373 T18 221
rising 4666 1 T16 145 T17 372 T18 221



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 14872 1 T16 485 T17 1120 T18 651
auto[1] 6959 1 T16 187 T17 588 T18 314


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
falling 4671 1 T16 145 T17 373 T18 221
rising 4666 1 T16 145 T17 372 T18 221



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 14872 1 T16 485 T17 1120 T18 651
auto[1] 6959 1 T16 187 T17 588 T18 314


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
falling 4002 1 T16 115 T17 329 T18 203
rising 3999 1 T16 115 T17 328 T18 203



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 16338 1 T16 550 T17 1291 T18 668
auto[1] 5493 1 T16 122 T17 417 T18 297


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
falling 4818 1 T16 159 T17 381 T18 224
rising 4824 1 T16 160 T17 382 T18 225



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 14198 1 T16 409 T17 1115 T18 621
auto[1] 7633 1 T16 263 T17 593 T18 344


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
falling 4307 1 T16 133 T17 343 T18 184
rising 4308 1 T16 133 T17 343 T18 184



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 15942 1 T16 478 T17 1214 T18 712
auto[1] 5889 1 T16 194 T17 494 T18 253

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%