Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_count
SCORELINECONDTOGGLEFSMBRANCHASSERT
47.92 81.25 47.51 46.26 16.67

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_count_0/rtl/prim_count.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_flash_hw_if.u_word_cnt 45.41 75.00 41.18 45.45 20.00
tb.dut.u_flash_hw_if.u_page_cnt 53.35 87.50 53.85 47.06 25.00



Module Instance : tb.dut.u_flash_hw_if.u_word_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
45.41 75.00 41.18 45.45 20.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
47.24 77.78 41.18 50.00 20.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
43.26 90.59 13.46 0.00 68.97 u_flash_hw_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_cnts[0].u_buf 100.00 100.00
gen_cnts[0].u_cnt_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_page_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
53.35 87.50 53.85 47.06 25.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
56.91 91.67 53.85 57.14 25.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
43.26 90.59 13.46 0.00 68.97 u_flash_hw_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_cnts[0].u_buf 100.00 100.00
gen_cnts[0].u_cnt_flop 100.00 100.00 100.00
gen_cnts[1].u_buf 100.00 100.00
gen_cnts[1].u_cnt_flop 100.00 100.00 100.00

Line Coverage for Module : prim_count ( parameter Width=9,OutSelDnCnt=0,CntStyle=1 )
Line Coverage for Module self-instances :
SCORELINE
53.35 87.50
tb.dut.u_flash_hw_if.u_page_cnt

Line No.TotalCoveredPercent
TOTAL161487.50
CONT_ASSIGN5111100.00
CONT_ASSIGN5611100.00
ALWAYS6633100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15211100.00
CONT_ASSIGN15911100.00
ALWAYS1676466.67
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_count_0/rtl/prim_count.sv' or '../src/lowrisc_prim_count_0/rtl/prim_count.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
51 1 1
56 1 1
66 1 1
67 1 1
68 1 1
69 unreachable
MISSING_ELSE
75 2 2
151 1 1
152 1 1
159 1 1
167 1 1
168 1 1
169 1 1
170 1 1
171 0 1
172 0 1
MISSING_ELSE


Line Coverage for Module : prim_count ( parameter Width=10,OutSelDnCnt=0,CntStyle=0 )
Line Coverage for Module self-instances :
SCORELINE
45.41 75.00
tb.dut.u_flash_hw_if.u_word_cnt

Line No.TotalCoveredPercent
TOTAL322475.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5600
ALWAYS664375.00
CONT_ASSIGN7511100.00
ALWAYS1036466.67
ALWAYS1148562.50
CONT_ASSIGN12611100.00
CONT_ASSIGN12711100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN15911100.00
ALWAYS1676466.67
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_count_0/rtl/prim_count.sv' or '../src/lowrisc_prim_count_0/rtl/prim_count.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
51 1 1
56 unreachable
66 1 1
67 1 1
68 1 1
69 0 1
MISSING_ELSE
75 1 1
103 1 1
104 1 1
105 1 1
106 0 1
107 1 1
108 0 1
MISSING_ELSE
114 1 1
115 1 1
116 1 1
117 0 1
118 1 1
119 0 1
120 1 1
121 0 1
MISSING_ELSE
126 1 1
127 1 1
128 1 1
142 1 1
144 1 1
159 1 1
167 1 1
168 1 1
169 1 1
170 1 1
171 0 1
172 0 1
MISSING_ELSE


Cond Coverage for Module : prim_count ( parameter Width=9,OutSelDnCnt=0,CntStyle=1 )
Cond Coverage for Module self-instances :
SCORECOND
53.35 53.85
tb.dut.u_flash_hw_if.u_page_cnt

TotalCoveredPercent
Conditions13753.85
Logical13753.85
Non-Logical00
Event00

 LINE       75
 EXPRESSION (clr_up_cnt ? '0 : (set_up_cnt ? set_cnt_i : (((en_i & (up_cnt_q[0] < max_val))) ? ((up_cnt_q[0] + step_i)) : up_cnt_q[0])))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       75
 SUB-EXPRESSION (set_up_cnt ? set_cnt_i : (((en_i & (up_cnt_q[0] < max_val))) ? ((up_cnt_q[0] + step_i)) : up_cnt_q[0]))
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       75
 SUB-EXPRESSION (((en_i & (up_cnt_q[0] < max_val))) ? ((up_cnt_q[0] + step_i)) : up_cnt_q[0])
                 -----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       75
 EXPRESSION (clr_up_cnt ? '0 : (set_up_cnt ? set_cnt_i : (((en_i & (up_cnt_q[1] < max_val))) ? ((up_cnt_q[1] + step_i)) : up_cnt_q[1])))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       75
 SUB-EXPRESSION (set_up_cnt ? set_cnt_i : (((en_i & (up_cnt_q[1] < max_val))) ? ((up_cnt_q[1] + step_i)) : up_cnt_q[1]))
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       75
 SUB-EXPRESSION (((en_i & (up_cnt_q[1] < max_val))) ? ((up_cnt_q[1] + step_i)) : up_cnt_q[1])
                 -----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       159
 EXPRESSION ((cmp_valid == CmpValid) ? err : ((cmp_valid == CmpInvalid) ? '0 : 1'b1))
             -----------1-----------
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       159
 SUB-EXPRESSION ((cmp_valid == CmpInvalid) ? '0 : 1'b1)
                 ------------1------------
-1-StatusTests
0Unreachable
1Unreachable

Cond Coverage for Module : prim_count ( parameter Width=10,OutSelDnCnt=0,CntStyle=0 )
Cond Coverage for Module self-instances :
SCORECOND
45.41 41.18
tb.dut.u_flash_hw_if.u_word_cnt

TotalCoveredPercent
Conditions17741.18
Logical17741.18
Non-Logical00
Event00

 LINE       68
 EXPRESSION (set_i && (CntStyle == CrossCnt))
             --1--    -----------2----------
-1--2-StatusTests
0-CoveredT1,T2,T3
1-Not Covered

 LINE       75
 EXPRESSION (clr_up_cnt ? '0 : (set_up_cnt ? set_cnt_i : (((en_i & (up_cnt_q[0] < max_val))) ? ((up_cnt_q[0] + step_i)) : up_cnt_q[0])))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       75
 SUB-EXPRESSION (set_up_cnt ? set_cnt_i : (((en_i & (up_cnt_q[0] < max_val))) ? ((up_cnt_q[0] + step_i)) : up_cnt_q[0]))
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1Unreachable

 LINE       75
 SUB-EXPRESSION (((en_i & (up_cnt_q[0] < max_val))) ? ((up_cnt_q[0] + step_i)) : up_cnt_q[0])
                 -----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       107
 EXPRESSION ((cmp_valid == CmpInvalid) && set_i)
             ------------1------------    --2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       120
 EXPRESSION (en_i && (gen_cross_cnt_hardening.down_cnt > '0))
             --1-    -------------------2-------------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       159
 EXPRESSION ((cmp_valid == CmpValid) ? err : ((cmp_valid == CmpInvalid) ? '0 : 1'b1))
             -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       159
 SUB-EXPRESSION ((cmp_valid == CmpInvalid) ? '0 : 1'b1)
                 ------------1------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Branch Coverage for Module : prim_count ( parameter Width=9,OutSelDnCnt=0,CntStyle=1 )
Branch Coverage for Module self-instances :
SCOREBRANCH
53.35 47.06
tb.dut.u_flash_hw_if.u_page_cnt

Line No.TotalCoveredPercent
Branches 17 8 47.06
TERNARY 159 3 1 33.33
TERNARY 75 4 1 25.00
TERNARY 75 4 2 50.00
IF 66 3 2 66.67
IF 167 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_count_0/rtl/prim_count.sv' or '../src/lowrisc_prim_count_0/rtl/prim_count.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 159 ((cmp_valid == CmpValid)) ? -2-: 159 ((cmp_valid == CmpInvalid)) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Not Covered


LineNo. Expression -1-: 75 (clr_up_cnt) ? -2-: 75 (set_up_cnt) ? -3-: 75 ((en_i & (up_cnt_q[0] < max_val))) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 75 (clr_up_cnt) ? -2-: 75 (set_up_cnt) ? -3-: 75 ((en_i & (up_cnt_q[1] < max_val))) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 66 if ((!rst_ni)) -2-: 68 if ((set_i && (CntStyle == CrossCnt)))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 167 if ((!rst_ni)) -2-: 170 if (en_i)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


Branch Coverage for Module : prim_count ( parameter Width=10,OutSelDnCnt=0,CntStyle=0 )
Branch Coverage for Module self-instances :
SCOREBRANCH
45.41 45.45
tb.dut.u_flash_hw_if.u_word_cnt

Line No.TotalCoveredPercent
Branches 22 10 45.45
TERNARY 159 3 1 33.33
TERNARY 75 4 1 25.00
IF 66 3 2 66.67
IF 167 3 2 66.67
IF 103 4 2 50.00
IF 114 5 2 40.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_count_0/rtl/prim_count.sv' or '../src/lowrisc_prim_count_0/rtl/prim_count.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 159 ((cmp_valid == CmpValid)) ? -2-: 159 ((cmp_valid == CmpInvalid)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T2,T3
0 0 Not Covered


LineNo. Expression -1-: 75 (clr_up_cnt) ? -2-: 75 (set_up_cnt) ? -3-: 75 ((en_i & (up_cnt_q[0] < max_val))) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 66 if ((!rst_ni)) -2-: 68 if ((set_i && (CntStyle == CrossCnt)))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 167 if ((!rst_ni)) -2-: 170 if (en_i)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 103 if ((!rst_ni)) -2-: 105 if (clr_i) -3-: 107 if (((cmp_valid == CmpInvalid) && set_i))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 114 if ((!rst_ni)) -2-: 116 if (clr_i) -3-: 118 if (set_i) -4-: 120 if ((en_i && (gen_cross_cnt_hardening.down_cnt > '0)))

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Not Covered
0 0 1 - Not Covered
0 0 0 1 Not Covered
0 0 0 0 Covered T1,T2,T3


Assert Coverage for Module : prim_count
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 12 12 100.00 2 16.67
Cover properties 0 0 0
Cover sequences 0 0 0
Total 12 12 100.00 2 16.67




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 110 110 0 0
CntStyleMatch_A 110 110 0 0
OutClr_A 3625036 0 0 0
OutSet_A 3625036 0 0 110
OutStep_A 3625036 0 0 0
SimulClrSet_A 3625036 0 0 0
gen_cross_cnt_hardening.CrossCntErrBackward_A 1812518 0 0 0
gen_cross_cnt_hardening.CrossCntErrForward_A 1812518 0 0 0
gen_cross_cnt_hardening.DownCntStepInt_A 1812518 0 0 0
gen_cross_cnt_hardening.UpCntOverFlow_A 1812518 0 0 0
gen_dup_cnt_hardening.DupCntErrBackward_A 1812518 0 0 0
gen_dup_cnt_hardening.DupCntErrForward_A 1812518 0 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 110 110 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T6 2 2 0 0
T7 2 2 0 0
T8 2 2 0 0
T9 2 2 0 0
T10 2 2 0 0

CntStyleMatch_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 110 110 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T6 2 2 0 0
T7 2 2 0 0
T8 2 2 0 0
T9 2 2 0 0
T10 2 2 0 0

OutClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3625036 0 0 0

OutSet_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3625036 0 0 110

OutStep_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3625036 0 0 0

SimulClrSet_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3625036 0 0 0

gen_cross_cnt_hardening.CrossCntErrBackward_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_cross_cnt_hardening.CrossCntErrForward_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_cross_cnt_hardening.DownCntStepInt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_cross_cnt_hardening.UpCntOverFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_dup_cnt_hardening.DupCntErrBackward_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_dup_cnt_hardening.DupCntErrForward_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

Line Coverage for Instance : tb.dut.u_flash_hw_if.u_word_cnt
Line No.TotalCoveredPercent
TOTAL322475.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5600
ALWAYS664375.00
CONT_ASSIGN7511100.00
ALWAYS1036466.67
ALWAYS1148562.50
CONT_ASSIGN12611100.00
CONT_ASSIGN12711100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN15911100.00
ALWAYS1676466.67
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_count_0/rtl/prim_count.sv' or '../src/lowrisc_prim_count_0/rtl/prim_count.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
51 1 1
56 unreachable
66 1 1
67 1 1
68 1 1
69 0 1
MISSING_ELSE
75 1 1
103 1 1
104 1 1
105 1 1
106 0 1
107 1 1
108 0 1
MISSING_ELSE
114 1 1
115 1 1
116 1 1
117 0 1
118 1 1
119 0 1
120 1 1
121 0 1
MISSING_ELSE
126 1 1
127 1 1
128 1 1
142 1 1
144 1 1
159 1 1
167 1 1
168 1 1
169 1 1
170 1 1
171 0 1
172 0 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_flash_hw_if.u_word_cnt
TotalCoveredPercent
Conditions17741.18
Logical17741.18
Non-Logical00
Event00

 LINE       68
 EXPRESSION (set_i && (CntStyle == CrossCnt))
             --1--    -----------2----------
-1--2-StatusTests
0-CoveredT1,T2,T3
1-Not Covered

 LINE       75
 EXPRESSION (clr_up_cnt ? '0 : (set_up_cnt ? set_cnt_i : (((en_i & (up_cnt_q[0] < max_val))) ? ((up_cnt_q[0] + step_i)) : up_cnt_q[0])))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       75
 SUB-EXPRESSION (set_up_cnt ? set_cnt_i : (((en_i & (up_cnt_q[0] < max_val))) ? ((up_cnt_q[0] + step_i)) : up_cnt_q[0]))
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1Unreachable

 LINE       75
 SUB-EXPRESSION (((en_i & (up_cnt_q[0] < max_val))) ? ((up_cnt_q[0] + step_i)) : up_cnt_q[0])
                 -----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       107
 EXPRESSION ((cmp_valid == CmpInvalid) && set_i)
             ------------1------------    --2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       120
 EXPRESSION (en_i && (gen_cross_cnt_hardening.down_cnt > '0))
             --1-    -------------------2-------------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       159
 EXPRESSION ((cmp_valid == CmpValid) ? err : ((cmp_valid == CmpInvalid) ? '0 : 1'b1))
             -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       159
 SUB-EXPRESSION ((cmp_valid == CmpInvalid) ? '0 : 1'b1)
                 ------------1------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_flash_hw_if.u_word_cnt
Line No.TotalCoveredPercent
Branches 22 10 45.45
TERNARY 159 3 1 33.33
TERNARY 75 4 1 25.00
IF 66 3 2 66.67
IF 167 3 2 66.67
IF 103 4 2 50.00
IF 114 5 2 40.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_count_0/rtl/prim_count.sv' or '../src/lowrisc_prim_count_0/rtl/prim_count.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 159 ((cmp_valid == CmpValid)) ? -2-: 159 ((cmp_valid == CmpInvalid)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T2,T3
0 0 Not Covered


LineNo. Expression -1-: 75 (clr_up_cnt) ? -2-: 75 (set_up_cnt) ? -3-: 75 ((en_i & (up_cnt_q[0] < max_val))) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 66 if ((!rst_ni)) -2-: 68 if ((set_i && (CntStyle == CrossCnt)))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 167 if ((!rst_ni)) -2-: 170 if (en_i)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 103 if ((!rst_ni)) -2-: 105 if (clr_i) -3-: 107 if (((cmp_valid == CmpInvalid) && set_i))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 114 if ((!rst_ni)) -2-: 116 if (clr_i) -3-: 118 if (set_i) -4-: 120 if ((en_i && (gen_cross_cnt_hardening.down_cnt > '0)))

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Not Covered
0 0 1 - Not Covered
0 0 0 1 Not Covered
0 0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_flash_hw_if.u_word_cnt
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 10 10 100.00 2 20.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 10 10 100.00 2 20.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 55 55 0 0
CntStyleMatch_A 55 55 0 0
OutClr_A 1812518 0 0 0
OutSet_A 1812518 0 0 55
OutStep_A 1812518 0 0 0
SimulClrSet_A 1812518 0 0 0
gen_cross_cnt_hardening.CrossCntErrBackward_A 1812518 0 0 0
gen_cross_cnt_hardening.CrossCntErrForward_A 1812518 0 0 0
gen_cross_cnt_hardening.DownCntStepInt_A 1812518 0 0 0
gen_cross_cnt_hardening.UpCntOverFlow_A 1812518 0 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

CntStyleMatch_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OutClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

OutSet_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 55

OutStep_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

SimulClrSet_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_cross_cnt_hardening.CrossCntErrBackward_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_cross_cnt_hardening.CrossCntErrForward_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_cross_cnt_hardening.DownCntStepInt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_cross_cnt_hardening.UpCntOverFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

Line Coverage for Instance : tb.dut.u_flash_hw_if.u_page_cnt
Line No.TotalCoveredPercent
TOTAL161487.50
CONT_ASSIGN5111100.00
CONT_ASSIGN5611100.00
ALWAYS6633100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15211100.00
CONT_ASSIGN15911100.00
ALWAYS1676466.67
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_count_0/rtl/prim_count.sv' or '../src/lowrisc_prim_count_0/rtl/prim_count.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
51 1 1
56 1 1
66 1 1
67 1 1
68 1 1
69 unreachable
MISSING_ELSE
75 2 2
151 1 1
152 1 1
159 1 1
167 1 1
168 1 1
169 1 1
170 1 1
171 0 1
172 0 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_flash_hw_if.u_page_cnt
TotalCoveredPercent
Conditions13753.85
Logical13753.85
Non-Logical00
Event00

 LINE       75
 EXPRESSION (clr_up_cnt ? '0 : (set_up_cnt ? set_cnt_i : (((en_i & (up_cnt_q[0] < max_val))) ? ((up_cnt_q[0] + step_i)) : up_cnt_q[0])))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       75
 SUB-EXPRESSION (set_up_cnt ? set_cnt_i : (((en_i & (up_cnt_q[0] < max_val))) ? ((up_cnt_q[0] + step_i)) : up_cnt_q[0]))
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       75
 SUB-EXPRESSION (((en_i & (up_cnt_q[0] < max_val))) ? ((up_cnt_q[0] + step_i)) : up_cnt_q[0])
                 -----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       75
 EXPRESSION (clr_up_cnt ? '0 : (set_up_cnt ? set_cnt_i : (((en_i & (up_cnt_q[1] < max_val))) ? ((up_cnt_q[1] + step_i)) : up_cnt_q[1])))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       75
 SUB-EXPRESSION (set_up_cnt ? set_cnt_i : (((en_i & (up_cnt_q[1] < max_val))) ? ((up_cnt_q[1] + step_i)) : up_cnt_q[1]))
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       75
 SUB-EXPRESSION (((en_i & (up_cnt_q[1] < max_val))) ? ((up_cnt_q[1] + step_i)) : up_cnt_q[1])
                 -----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       159
 EXPRESSION ((cmp_valid == CmpValid) ? err : ((cmp_valid == CmpInvalid) ? '0 : 1'b1))
             -----------1-----------
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       159
 SUB-EXPRESSION ((cmp_valid == CmpInvalid) ? '0 : 1'b1)
                 ------------1------------
-1-StatusTests
0Unreachable
1Unreachable

Branch Coverage for Instance : tb.dut.u_flash_hw_if.u_page_cnt
Line No.TotalCoveredPercent
Branches 17 8 47.06
TERNARY 159 3 1 33.33
TERNARY 75 4 1 25.00
TERNARY 75 4 2 50.00
IF 66 3 2 66.67
IF 167 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_count_0/rtl/prim_count.sv' or '../src/lowrisc_prim_count_0/rtl/prim_count.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 159 ((cmp_valid == CmpValid)) ? -2-: 159 ((cmp_valid == CmpInvalid)) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Not Covered


LineNo. Expression -1-: 75 (clr_up_cnt) ? -2-: 75 (set_up_cnt) ? -3-: 75 ((en_i & (up_cnt_q[0] < max_val))) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 75 (clr_up_cnt) ? -2-: 75 (set_up_cnt) ? -3-: 75 ((en_i & (up_cnt_q[1] < max_val))) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 66 if ((!rst_ni)) -2-: 68 if ((set_i && (CntStyle == CrossCnt)))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 167 if ((!rst_ni)) -2-: 170 if (en_i)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_flash_hw_if.u_page_cnt
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 8 8 100.00 2 25.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 8 8 100.00 2 25.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 55 55 0 0
CntStyleMatch_A 55 55 0 0
OutClr_A 1812518 0 0 0
OutSet_A 1812518 0 0 55
OutStep_A 1812518 0 0 0
SimulClrSet_A 1812518 0 0 0
gen_dup_cnt_hardening.DupCntErrBackward_A 1812518 0 0 0
gen_dup_cnt_hardening.DupCntErrForward_A 1812518 0 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

CntStyleMatch_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OutClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

OutSet_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 55

OutStep_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

SimulClrSet_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_dup_cnt_hardening.DupCntErrBackward_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_dup_cnt_hardening.DupCntErrForward_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%