Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_generic_ram_1p
SCORELINECONDTOGGLEFSMBRANCHASSERT
52.02 50.00 100.00 6.06

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg_ram.gen_generic.u_impl_generic 16.88 14.29 33.33 3.03
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic 32.54 14.29 33.33 50.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem_meta.gen_generic.u_impl_generic 32.54 14.29 33.33 50.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic 32.54 14.29 33.33 50.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem_meta.gen_generic.u_impl_generic 32.54 14.29 33.33 50.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic 32.54 14.29 33.33 50.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem_meta.gen_generic.u_impl_generic 32.54 14.29 33.33 50.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic 32.54 14.29 33.33 50.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem_meta.gen_generic.u_impl_generic 32.54 14.29 33.33 50.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic 32.54 14.29 33.33 50.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem_meta.gen_generic.u_impl_generic 32.54 14.29 33.33 50.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic 32.54 14.29 33.33 50.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem_meta.gen_generic.u_impl_generic 32.54 14.29 33.33 50.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic 95.24 85.71 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem_meta.gen_generic.u_impl_generic 95.24 85.71 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic 95.24 85.71 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem_meta.gen_generic.u_impl_generic 95.24 85.71 100.00 100.00



Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg_ram.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
16.88 14.29 33.33 3.03


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
16.88 14.29 33.33 3.03


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_cfg_ram


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
32.54 14.29 33.33 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
32.54 14.29 33.33 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_info_types[0].u_info_mem


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem_meta.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
32.54 14.29 33.33 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
32.54 14.29 33.33 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_info_types[0].u_info_mem_meta


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
32.54 14.29 33.33 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
32.54 14.29 33.33 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_info_types[1].u_info_mem


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem_meta.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
32.54 14.29 33.33 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
32.54 14.29 33.33 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_info_types[1].u_info_mem_meta


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
32.54 14.29 33.33 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
32.54 14.29 33.33 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_info_types[2].u_info_mem


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem_meta.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
32.54 14.29 33.33 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
32.54 14.29 33.33 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_info_types[2].u_info_mem_meta


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
32.54 14.29 33.33 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
32.54 14.29 33.33 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_info_types[0].u_info_mem


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem_meta.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
32.54 14.29 33.33 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
32.54 14.29 33.33 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_info_types[0].u_info_mem_meta


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
32.54 14.29 33.33 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
32.54 14.29 33.33 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_info_types[1].u_info_mem


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem_meta.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
32.54 14.29 33.33 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
32.54 14.29 33.33 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_info_types[1].u_info_mem_meta


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
32.54 14.29 33.33 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
32.54 14.29 33.33 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_info_types[2].u_info_mem


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem_meta.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
32.54 14.29 33.33 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
32.54 14.29 33.33 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_info_types[2].u_info_mem_meta


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.24 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.24 85.71 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_mem


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem_meta.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.24 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.24 85.71 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_mem_meta


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.24 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.24 85.71 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_mem


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem_meta.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.24 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.24 85.71 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_mem_meta


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_ram_1p ( parameter Width=32,Depth=21,DataBitsPerMask=1,MemInitFile="" )
Line Coverage for Module self-instances :
SCORELINE
16.88 14.29
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg_ram.gen_generic.u_impl_generic

Line No.TotalCoveredPercent
TOTAL7114.29
CONT_ASSIGN42100.00
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
ALWAYS636116.67
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 0 1
52 unreachable
63 1 1
64 0 1
65 0 1
66 0 1
67 0 1
==> MISSING_ELSE
72 0 1
MISSING_ELSE


Line Coverage for Module : prim_generic_ram_1p ( parameter Width=68,Depth=65536,DataBitsPerMask=68,MemInitFile="" + Width=8,Depth=65536,DataBitsPerMask=8,MemInitFile="" + Width=68,Depth=2560,DataBitsPerMask=68,MemInitFile="" + Width=8,Depth=2560,DataBitsPerMask=8,MemInitFile="" )
Line Coverage for Module self-instances :
SCORELINE
95.24 85.71
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic

SCORELINE
95.24 85.71
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem_meta.gen_generic.u_impl_generic

SCORELINE
32.54 14.29
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic

SCORELINE
32.54 14.29
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem_meta.gen_generic.u_impl_generic

SCORELINE
32.54 14.29
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic

SCORELINE
32.54 14.29
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem_meta.gen_generic.u_impl_generic

SCORELINE
32.54 14.29
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic

SCORELINE
32.54 14.29
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem_meta.gen_generic.u_impl_generic

SCORELINE
95.24 85.71
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic

SCORELINE
95.24 85.71
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem_meta.gen_generic.u_impl_generic

SCORELINE
32.54 14.29
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic

SCORELINE
32.54 14.29
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem_meta.gen_generic.u_impl_generic

SCORELINE
32.54 14.29
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic

SCORELINE
32.54 14.29
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem_meta.gen_generic.u_impl_generic

SCORELINE
32.54 14.29
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic

SCORELINE
32.54 14.29
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem_meta.gen_generic.u_impl_generic

Line No.TotalCoveredPercent
TOTAL7685.71
CONT_ASSIGN42100.00
CONT_ASSIGN5200
ALWAYS6366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 0 1
52 unreachable
63 1 1
64 1 1
65 1 1
66 1 1
67 1 1
==> MISSING_ELSE
72 1 1
MISSING_ELSE


Branch Coverage for Module : prim_generic_ram_1p
Line No.TotalCoveredPercent
Branches 3 3 100.00
IF 63 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Covered T1,T2,T3
0 - Covered T1,T2,T3


Assert Coverage for Module : prim_generic_ram_1p
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 33 33 100.00 2 6.06
Cover properties 0 0 0
Cover sequences 0 0 0
Total 33 33 100.00 2 6.06




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataBitsPerMaskCheck_A 935 935 0 0
gen_wmask[0].MaskCheck_A 30812806 3051496 0 0
gen_wmask[10].MaskCheck_A 1812518 0 0 0
gen_wmask[11].MaskCheck_A 1812518 0 0 0
gen_wmask[12].MaskCheck_A 1812518 0 0 0
gen_wmask[13].MaskCheck_A 1812518 0 0 0
gen_wmask[14].MaskCheck_A 1812518 0 0 0
gen_wmask[15].MaskCheck_A 1812518 0 0 0
gen_wmask[16].MaskCheck_A 1812518 0 0 0
gen_wmask[17].MaskCheck_A 1812518 0 0 0
gen_wmask[18].MaskCheck_A 1812518 0 0 0
gen_wmask[19].MaskCheck_A 1812518 0 0 0
gen_wmask[1].MaskCheck_A 1812518 0 0 0
gen_wmask[20].MaskCheck_A 1812518 0 0 0
gen_wmask[21].MaskCheck_A 1812518 0 0 0
gen_wmask[22].MaskCheck_A 1812518 0 0 0
gen_wmask[23].MaskCheck_A 1812518 0 0 0
gen_wmask[24].MaskCheck_A 1812518 0 0 0
gen_wmask[25].MaskCheck_A 1812518 0 0 0
gen_wmask[26].MaskCheck_A 1812518 0 0 0
gen_wmask[27].MaskCheck_A 1812518 0 0 0
gen_wmask[28].MaskCheck_A 1812518 0 0 0
gen_wmask[29].MaskCheck_A 1812518 0 0 0
gen_wmask[2].MaskCheck_A 1812518 0 0 0
gen_wmask[30].MaskCheck_A 1812518 0 0 0
gen_wmask[31].MaskCheck_A 1812518 0 0 0
gen_wmask[3].MaskCheck_A 1812518 0 0 0
gen_wmask[4].MaskCheck_A 1812518 0 0 0
gen_wmask[5].MaskCheck_A 1812518 0 0 0
gen_wmask[6].MaskCheck_A 1812518 0 0 0
gen_wmask[7].MaskCheck_A 1812518 0 0 0
gen_wmask[8].MaskCheck_A 1812518 0 0 0
gen_wmask[9].MaskCheck_A 1812518 0 0 0


DataBitsPerMaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 935 935 0 0
T1 17 17 0 0
T2 17 17 0 0
T3 17 17 0 0
T4 17 17 0 0
T5 17 17 0 0
T6 17 17 0 0
T7 17 17 0 0
T8 17 17 0 0
T9 17 17 0 0
T10 17 17 0 0

gen_wmask[0].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 30812806 3051496 0 0
T1 27604 10100 0 0
T2 31760 6800 0 0
T3 18978 9400 0 0
T4 2440 300 0 0
T5 50424 17700 0 0
T6 1113664 544168 0 0
T7 11182 8400 0 0
T8 30624 11000 0 0
T9 40100 13500 0 0
T10 587084 276792 0 0
T11 23352 7900 0 0
T12 7102 2112 0 0

gen_wmask[10].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[11].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[12].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[13].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[14].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[15].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[16].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[17].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[18].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[19].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[1].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[20].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[21].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[22].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[23].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[24].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[25].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[26].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[27].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[28].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[29].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[2].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[30].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[31].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[3].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[4].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[5].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[6].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[7].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[8].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[9].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg_ram.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL7114.29
CONT_ASSIGN42100.00
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
ALWAYS636116.67
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 0 1
52 unreachable
63 1 1
64 0 1
65 0 1
66 0 1
67 0 1
==> MISSING_ELSE
72 0 1
MISSING_ELSE


Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg_ram.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 3 1 33.33
IF 63 3 1 33.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)

Branches:
-1--2-StatusTests
1 1 Not Covered
1 0 Not Covered
0 - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg_ram.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 33 33 100.00 1 3.03
Cover properties 0 0 0
Cover sequences 0 0 0
Total 33 33 100.00 1 3.03




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataBitsPerMaskCheck_A 55 55 0 0
gen_wmask[0].MaskCheck_A 1812518 0 0 0
gen_wmask[10].MaskCheck_A 1812518 0 0 0
gen_wmask[11].MaskCheck_A 1812518 0 0 0
gen_wmask[12].MaskCheck_A 1812518 0 0 0
gen_wmask[13].MaskCheck_A 1812518 0 0 0
gen_wmask[14].MaskCheck_A 1812518 0 0 0
gen_wmask[15].MaskCheck_A 1812518 0 0 0
gen_wmask[16].MaskCheck_A 1812518 0 0 0
gen_wmask[17].MaskCheck_A 1812518 0 0 0
gen_wmask[18].MaskCheck_A 1812518 0 0 0
gen_wmask[19].MaskCheck_A 1812518 0 0 0
gen_wmask[1].MaskCheck_A 1812518 0 0 0
gen_wmask[20].MaskCheck_A 1812518 0 0 0
gen_wmask[21].MaskCheck_A 1812518 0 0 0
gen_wmask[22].MaskCheck_A 1812518 0 0 0
gen_wmask[23].MaskCheck_A 1812518 0 0 0
gen_wmask[24].MaskCheck_A 1812518 0 0 0
gen_wmask[25].MaskCheck_A 1812518 0 0 0
gen_wmask[26].MaskCheck_A 1812518 0 0 0
gen_wmask[27].MaskCheck_A 1812518 0 0 0
gen_wmask[28].MaskCheck_A 1812518 0 0 0
gen_wmask[29].MaskCheck_A 1812518 0 0 0
gen_wmask[2].MaskCheck_A 1812518 0 0 0
gen_wmask[30].MaskCheck_A 1812518 0 0 0
gen_wmask[31].MaskCheck_A 1812518 0 0 0
gen_wmask[3].MaskCheck_A 1812518 0 0 0
gen_wmask[4].MaskCheck_A 1812518 0 0 0
gen_wmask[5].MaskCheck_A 1812518 0 0 0
gen_wmask[6].MaskCheck_A 1812518 0 0 0
gen_wmask[7].MaskCheck_A 1812518 0 0 0
gen_wmask[8].MaskCheck_A 1812518 0 0 0
gen_wmask[9].MaskCheck_A 1812518 0 0 0


DataBitsPerMaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

gen_wmask[0].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[10].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[11].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[12].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[13].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[14].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[15].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[16].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[17].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[18].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[19].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[1].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[20].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[21].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[22].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[23].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[24].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[25].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[26].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[27].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[28].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[29].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[2].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[30].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[31].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[3].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[4].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[5].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[6].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[7].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[8].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

gen_wmask[9].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL7114.29
CONT_ASSIGN42100.00
CONT_ASSIGN5200
ALWAYS636116.67
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 0 1
52 unreachable
63 1 1
64 0 1
65 0 1
66 0 1
67 0 1
==> MISSING_ELSE
72 0 1
MISSING_ELSE


Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 3 1 33.33
IF 63 3 1 33.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)

Branches:
-1--2-StatusTests
1 1 Not Covered
1 0 Not Covered
0 - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataBitsPerMaskCheck_A 55 55 0 0
gen_wmask[0].MaskCheck_A 1812518 0 0 0


DataBitsPerMaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

gen_wmask[0].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem_meta.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL7114.29
CONT_ASSIGN42100.00
CONT_ASSIGN5200
ALWAYS636116.67
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 0 1
52 unreachable
63 1 1
64 0 1
65 0 1
66 0 1
67 0 1
==> MISSING_ELSE
72 0 1
MISSING_ELSE


Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem_meta.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 3 1 33.33
IF 63 3 1 33.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)

Branches:
-1--2-StatusTests
1 1 Not Covered
1 0 Not Covered
0 - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem_meta.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataBitsPerMaskCheck_A 55 55 0 0
gen_wmask[0].MaskCheck_A 1812518 0 0 0


DataBitsPerMaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

gen_wmask[0].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL7114.29
CONT_ASSIGN42100.00
CONT_ASSIGN5200
ALWAYS636116.67
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 0 1
52 unreachable
63 1 1
64 0 1
65 0 1
66 0 1
67 0 1
==> MISSING_ELSE
72 0 1
MISSING_ELSE


Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 3 1 33.33
IF 63 3 1 33.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)

Branches:
-1--2-StatusTests
1 1 Not Covered
1 0 Not Covered
0 - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataBitsPerMaskCheck_A 55 55 0 0
gen_wmask[0].MaskCheck_A 1812518 0 0 0


DataBitsPerMaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

gen_wmask[0].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem_meta.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL7114.29
CONT_ASSIGN42100.00
CONT_ASSIGN5200
ALWAYS636116.67
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 0 1
52 unreachable
63 1 1
64 0 1
65 0 1
66 0 1
67 0 1
==> MISSING_ELSE
72 0 1
MISSING_ELSE


Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem_meta.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 3 1 33.33
IF 63 3 1 33.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)

Branches:
-1--2-StatusTests
1 1 Not Covered
1 0 Not Covered
0 - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem_meta.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataBitsPerMaskCheck_A 55 55 0 0
gen_wmask[0].MaskCheck_A 1812518 0 0 0


DataBitsPerMaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

gen_wmask[0].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL7114.29
CONT_ASSIGN42100.00
CONT_ASSIGN5200
ALWAYS636116.67
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 0 1
52 unreachable
63 1 1
64 0 1
65 0 1
66 0 1
67 0 1
==> MISSING_ELSE
72 0 1
MISSING_ELSE


Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 3 1 33.33
IF 63 3 1 33.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)

Branches:
-1--2-StatusTests
1 1 Not Covered
1 0 Not Covered
0 - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataBitsPerMaskCheck_A 55 55 0 0
gen_wmask[0].MaskCheck_A 1812518 0 0 0


DataBitsPerMaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

gen_wmask[0].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem_meta.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL7114.29
CONT_ASSIGN42100.00
CONT_ASSIGN5200
ALWAYS636116.67
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 0 1
52 unreachable
63 1 1
64 0 1
65 0 1
66 0 1
67 0 1
==> MISSING_ELSE
72 0 1
MISSING_ELSE


Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem_meta.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 3 1 33.33
IF 63 3 1 33.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)

Branches:
-1--2-StatusTests
1 1 Not Covered
1 0 Not Covered
0 - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem_meta.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataBitsPerMaskCheck_A 55 55 0 0
gen_wmask[0].MaskCheck_A 1812518 0 0 0


DataBitsPerMaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

gen_wmask[0].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL7114.29
CONT_ASSIGN42100.00
CONT_ASSIGN5200
ALWAYS636116.67
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 0 1
52 unreachable
63 1 1
64 0 1
65 0 1
66 0 1
67 0 1
==> MISSING_ELSE
72 0 1
MISSING_ELSE


Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 3 1 33.33
IF 63 3 1 33.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)

Branches:
-1--2-StatusTests
1 1 Not Covered
1 0 Not Covered
0 - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataBitsPerMaskCheck_A 55 55 0 0
gen_wmask[0].MaskCheck_A 1812518 0 0 0


DataBitsPerMaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

gen_wmask[0].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem_meta.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL7114.29
CONT_ASSIGN42100.00
CONT_ASSIGN5200
ALWAYS636116.67
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 0 1
52 unreachable
63 1 1
64 0 1
65 0 1
66 0 1
67 0 1
==> MISSING_ELSE
72 0 1
MISSING_ELSE


Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem_meta.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 3 1 33.33
IF 63 3 1 33.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)

Branches:
-1--2-StatusTests
1 1 Not Covered
1 0 Not Covered
0 - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem_meta.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataBitsPerMaskCheck_A 55 55 0 0
gen_wmask[0].MaskCheck_A 1812518 0 0 0


DataBitsPerMaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

gen_wmask[0].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL7114.29
CONT_ASSIGN42100.00
CONT_ASSIGN5200
ALWAYS636116.67
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 0 1
52 unreachable
63 1 1
64 0 1
65 0 1
66 0 1
67 0 1
==> MISSING_ELSE
72 0 1
MISSING_ELSE


Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 3 1 33.33
IF 63 3 1 33.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)

Branches:
-1--2-StatusTests
1 1 Not Covered
1 0 Not Covered
0 - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataBitsPerMaskCheck_A 55 55 0 0
gen_wmask[0].MaskCheck_A 1812518 0 0 0


DataBitsPerMaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

gen_wmask[0].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem_meta.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL7114.29
CONT_ASSIGN42100.00
CONT_ASSIGN5200
ALWAYS636116.67
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 0 1
52 unreachable
63 1 1
64 0 1
65 0 1
66 0 1
67 0 1
==> MISSING_ELSE
72 0 1
MISSING_ELSE


Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem_meta.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 3 1 33.33
IF 63 3 1 33.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)

Branches:
-1--2-StatusTests
1 1 Not Covered
1 0 Not Covered
0 - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem_meta.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataBitsPerMaskCheck_A 55 55 0 0
gen_wmask[0].MaskCheck_A 1812518 0 0 0


DataBitsPerMaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

gen_wmask[0].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL7114.29
CONT_ASSIGN42100.00
CONT_ASSIGN5200
ALWAYS636116.67
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 0 1
52 unreachable
63 1 1
64 0 1
65 0 1
66 0 1
67 0 1
==> MISSING_ELSE
72 0 1
MISSING_ELSE


Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 3 1 33.33
IF 63 3 1 33.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)

Branches:
-1--2-StatusTests
1 1 Not Covered
1 0 Not Covered
0 - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataBitsPerMaskCheck_A 55 55 0 0
gen_wmask[0].MaskCheck_A 1812518 0 0 0


DataBitsPerMaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

gen_wmask[0].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem_meta.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL7114.29
CONT_ASSIGN42100.00
CONT_ASSIGN5200
ALWAYS636116.67
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 0 1
52 unreachable
63 1 1
64 0 1
65 0 1
66 0 1
67 0 1
==> MISSING_ELSE
72 0 1
MISSING_ELSE


Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem_meta.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 3 1 33.33
IF 63 3 1 33.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)

Branches:
-1--2-StatusTests
1 1 Not Covered
1 0 Not Covered
0 - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem_meta.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataBitsPerMaskCheck_A 55 55 0 0
gen_wmask[0].MaskCheck_A 1812518 0 0 0


DataBitsPerMaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

gen_wmask[0].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL7685.71
CONT_ASSIGN42100.00
CONT_ASSIGN5200
ALWAYS6366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 0 1
52 unreachable
63 1 1
64 1 1
65 1 1
66 1 1
67 1 1
==> MISSING_ELSE
72 1 1
MISSING_ELSE


Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 3 3 100.00
IF 63 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Covered T1,T2,T3
0 - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataBitsPerMaskCheck_A 55 55 0 0
gen_wmask[0].MaskCheck_A 1812518 526328 0 0


DataBitsPerMaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

gen_wmask[0].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 526328 0 0
T1 6901 2050 0 0
T2 7940 600 0 0
T3 9489 4700 0 0
T5 12606 6950 0 0
T6 278416 2850 0 0
T7 5591 4200 0 0
T8 7656 3850 0 0
T9 10025 800 0 0
T10 146771 2656 0 0
T11 5838 2400 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem_meta.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL7685.71
CONT_ASSIGN42100.00
CONT_ASSIGN5200
ALWAYS6366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 0 1
52 unreachable
63 1 1
64 1 1
65 1 1
66 1 1
67 1 1
==> MISSING_ELSE
72 1 1
MISSING_ELSE


Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem_meta.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 3 3 100.00
IF 63 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Covered T1,T2,T3
0 - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem_meta.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataBitsPerMaskCheck_A 55 55 0 0
gen_wmask[0].MaskCheck_A 1812518 526328 0 0


DataBitsPerMaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

gen_wmask[0].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 526328 0 0
T1 6901 2050 0 0
T2 7940 600 0 0
T3 9489 4700 0 0
T5 12606 6950 0 0
T6 278416 2850 0 0
T7 5591 4200 0 0
T8 7656 3850 0 0
T9 10025 800 0 0
T10 146771 2656 0 0
T11 5838 2400 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL7685.71
CONT_ASSIGN42100.00
CONT_ASSIGN5200
ALWAYS6366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 0 1
52 unreachable
63 1 1
64 1 1
65 1 1
66 1 1
67 1 1
==> MISSING_ELSE
72 1 1
MISSING_ELSE


Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 3 3 100.00
IF 63 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T4
1 0 Covered T1,T2,T4
0 - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataBitsPerMaskCheck_A 55 55 0 0
gen_wmask[0].MaskCheck_A 1812518 999420 0 0


DataBitsPerMaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

gen_wmask[0].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 999420 0 0
T1 6901 3000 0 0
T2 7940 2800 0 0
T4 1220 150 0 0
T5 12606 1900 0 0
T6 278416 269234 0 0
T8 7656 1650 0 0
T9 10025 5950 0 0
T10 146771 135740 0 0
T11 5838 1550 0 0
T12 3551 1056 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem_meta.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL7685.71
CONT_ASSIGN42100.00
CONT_ASSIGN5200
ALWAYS6366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 0 1
52 unreachable
63 1 1
64 1 1
65 1 1
66 1 1
67 1 1
==> MISSING_ELSE
72 1 1
MISSING_ELSE


Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem_meta.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 3 3 100.00
IF 63 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T4
1 0 Covered T1,T2,T4
0 - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem_meta.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataBitsPerMaskCheck_A 55 55 0 0
gen_wmask[0].MaskCheck_A 1812518 999420 0 0


DataBitsPerMaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

gen_wmask[0].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 999420 0 0
T1 6901 3000 0 0
T2 7940 2800 0 0
T4 1220 150 0 0
T5 12606 1900 0 0
T6 278416 269234 0 0
T8 7656 1650 0 0
T9 10025 5950 0 0
T10 146771 135740 0 0
T11 5838 1550 0 0
T12 3551 1056 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%