Unified Coverage Report :: Module Instance :: tb.dut.u_to_rd_fifo.u_rspfifo

Module Instance : tb.dut.u_to_rd_fifo.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.38	94.44	81.82			77.27	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.38	94.44	81.82			77.27	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.50	100.00	75.00			95.00	100.00	u_to_rd_fifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_rd_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.00	94.74	90.91			86.36	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.00	94.74	90.91			86.36	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.52	91.74	69.23	13.28		75.00	83.33	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_tl_adapter_eflash.u_sram_byte.u_sync_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.16	80.65	50.00			50.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.16	80.65	50.00			50.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
58.40	88.37	40.00		0.00	63.64	100.00	u_sram_byte

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_tl_adapter_eflash.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
59.44	77.78	50.00			50.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
59.44	77.78	50.00			50.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
68.44	93.22	22.22			75.00	83.33	u_tl_adapter_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_tl_adapter_eflash.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
59.44	77.78	50.00			50.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
59.44	77.78	50.00			50.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
68.44	93.22	22.22			75.00	83.33	u_tl_adapter_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_tl_adapter_eflash.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
59.00	80.56	45.45			50.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
59.00	80.56	45.45			50.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
68.44	93.22	22.22			75.00	83.33	u_tl_adapter_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_eflash.u_bank_sequence_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
59.44	77.78	50.00			50.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
59.44	77.78	50.00			50.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
65.48	96.43	50.00			50.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_sram_byte.u_sync_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.16	80.65	50.00			50.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.16	80.65	50.00			50.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
55.72	79.07	45.00		0.00	54.55	100.00	u_sram_byte

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_to_rd_fifo.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		36	34	94.44
ALWAYS	65	4	4	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
ALWAYS	98	7	6	85.71
ALWAYS	112	7	6	85.71
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
ALWAYS	137	2	2	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	162	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
66	1	1
67	1	1
68	1	1
			MISSING_ELSE
79	1	1
80	1	1
81	1	1
82	1	1
83	1	1
87	1	1
88	1	1
93	1	1
94	1	1
95	1	1
98	1	1
99	1	1
100	1	1
101		unreachable
102	1	1
103	1	1
104	1	1
106	0	1
			MISSING_ELSE
112	1	1
113	1	1
114	1	1
115		unreachable
116	1	1
117	1	1
118	1	1
120	0	1
			MISSING_ELSE
125	1	1
126	1	1
134	1	1
137	1	1
138	1	1
			MISSING_ELSE
155	1	1
156	1	1
162	1	1

---

Cond Coverage for Instance : tb.dut.u_to_rd_fifo.u_rspfifo

	Total	Covered	Percent
Conditions	11	9	81.82
Logical	11	9	81.82
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T32,T33

 LINE       83
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       152
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       152
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_to_rd_fifo.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		22	17	77.27
TERNARY	83	3	2	66.67
TERNARY	152	2	2	100.00
TERNARY	160	2	2	100.00
IF	65	3	3	100.00
IF	98	5	3	60.00
IF	112	5	3	60.00
IF	137	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	83	(gen_normal_fifo.full) ? 
-2-:	83	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T12,T32,T33
0	1	Covered	T1,T2,T3
0	0	Not Covered

	LineNo.	Expression
-1-:	152	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	160	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	65	if ((!rst_ni))
-2-:	67	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	98	if ((!rst_ni))
-2-:	100	if (clr_i)
-3-:	102	if (gen_normal_fifo.fifo_incr_wptr)
-4-:	103	if ((gen_normal_fifo.fifo_wptr[0] == 1'((Depth - 1))))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	1	Covered	T1,T2,T3
0	0	1	0	Not Covered
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	112	if ((!rst_ni))
-2-:	114	if (clr_i)
-3-:	116	if (gen_normal_fifo.fifo_incr_rptr)
-4-:	117	if ((gen_normal_fifo.fifo_rptr[0] == 1'((Depth - 1))))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	1	Covered	T1,T2,T3
0	0	1	0	Not Covered
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	137	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_to_rd_fifo.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1812518	18903	0	0
DepthKnown_A	1812518	1808370	0	0
RvalidKnown_A	1812518	1808370	0	0
WreadyKnown_A	1812518	1808370	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	1812518	18903	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1812518	18903	0	0
T1	6901	154	0	0
T2	7940	83	0	0
T3	9489	119	0	0
T4	1220	6	0	0
T5	12606	261	0	0
T6	278416	134	0	0
T7	5591	126	0	0
T8	7656	162	0	0
T9	10025	166	0	0
T10	146771	215	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1812518	1808370	0	0
T1	6901	6805	0	0
T2	7940	7877	0	0
T3	9489	9419	0	0
T4	1220	1141	0	0
T5	12606	12533	0	0
T6	278416	278331	0	0
T7	5591	5535	0	0
T8	7656	7588	0	0
T9	10025	9967	0	0
T10	146771	146701	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1812518	1808370	0	0
T1	6901	6805	0	0
T2	7940	7877	0	0
T3	9489	9419	0	0
T4	1220	1141	0	0
T5	12606	12533	0	0
T6	278416	278331	0	0
T7	5591	5535	0	0
T8	7656	7588	0	0
T9	10025	9967	0	0
T10	146771	146701	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1812518	1808370	0	0
T1	6901	6805	0	0
T2	7940	7877	0	0
T3	9489	9419	0	0
T4	1220	1141	0	0
T5	12606	12533	0	0
T6	278416	278331	0	0
T7	5591	5535	0	0
T8	7656	7588	0	0
T9	10025	9967	0	0
T10	146771	146701	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	1812518	18903	0	0
T1	6901	154	0	0
T2	7940	83	0	0
T3	9489	119	0	0
T4	1220	6	0	0
T5	12606	261	0	0
T6	278416	134	0	0
T7	5591	126	0	0
T8	7656	162	0	0
T9	10025	166	0	0
T10	146771	215	0	0

Line Coverage for Instance : tb.dut.u_rd_fifo

	Line No.	Total	Covered	Percent
TOTAL		38	36	94.74
ALWAYS	65	4	4	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
ALWAYS	98	8	7	87.50
ALWAYS	112	8	7	87.50
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
ALWAYS	137	2	2	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	162	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
66	1	1
67	1	1
68	1	1
			MISSING_ELSE
79	1	1
80	1	1
81	1	1
82	1	1
83	1	1
87	1	1
88	1	1
93	1	1
94	1	1
95	1	1
98	1	1
99	1	1
100	1	1
101	0	1
102	1	1
103	1	1
104	1	1
106	1	1
			MISSING_ELSE
112	1	1
113	1	1
114	1	1
115	0	1
116	1	1
117	1	1
118	1	1
120	1	1
			MISSING_ELSE
125	1	1
126	1	1
134	1	1
137	1	1
138	1	1
			MISSING_ELSE
155	1	1
156	1	1
162	1	1

---

Cond Coverage for Instance : tb.dut.u_rd_fifo

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (5'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((5'(gen_normal_fifo.wptr_value) - 5'(gen_normal_fifo.rptr_value))) : (((5'(Depth) - 5'(gen_normal_fifo.rptr_value)) + 5'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       83
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((5'(gen_normal_fifo.wptr_value) - 5'(gen_normal_fifo.rptr_value))) : (((5'(Depth) - 5'(gen_normal_fifo.rptr_value)) + 5'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       152
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       152
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_rd_fifo

	Line No.	Total	Covered	Percent
Branches		22	19	86.36
TERNARY	83	3	2	66.67
TERNARY	152	2	2	100.00
TERNARY	160	2	2	100.00
IF	65	3	3	100.00
IF	98	5	4	80.00
IF	112	5	4	80.00
IF	145	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	83	(gen_normal_fifo.full) ? 
-2-:	83	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	152	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	160	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	65	if ((!rst_ni))
-2-:	67	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	98	if ((!rst_ni))
-2-:	100	if (clr_i)
-3-:	102	if (gen_normal_fifo.fifo_incr_wptr)
-4-:	103	if ((gen_normal_fifo.fifo_wptr[(gen_normal_fifo.PTR_WIDTH - 2):0] == 4'((Depth - 1))))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	1	Covered	T1,T2,T3
0	0	1	0	Covered	T1,T2,T3
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	112	if ((!rst_ni))
-2-:	114	if (clr_i)
-3-:	116	if (gen_normal_fifo.fifo_incr_rptr)
-4-:	117	if ((gen_normal_fifo.fifo_rptr[(gen_normal_fifo.PTR_WIDTH - 2):0] == 4'((Depth - 1))))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	1	Covered	T1,T2,T3
0	0	1	0	Covered	T1,T2,T3
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	145	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_rd_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1812518	56859	0	0
DepthKnown_A	1812518	1808370	0	0
RvalidKnown_A	1812518	1808370	0	0
WreadyKnown_A	1812518	1808370	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	1812518	56859	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1812518	56859	0	0
T1	6901	308	0	0
T2	7940	550	0	0
T3	9489	776	0	0
T4	1220	44	0	0
T5	12606	551	0	0
T6	278416	953	0	0
T7	5591	252	0	0
T8	7656	324	0	0
T9	10025	332	0	0
T10	146771	1488	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1812518	1808370	0	0
T1	6901	6805	0	0
T2	7940	7877	0	0
T3	9489	9419	0	0
T4	1220	1141	0	0
T5	12606	12533	0	0
T6	278416	278331	0	0
T7	5591	5535	0	0
T8	7656	7588	0	0
T9	10025	9967	0	0
T10	146771	146701	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1812518	1808370	0	0
T1	6901	6805	0	0
T2	7940	7877	0	0
T3	9489	9419	0	0
T4	1220	1141	0	0
T5	12606	12533	0	0
T6	278416	278331	0	0
T7	5591	5535	0	0
T8	7656	7588	0	0
T9	10025	9967	0	0
T10	146771	146701	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1812518	1808370	0	0
T1	6901	6805	0	0
T2	7940	7877	0	0
T3	9489	9419	0	0
T4	1220	1141	0	0
T5	12606	12533	0	0
T6	278416	278331	0	0
T7	5591	5535	0	0
T8	7656	7588	0	0
T9	10025	9967	0	0
T10	146771	146701	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	1812518	56859	0	0
T1	6901	308	0	0
T2	7940	550	0	0
T3	9489	776	0	0
T4	1220	44	0	0
T5	12606	551	0	0
T6	278416	953	0	0
T7	5591	252	0	0
T8	7656	324	0	0
T9	10025	332	0	0
T10	146771	1488	0	0

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sram_byte.u_sync_fifo

	Line No.	Total	Covered	Percent
TOTAL		31	25	80.65
ALWAYS	65	4	4	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	87	0	0
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
ALWAYS	98	4	4	100.00
ALWAYS	112	7	4	57.14
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	134	1	0	0.00
ALWAYS	137	1	1	100.00
CONT_ASSIGN	155	1	0	0.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	162	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
66	1	1
67	1	1
68	1	1
			MISSING_ELSE
79	1	1
80	1	1
81	1	1
82	1	1
83	1	1
87		unreachable
88	1	1
93	1	1
94	1	1
95	1	1
98	1	1
99	1	1
100	1	1
101		unreachable
102	1	1
103		unreachable
104		unreachable
106		unreachable
			MISSING_ELSE
112	1	1
113	1	1
114	1	1
115		unreachable
116	1	1
117	0	1
118	0	1
120	0	1
			MISSING_ELSE
125	1	1
126	1	1
134	0	1
137	1	1
138		unreachable
			MISSING_ELSE
155	0	1
156	1	1
162	0	1

---

Cond Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sram_byte.u_sync_fifo

	Total	Covered	Percent
Conditions	4	2	50.00
Logical	4	2	50.00
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       83
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sram_byte.u_sync_fifo

	Line No.	Total	Covered	Percent
Branches		18	9	50.00
TERNARY	83	3	1	33.33
IF	65	3	3	100.00
IF	98	5	2	40.00
IF	112	5	2	40.00
IF	137	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	83	(gen_normal_fifo.full) ? 
-2-:	83	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T3
0	0	Not Covered

	LineNo.	Expression
-1-:	65	if ((!rst_ni))
-2-:	67	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	98	if ((!rst_ni))
-2-:	100	if (clr_i)
-3-:	102	if (gen_normal_fifo.fifo_incr_wptr)
-4-:	103	if ((gen_normal_fifo.fifo_wptr[0] == 1'((Depth - 1))))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	1	Not Covered
0	0	1	0	Not Covered
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	112	if ((!rst_ni))
-2-:	114	if (clr_i)
-3-:	116	if (gen_normal_fifo.fifo_incr_rptr)
-4-:	117	if ((gen_normal_fifo.fifo_rptr[0] == 1'((Depth - 1))))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	1	Not Covered
0	0	1	0	Not Covered
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	137	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sram_byte.u_sync_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1812518	0	0	0
DepthKnown_A	1812518	1808370	0	0
RvalidKnown_A	1812518	1808370	0	0
WreadyKnown_A	1812518	1808370	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	1812518	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1812518	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1812518	1808370	0	0
T1	6901	6805	0	0
T2	7940	7877	0	0
T3	9489	9419	0	0
T4	1220	1141	0	0
T5	12606	12533	0	0
T6	278416	278331	0	0
T7	5591	5535	0	0
T8	7656	7588	0	0
T9	10025	9967	0	0
T10	146771	146701	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1812518	1808370	0	0
T1	6901	6805	0	0
T2	7940	7877	0	0
T3	9489	9419	0	0
T4	1220	1141	0	0
T5	12606	12533	0	0
T6	278416	278331	0	0
T7	5591	5535	0	0
T8	7656	7588	0	0
T9	10025	9967	0	0
T10	146771	146701	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1812518	1808370	0	0
T1	6901	6805	0	0
T2	7940	7877	0	0
T3	9489	9419	0	0
T4	1220	1141	0	0
T5	12606	12533	0	0
T6	278416	278331	0	0
T7	5591	5535	0	0
T8	7656	7588	0	0
T9	10025	9967	0	0
T10	146771	146701	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	1812518	0	0	0

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		36	28	77.78
ALWAYS	65	4	4	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
ALWAYS	98	7	4	57.14
ALWAYS	112	7	4	57.14
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
ALWAYS	137	2	1	50.00
CONT_ASSIGN	155	1	0	0.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	162	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
66	1	1
67	1	1
68	1	1
			MISSING_ELSE
79	1	1
80	1	1
81	1	1
82	1	1
83	1	1
87	1	1
88	1	1
93	1	1
94	1	1
95	1	1
98	1	1
99	1	1
100	1	1
101		unreachable
102	1	1
103	0	1
104	0	1
106	0	1
			MISSING_ELSE
112	1	1
113	1	1
114	1	1
115		unreachable
116	1	1
117	0	1
118	0	1
120	0	1
			MISSING_ELSE
125	1	1
126	1	1
134	1	1
137	1	1
138	0	1
			MISSING_ELSE
155	0	1
156	1	1
162	1	1

---

Cond Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_reqfifo

	Total	Covered	Percent
Conditions	6	3	50.00
Logical	6	3	50.00
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       83
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		20	10	50.00
TERNARY	83	3	1	33.33
TERNARY	160	2	1	50.00
IF	65	3	3	100.00
IF	98	5	2	40.00
IF	112	5	2	40.00
IF	137	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	83	(gen_normal_fifo.full) ? 
-2-:	83	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T3
0	0	Not Covered

	LineNo.	Expression
-1-:	160	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	65	if ((!rst_ni))
-2-:	67	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	98	if ((!rst_ni))
-2-:	100	if (clr_i)
-3-:	102	if (gen_normal_fifo.fifo_incr_wptr)
-4-:	103	if ((gen_normal_fifo.fifo_wptr[0] == 1'((Depth - 1))))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	1	Not Covered
0	0	1	0	Not Covered
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	112	if ((!rst_ni))
-2-:	114	if (clr_i)
-3-:	116	if (gen_normal_fifo.fifo_incr_rptr)
-4-:	117	if ((gen_normal_fifo.fifo_rptr[0] == 1'((Depth - 1))))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	1	Not Covered
0	0	1	0	Not Covered
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	137	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1812518	0	0	0
DepthKnown_A	1812518	1808370	0	0
RvalidKnown_A	1812518	1808370	0	0
WreadyKnown_A	1812518	1808370	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	1812518	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1812518	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1812518	1808370	0	0
T1	6901	6805	0	0
T2	7940	7877	0	0
T3	9489	9419	0	0
T4	1220	1141	0	0
T5	12606	12533	0	0
T6	278416	278331	0	0
T7	5591	5535	0	0
T8	7656	7588	0	0
T9	10025	9967	0	0
T10	146771	146701	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1812518	1808370	0	0
T1	6901	6805	0	0
T2	7940	7877	0	0
T3	9489	9419	0	0
T4	1220	1141	0	0
T5	12606	12533	0	0
T6	278416	278331	0	0
T7	5591	5535	0	0
T8	7656	7588	0	0
T9	10025	9967	0	0
T10	146771	146701	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1812518	1808370	0	0
T1	6901	6805	0	0
T2	7940	7877	0	0
T3	9489	9419	0	0
T4	1220	1141	0	0
T5	12606	12533	0	0
T6	278416	278331	0	0
T7	5591	5535	0	0
T8	7656	7588	0	0
T9	10025	9967	0	0
T10	146771	146701	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	1812518	0	0	0

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		36	28	77.78
ALWAYS	65	4	4	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
ALWAYS	98	7	4	57.14
ALWAYS	112	7	4	57.14
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
ALWAYS	137	2	1	50.00
CONT_ASSIGN	155	1	0	0.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	162	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
66	1	1
67	1	1
68	1	1
			MISSING_ELSE
79	1	1
80	1	1
81	1	1
82	1	1
83	1	1
87	1	1
88	1	1
93	1	1
94	1	1
95	1	1
98	1	1
99	1	1
100	1	1
101		unreachable
102	1	1
103	0	1
104	0	1
106	0	1
			MISSING_ELSE
112	1	1
113	1	1
114	1	1
115		unreachable
116	1	1
117	0	1
118	0	1
120	0	1
			MISSING_ELSE
125	1	1
126	1	1
134	1	1
137	1	1
138	0	1
			MISSING_ELSE
155	0	1
156	1	1
162	1	1

---

Cond Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sramreqfifo

	Total	Covered	Percent
Conditions	6	3	50.00
Logical	6	3	50.00
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       83
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		20	10	50.00
TERNARY	83	3	1	33.33
TERNARY	160	2	1	50.00
IF	65	3	3	100.00
IF	98	5	2	40.00
IF	112	5	2	40.00
IF	137	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	83	(gen_normal_fifo.full) ? 
-2-:	83	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T3
0	0	Not Covered

	LineNo.	Expression
-1-:	160	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	65	if ((!rst_ni))
-2-:	67	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	98	if ((!rst_ni))
-2-:	100	if (clr_i)
-3-:	102	if (gen_normal_fifo.fifo_incr_wptr)
-4-:	103	if ((gen_normal_fifo.fifo_wptr[0] == 1'((Depth - 1))))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	1	Not Covered
0	0	1	0	Not Covered
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	112	if ((!rst_ni))
-2-:	114	if (clr_i)
-3-:	116	if (gen_normal_fifo.fifo_incr_rptr)
-4-:	117	if ((gen_normal_fifo.fifo_rptr[0] == 1'((Depth - 1))))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	1	Not Covered
0	0	1	0	Not Covered
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	137	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1812518	0	0	0
DepthKnown_A	1812518	1808370	0	0
RvalidKnown_A	1812518	1808370	0	0
WreadyKnown_A	1812518	1808370	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	1812518	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1812518	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1812518	1808370	0	0
T1	6901	6805	0	0
T2	7940	7877	0	0
T3	9489	9419	0	0
T4	1220	1141	0	0
T5	12606	12533	0	0
T6	278416	278331	0	0
T7	5591	5535	0	0
T8	7656	7588	0	0
T9	10025	9967	0	0
T10	146771	146701	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1812518	1808370	0	0
T1	6901	6805	0	0
T2	7940	7877	0	0
T3	9489	9419	0	0
T4	1220	1141	0	0
T5	12606	12533	0	0
T6	278416	278331	0	0
T7	5591	5535	0	0
T8	7656	7588	0	0
T9	10025	9967	0	0
T10	146771	146701	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1812518	1808370	0	0
T1	6901	6805	0	0
T2	7940	7877	0	0
T3	9489	9419	0	0
T4	1220	1141	0	0
T5	12606	12533	0	0
T6	278416	278331	0	0
T7	5591	5535	0	0
T8	7656	7588	0	0
T9	10025	9967	0	0
T10	146771	146701	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	1812518	0	0	0

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		36	29	80.56
ALWAYS	65	4	4	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
ALWAYS	98	7	4	57.14
ALWAYS	112	7	4	57.14
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
ALWAYS	137	2	1	50.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	162	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
66	1	1
67	1	1
68	1	1
			MISSING_ELSE
79	1	1
80	1	1
81	1	1
82	1	1
83	1	1
87	1	1
88	1	1
93	1	1
94	1	1
95	1	1
98	1	1
99	1	1
100	1	1
101		unreachable
102	1	1
103	0	1
104	0	1
106	0	1
			MISSING_ELSE
112	1	1
113	1	1
114	1	1
115		unreachable
116	1	1
117	0	1
118	0	1
120	0	1
			MISSING_ELSE
125	1	1
126	1	1
134	1	1
137	1	1
138	0	1
			MISSING_ELSE
155	1	1
156	1	1
162	1	1

---

Cond Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_rspfifo

	Total	Covered	Percent
Conditions	11	5	45.45
Logical	11	5	45.45
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       83
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       152
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       152
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       160
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		22	11	50.00
TERNARY	83	3	1	33.33
TERNARY	152	2	1	50.00
TERNARY	160	2	1	50.00
IF	65	3	3	100.00
IF	98	5	2	40.00
IF	112	5	2	40.00
IF	137	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	83	(gen_normal_fifo.full) ? 
-2-:	83	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T3
0	0	Not Covered

	LineNo.	Expression
-1-:	152	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	160	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	65	if ((!rst_ni))
-2-:	67	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	98	if ((!rst_ni))
-2-:	100	if (clr_i)
-3-:	102	if (gen_normal_fifo.fifo_incr_wptr)
-4-:	103	if ((gen_normal_fifo.fifo_wptr[0] == 1'((Depth - 1))))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	1	Not Covered
0	0	1	0	Not Covered
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	112	if ((!rst_ni))
-2-:	114	if (clr_i)
-3-:	116	if (gen_normal_fifo.fifo_incr_rptr)
-4-:	117	if ((gen_normal_fifo.fifo_rptr[0] == 1'((Depth - 1))))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	1	Not Covered
0	0	1	0	Not Covered
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	137	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1812518	0	0	0
DepthKnown_A	1812518	1808370	0	0
RvalidKnown_A	1812518	1808370	0	0
WreadyKnown_A	1812518	1808370	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	1812518	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1812518	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1812518	1808370	0	0
T1	6901	6805	0	0
T2	7940	7877	0	0
T3	9489	9419	0	0
T4	1220	1141	0	0
T5	12606	12533	0	0
T6	278416	278331	0	0
T7	5591	5535	0	0
T8	7656	7588	0	0
T9	10025	9967	0	0
T10	146771	146701	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1812518	1808370	0	0
T1	6901	6805	0	0
T2	7940	7877	0	0
T3	9489	9419	0	0
T4	1220	1141	0	0
T5	12606	12533	0	0
T6	278416	278331	0	0
T7	5591	5535	0	0
T8	7656	7588	0	0
T9	10025	9967	0	0
T10	146771	146701	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1812518	1808370	0	0
T1	6901	6805	0	0
T2	7940	7877	0	0
T3	9489	9419	0	0
T4	1220	1141	0	0
T5	12606	12533	0	0
T6	278416	278331	0	0
T7	5591	5535	0	0
T8	7656	7588	0	0
T9	10025	9967	0	0
T10	146771	146701	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	1812518	0	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_bank_sequence_fifo

	Line No.	Total	Covered	Percent
TOTAL		36	28	77.78
ALWAYS	65	4	4	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
ALWAYS	98	7	4	57.14
ALWAYS	112	7	4	57.14
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
ALWAYS	137	2	1	50.00
CONT_ASSIGN	155	1	0	0.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	162	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
66	1	1
67	1	1
68	1	1
			MISSING_ELSE
79	1	1
80	1	1
81	1	1
82	1	1
83	1	1
87	1	1
88	1	1
93	1	1
94	1	1
95	1	1
98	1	1
99	1	1
100	1	1
101		unreachable
102	1	1
103	0	1
104	0	1
106	0	1
			MISSING_ELSE
112	1	1
113	1	1
114	1	1
115		unreachable
116	1	1
117	0	1
118	0	1
120	0	1
			MISSING_ELSE
125	1	1
126	1	1
134	1	1
137	1	1
138	0	1
			MISSING_ELSE
155	0	1
156	1	1
162	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_bank_sequence_fifo

	Total	Covered	Percent
Conditions	6	3	50.00
Logical	6	3	50.00
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       83
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.u_bank_sequence_fifo

	Line No.	Total	Covered	Percent
Branches		20	10	50.00
TERNARY	83	3	1	33.33
TERNARY	160	2	1	50.00
IF	65	3	3	100.00
IF	98	5	2	40.00
IF	112	5	2	40.00
IF	137	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	83	(gen_normal_fifo.full) ? 
-2-:	83	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T3
0	0	Not Covered

	LineNo.	Expression
-1-:	160	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	65	if ((!rst_ni))
-2-:	67	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	98	if ((!rst_ni))
-2-:	100	if (clr_i)
-3-:	102	if (gen_normal_fifo.fifo_incr_wptr)
-4-:	103	if ((gen_normal_fifo.fifo_wptr[0] == 1'((Depth - 1))))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	1	Not Covered
0	0	1	0	Not Covered
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	112	if ((!rst_ni))
-2-:	114	if (clr_i)
-3-:	116	if (gen_normal_fifo.fifo_incr_rptr)
-4-:	117	if ((gen_normal_fifo.fifo_rptr[0] == 1'((Depth - 1))))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	1	Not Covered
0	0	1	0	Not Covered
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	137	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_bank_sequence_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1812518	0	0	0
DepthKnown_A	1812518	1808370	0	0
RvalidKnown_A	1812518	1808370	0	0
WreadyKnown_A	1812518	1808370	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	1812518	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1812518	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1812518	1808370	0	0
T1	6901	6805	0	0
T2	7940	7877	0	0
T3	9489	9419	0	0
T4	1220	1141	0	0
T5	12606	12533	0	0
T6	278416	278331	0	0
T7	5591	5535	0	0
T8	7656	7588	0	0
T9	10025	9967	0	0
T10	146771	146701	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1812518	1808370	0	0
T1	6901	6805	0	0
T2	7940	7877	0	0
T3	9489	9419	0	0
T4	1220	1141	0	0
T5	12606	12533	0	0
T6	278416	278331	0	0
T7	5591	5535	0	0
T8	7656	7588	0	0
T9	10025	9967	0	0
T10	146771	146701	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1812518	1808370	0	0
T1	6901	6805	0	0
T2	7940	7877	0	0
T3	9489	9419	0	0
T4	1220	1141	0	0
T5	12606	12533	0	0
T6	278416	278331	0	0
T7	5591	5535	0	0
T8	7656	7588	0	0
T9	10025	9967	0	0
T10	146771	146701	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	1812518	0	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_sram_byte.u_sync_fifo

	Line No.	Total	Covered	Percent
TOTAL		31	25	80.65
ALWAYS	65	4	4	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	87	0	0
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
ALWAYS	98	4	4	100.00
ALWAYS	112	7	4	57.14
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	134	1	0	0.00
ALWAYS	137	1	1	100.00
CONT_ASSIGN	155	1	0	0.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	162	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
66	1	1
67	1	1
68	1	1
			MISSING_ELSE
79	1	1
80	1	1
81	1	1
82	1	1
83	1	1
87		unreachable
88	1	1
93	1	1
94	1	1
95	1	1
98	1	1
99	1	1
100	1	1
101		unreachable
102	1	1
103		unreachable
104		unreachable
106		unreachable
			MISSING_ELSE
112	1	1
113	1	1
114	1	1
115		unreachable
116	1	1
117	0	1
118	0	1
120	0	1
			MISSING_ELSE
125	1	1
126	1	1
134	0	1
137	1	1
138		unreachable
			MISSING_ELSE
155	0	1
156	1	1
162	0	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_sram_byte.u_sync_fifo

	Total	Covered	Percent
Conditions	4	2	50.00
Logical	4	2	50.00
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       83
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_sram_byte.u_sync_fifo

	Line No.	Total	Covered	Percent
Branches		18	9	50.00
TERNARY	83	3	1	33.33
IF	65	3	3	100.00
IF	98	5	2	40.00
IF	112	5	2	40.00
IF	137	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	83	(gen_normal_fifo.full) ? 
-2-:	83	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T3
0	0	Not Covered

	LineNo.	Expression
-1-:	65	if ((!rst_ni))
-2-:	67	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	98	if ((!rst_ni))
-2-:	100	if (clr_i)
-3-:	102	if (gen_normal_fifo.fifo_incr_wptr)
-4-:	103	if ((gen_normal_fifo.fifo_wptr[0] == 1'((Depth - 1))))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	1	Not Covered
0	0	1	0	Not Covered
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	112	if ((!rst_ni))
-2-:	114	if (clr_i)
-3-:	116	if (gen_normal_fifo.fifo_incr_rptr)
-4-:	117	if ((gen_normal_fifo.fifo_rptr[0] == 1'((Depth - 1))))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	1	Not Covered
0	0	1	0	Not Covered
0	0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	137	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_sram_byte.u_sync_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1812518	0	0	0
DepthKnown_A	1812518	1808370	0	0
RvalidKnown_A	1812518	1808370	0	0
WreadyKnown_A	1812518	1808370	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	1812518	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1812518	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1812518	1808370	0	0
T1	6901	6805	0	0
T2	7940	7877	0	0
T3	9489	9419	0	0
T4	1220	1141	0	0
T5	12606	12533	0	0
T6	278416	278331	0	0
T7	5591	5535	0	0
T8	7656	7588	0	0
T9	10025	9967	0	0
T10	146771	146701	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1812518	1808370	0	0
T1	6901	6805	0	0
T2	7940	7877	0	0
T3	9489	9419	0	0
T4	1220	1141	0	0
T5	12606	12533	0	0
T6	278416	278331	0	0
T7	5591	5535	0	0
T8	7656	7588	0	0
T9	10025	9967	0	0
T10	146771	146701	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1812518	1808370	0	0
T1	6901	6805	0	0
T2	7940	7877	0	0
T3	9489	9419	0	0
T4	1220	1141	0	0
T5	12606	12533	0	0
T6	278416	278331	0	0
T7	5591	5535	0	0
T8	7656	7588	0	0
T9	10025	9967	0	0
T10	146771	146701	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	1812518	0	0	0