Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
62.46 63.16 33.33 70.00 83.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
47.61 74.25 39.29 0.00 51.54 72.97


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.67 83.33 100.00 gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_err 35.12 28.00 0.00 12.50 100.00
u_reqfifo 59.44 77.78 50.00 50.00 60.00
u_rsp_gen 100.00 100.00 100.00
u_rspfifo 59.00 80.56 45.45 50.00 60.00
u_sram_byte 50.58 83.15 45.83 0.00 52.50 71.43
u_sramreqfifo 59.44 77.78 50.00 50.00 60.00



Module Instance : tb.dut.u_tl_adapter_eflash

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
68.44 93.22 22.22 75.00 83.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
45.10 62.32 33.33 0.00 56.15 73.68


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
66.52 91.74 69.23 13.28 75.00 83.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_cmd_intg_check.u_cmd_intg_chk 51.33 2.65 100.00
u_err 56.50 76.00 0.00 50.00 100.00
u_reqfifo 59.44 77.78 50.00 50.00 60.00
u_rsp_gen 100.00 100.00 100.00
u_rspfifo 59.00 80.56 45.45 50.00 60.00
u_sram_byte 51.20 85.39 41.67 0.00 57.50 71.43
u_sramreqfifo 59.44 77.78 50.00 50.00 60.00



Module Instance : tb.dut.u_to_prog_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.69 100.00 69.44 90.00 83.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
59.05 92.73 59.52 0.00 64.62 78.38


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
66.52 91.74 69.23 13.28 75.00 83.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_err 62.50 100.00 0.00 50.00 100.00
u_reqfifo 88.19 94.44 83.33 75.00 100.00
u_rsp_gen 91.67 83.33 100.00
u_rspfifo 64.90 87.10 62.50 50.00 60.00
u_sram_byte 55.71 92.13 50.00 0.00 65.00 71.43
u_sramreqfifo 60.31 81.25 50.00 50.00 60.00



Module Instance : tb.dut.u_to_rd_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.50 100.00 75.00 95.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.04 95.10 66.67 0.00 73.85 94.59


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
66.52 91.74 69.23 13.28 75.00 83.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_err 62.50 100.00 0.00 50.00 100.00
u_reqfifo 88.19 94.44 83.33 75.00 100.00
u_rsp_gen 91.67 83.33 100.00
u_rspfifo 88.38 94.44 81.82 77.27 100.00
u_sram_byte 55.71 92.13 50.00 0.00 65.00 71.43
u_sramreqfifo 88.19 94.44 83.33 75.00 100.00

Line Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=0,ErrOnRead=1,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=0 )
Line Coverage for Module self-instances :
SCORELINE
85.69 100.00
tb.dut.u_to_prog_fifo

Line No.TotalCoveredPercent
TOTAL5656100.00
ALWAYS8933100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN10311100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN21511100.00
CONT_ASSIGN21611100.00
CONT_ASSIGN21711100.00
ALWAYS22288100.00
ALWAYS24266100.00
CONT_ASSIGN25611100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28211100.00
ALWAYS31266100.00
ALWAYS32455100.00
CONT_ASSIGN33911100.00
CONT_ASSIGN34011100.00
CONT_ASSIGN34111100.00
CONT_ASSIGN34511100.00
CONT_ASSIGN34611100.00
CONT_ASSIGN34811100.00
CONT_ASSIGN35511100.00
CONT_ASSIGN36211100.00
CONT_ASSIGN36300
CONT_ASSIGN36500
ALWAYS37833100.00
CONT_ASSIGN38511100.00
CONT_ASSIGN38611100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN39800
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
89 1 1
90 1 1
91 1 1
92 unreachable
MISSING_ELSE
98 1 1
103 1 1
109 1 1
119 1 1
133 1 1
145 1 1
215 1 1
216 1 1
217 1 1
222 1 1
224 1 1
225 1 1
227 1 1
228 1 1
229 1 1
232 1 1
235 1 1
242 1 1
244 1 1
245 1 1
246 1 1
248 1 1
251 1 1
256 1 1
279 1 1
280 1 1
281 1 1
282 1 1
312 1 1
313 1 1
315 1 1
316 1 1
317 1 1
318 1 1
MISSING_ELSE
324 1 1
325 1 1
327 1 1
328 1 1
329 1 1
MISSING_ELSE
339 1 1
340 1 1
341 1 1
345 1 1
346 1 1
348 1 1
355 1 1
362 1 1
363 unreachable
365 unreachable
378 1 1
379 1 1
380 1 1
385 1 1
386 1 1
393 1 1
398 unreachable


Line Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=0 )
Line Coverage for Module self-instances :
SCORELINE
92.50 100.00
tb.dut.u_to_rd_fifo

Line No.TotalCoveredPercent
TOTAL5858100.00
ALWAYS8933100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN10311100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN21511100.00
CONT_ASSIGN21611100.00
CONT_ASSIGN21711100.00
ALWAYS22288100.00
ALWAYS24266100.00
CONT_ASSIGN25611100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28211100.00
ALWAYS31266100.00
ALWAYS32455100.00
CONT_ASSIGN33911100.00
CONT_ASSIGN34011100.00
CONT_ASSIGN34111100.00
CONT_ASSIGN34511100.00
CONT_ASSIGN34611100.00
CONT_ASSIGN34811100.00
CONT_ASSIGN35511100.00
CONT_ASSIGN36211100.00
CONT_ASSIGN36311100.00
CONT_ASSIGN36511100.00
ALWAYS37833100.00
CONT_ASSIGN38511100.00
CONT_ASSIGN38611100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN39800
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
89 1 1
90 1 1
91 1 1
92 unreachable
MISSING_ELSE
98 1 1
103 1 1
109 1 1
113 1 1
133 1 1
145 1 1
215 1 1
216 1 1
217 1 1
222 1 1
224 1 1
225 1 1
227 1 1
228 1 1
229 1 1
232 1 1
235 1 1
242 1 1
244 1 1
245 1 1
246 1 1
248 1 1
251 1 1
256 1 1
279 1 1
280 1 1
281 1 1
282 1 1
312 1 1
313 1 1
315 1 1
316 1 1
317 1 1
318 1 1
MISSING_ELSE
324 1 1
325 1 1
327 1 1
328 1 1
329 1 1
MISSING_ELSE
339 1 1
340 1 1
341 1 1
345 1 1
346 1 1
348 1 1
355 1 1
362 1 1
363 1 1
365 1 1
378 1 1
379 1 1
380 1 1
385 1 1
386 1 1
393 1 1
398 unreachable


Line Coverage for Module : tlul_adapter_sram ( parameter SramAw=18,SramDw=32,Outstanding=2,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=1,EnableRspIntgGen=1,EnableDataIntgGen=1,EnableDataIntgPt=0 )
Line Coverage for Module self-instances :
SCORELINE
68.44 93.22
tb.dut.u_tl_adapter_eflash

Line No.TotalCoveredPercent
TOTAL595593.22
ALWAYS894375.00
CONT_ASSIGN9811100.00
CONT_ASSIGN103100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN113100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN21511100.00
CONT_ASSIGN21611100.00
CONT_ASSIGN21711100.00
ALWAYS22288100.00
ALWAYS24266100.00
CONT_ASSIGN25611100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN280100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28211100.00
ALWAYS31266100.00
ALWAYS32455100.00
CONT_ASSIGN33911100.00
CONT_ASSIGN34011100.00
CONT_ASSIGN34111100.00
CONT_ASSIGN34511100.00
CONT_ASSIGN34611100.00
CONT_ASSIGN34811100.00
CONT_ASSIGN35511100.00
CONT_ASSIGN36211100.00
CONT_ASSIGN36311100.00
CONT_ASSIGN36511100.00
ALWAYS37833100.00
CONT_ASSIGN38511100.00
CONT_ASSIGN38611100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN39800
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
89 1 1
90 1 1
91 1 1
92 0 1
MISSING_ELSE
98 1 1
103 0 1
109 1 1
113 0 1
133 1 1
145 1 1
215 1 1
216 1 1
217 1 1
222 1 1
224 1 1
225 1 1
227 1 1
228 1 1
229 1 1
232 1 1
235 1 1
242 1 1
244 1 1
245 1 1
246 1 1
248 1 1
251 1 1
256 1 1
279 1 1
280 0 1
281 1 1
282 1 1
312 1 1
313 1 1
315 1 1
316 1 1
317 1 1
318 1 1
MISSING_ELSE
324 1 1
325 1 1
327 1 1
328 1 1
329 1 1
MISSING_ELSE
339 1 1
340 1 1
341 1 1
345 1 1
346 1 1
348 1 1
355 1 1
362 1 1
363 1 1
365 1 1
378 1 1
379 1 1
380 1 1
385 1 1
386 1 1
393 1 1
398 unreachable


Line Coverage for Module : tlul_adapter_sram ( parameter SramAw=5,SramDw=32,Outstanding=2,ByteAccess=1,ErrOnWrite=0,ErrOnRead=0,CmdIntgCheck=0,EnableRspIntgGen=1,EnableDataIntgGen=1,EnableDataIntgPt=0 )
Line Coverage for Module self-instances :
SCORELINE
62.46 63.16
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg

Line No.TotalCoveredPercent
TOTAL573663.16
ALWAYS8933100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN103100.00
CONT_ASSIGN109100.00
CONT_ASSIGN133100.00
CONT_ASSIGN145100.00
CONT_ASSIGN21511100.00
CONT_ASSIGN21611100.00
CONT_ASSIGN217100.00
ALWAYS22288100.00
ALWAYS24266100.00
CONT_ASSIGN25611100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN280100.00
CONT_ASSIGN281100.00
CONT_ASSIGN282100.00
ALWAYS3126350.00
ALWAYS3245360.00
CONT_ASSIGN339100.00
CONT_ASSIGN340100.00
CONT_ASSIGN341100.00
CONT_ASSIGN345100.00
CONT_ASSIGN346100.00
CONT_ASSIGN348100.00
CONT_ASSIGN355100.00
CONT_ASSIGN362100.00
CONT_ASSIGN36311100.00
CONT_ASSIGN36511100.00
ALWAYS37833100.00
CONT_ASSIGN38511100.00
CONT_ASSIGN38611100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN39800
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
89 1 1
90 1 1
91 1 1
92 unreachable
MISSING_ELSE
98 1 1
103 0 1
109 0 1
133 0 1
145 0 1
215 1 1
216 1 1
217 0 1
222 1 1
224 1 1
225 1 1
227 1 1
228 1 1
229 1 1
232 1 1
235 1 1
242 1 1
244 1 1
245 1 1
246 1 1
248 1 1
251 1 1
256 1 1
279 1 1
280 0 1
281 0 1
282 0 1
312 1 1
313 1 1
315 1 1
316 0 1
317 0 1
318 0 1
MISSING_ELSE
324 1 1
325 1 1
327 1 1
328 0 1
329 0 1
MISSING_ELSE
339 0 1
340 0 1
341 0 1
345 0 1
346 0 1
348 0 1
355 0 1
362 0 1
363 1 1
365 1 1
378 1 1
379 1 1
380 1 1
385 1 1
386 1 1
393 1 1
398 unreachable


Cond Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=0,ErrOnRead=1,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=0 + SramAw=1,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=0 )
Cond Coverage for Module self-instances :
SCORECOND
85.69 69.44
tb.dut.u_to_prog_fifo

SCORECOND
92.50 75.00
tb.dut.u_to_rd_fifo

TotalCoveredPercent
Conditions363186.11
Logical363186.11
Non-Logical00
Event00

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       103
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       103
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3

 LINE       257
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       257
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       257
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       257
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       257
 EXPRESSION ((d_valid && vld_rd_rsp) ? rspfifo_rdata.data : '0)
             -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       257
 SUB-EXPRESSION (d_valid && vld_rd_rsp)
                 ---1---    -----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       257
 EXPRESSION ((d_valid && vld_rd_rsp) ? rspfifo_rdata.data_intg : '0)
             -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       257
 SUB-EXPRESSION (d_valid && vld_rd_rsp)
                 ---1---    -----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       257
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       282
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       349
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       393
 EXPRESSION ((((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : tlul_adapter_sram ( parameter SramAw=18,SramDw=32,Outstanding=2,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=1,EnableRspIntgGen=1,EnableDataIntgGen=1,EnableDataIntgPt=0 )
Cond Coverage for Module self-instances :
SCORECOND
68.44 22.22
tb.dut.u_tl_adapter_eflash

TotalCoveredPercent
Conditions36822.22
Logical36822.22
Non-Logical00
Event00

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0Not Covered
1Not Covered

 LINE       103
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

 LINE       103
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

 LINE       257
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       257
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       257
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       257
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       257
 EXPRESSION ((d_valid && vld_rd_rsp) ? rspfifo_rdata.data : '0)
             -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       257
 SUB-EXPRESSION (d_valid && vld_rd_rsp)
                 ---1---    -----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       257
 EXPRESSION ((d_valid && vld_rd_rsp) ? rspfifo_rdata.data_intg : '0)
             -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       257
 SUB-EXPRESSION (d_valid && vld_rd_rsp)
                 ---1---    -----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       257
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       282
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       349
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       393
 EXPRESSION ((((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

Cond Coverage for Module : tlul_adapter_sram ( parameter SramAw=5,SramDw=32,Outstanding=2,ByteAccess=1,ErrOnWrite=0,ErrOnRead=0,CmdIntgCheck=0,EnableRspIntgGen=1,EnableDataIntgGen=1,EnableDataIntgPt=0 )
Cond Coverage for Module self-instances :
SCORECOND
62.46 33.33
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg

TotalCoveredPercent
Conditions331133.33
Logical331133.33
Non-Logical00
Event00

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? (((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0)) : 1'b0)
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       103
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00Not Covered
01Not Covered
10CoveredT1,T2,T3

 LINE       257
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       257
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       257
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       257
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       257
 EXPRESSION ((d_valid && vld_rd_rsp) ? rspfifo_rdata.data : '0)
             -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       257
 SUB-EXPRESSION (d_valid && vld_rd_rsp)
                 ---1---    -----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       257
 EXPRESSION ((d_valid && vld_rd_rsp) ? rspfifo_rdata.data_intg : '0)
             -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       257
 SUB-EXPRESSION (d_valid && vld_rd_rsp)
                 ---1---    -----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       257
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       282
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       349
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       393
 EXPRESSION ((((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

Branch Coverage for Module : tlul_adapter_sram
Line No.TotalCoveredPercent
Branches 20 19 95.00
TERNARY 103 2 2 100.00
TERNARY 282 2 2 100.00
TERNARY 393 2 2 100.00
IF 89 3 2 66.67
IF 224 4 4 100.00
IF 244 3 3 100.00
IF 315 2 2 100.00
IF 327 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 103 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 282 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 393 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_ni)) -2-: 91 if (intg_error)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 224 if (reqfifo_rvalid) -2-: 225 if (reqfifo_rdata.error) -3-: 228 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTests
1 1 - Covered T1,T2,T3
1 0 1 Covered T1,T2,T3
1 0 0 Covered T1,T2,T3
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 244 if (reqfifo_rvalid) -2-: 245 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Covered T1,T2,T3
0 - Covered T1,T2,T3


LineNo. Expression -1-: 315 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 327 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : tlul_adapter_sram
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 12 12 100.00 12 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 12 12 100.00 12 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 7250072 7233480 0 0
DataIntgOptions_A 220 220 0 0
ReqOutKnown_A 7250072 7233480 0 0
SramDwHasByteGranularity_A 220 220 0 0
SramDwIsMultipleOfTlulWidth_A 220 220 0 0
TlOutKnown_A 7250072 7233480 0 0
WdataOutKnown_A 7250072 7233480 0 0
WeOutKnown_A 7250072 7233480 0 0
WmaskOutKnown_A 7250072 7233480 0 0
adapterNoReadOrWrite 220 220 0 0
rvalidHighReqFifoEmpty 7250072 8629 0 0
rvalidHighWhenRspFifoFull 7250072 8629 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7250072 7233480 0 0
T1 27604 27220 0 0
T2 31760 31508 0 0
T3 37956 37676 0 0
T4 4880 4564 0 0
T5 50424 50132 0 0
T6 1113664 1113324 0 0
T7 22364 22140 0 0
T8 30624 30352 0 0
T9 40100 39868 0 0
T10 587084 586804 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 220 220 0 0
T1 4 4 0 0
T2 4 4 0 0
T3 4 4 0 0
T4 4 4 0 0
T5 4 4 0 0
T6 4 4 0 0
T7 4 4 0 0
T8 4 4 0 0
T9 4 4 0 0
T10 4 4 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7250072 7233480 0 0
T1 27604 27220 0 0
T2 31760 31508 0 0
T3 37956 37676 0 0
T4 4880 4564 0 0
T5 50424 50132 0 0
T6 1113664 1113324 0 0
T7 22364 22140 0 0
T8 30624 30352 0 0
T9 40100 39868 0 0
T10 587084 586804 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 220 220 0 0
T1 4 4 0 0
T2 4 4 0 0
T3 4 4 0 0
T4 4 4 0 0
T5 4 4 0 0
T6 4 4 0 0
T7 4 4 0 0
T8 4 4 0 0
T9 4 4 0 0
T10 4 4 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 220 220 0 0
T1 4 4 0 0
T2 4 4 0 0
T3 4 4 0 0
T4 4 4 0 0
T5 4 4 0 0
T6 4 4 0 0
T7 4 4 0 0
T8 4 4 0 0
T9 4 4 0 0
T10 4 4 0 0

TlOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7250072 7233480 0 0
T1 27604 27220 0 0
T2 31760 31508 0 0
T3 37956 37676 0 0
T4 4880 4564 0 0
T5 50424 50132 0 0
T6 1113664 1113324 0 0
T7 22364 22140 0 0
T8 30624 30352 0 0
T9 40100 39868 0 0
T10 587084 586804 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7250072 7233480 0 0
T1 27604 27220 0 0
T2 31760 31508 0 0
T3 37956 37676 0 0
T4 4880 4564 0 0
T5 50424 50132 0 0
T6 1113664 1113324 0 0
T7 22364 22140 0 0
T8 30624 30352 0 0
T9 40100 39868 0 0
T10 587084 586804 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7250072 7233480 0 0
T1 27604 27220 0 0
T2 31760 31508 0 0
T3 37956 37676 0 0
T4 4880 4564 0 0
T5 50424 50132 0 0
T6 1113664 1113324 0 0
T7 22364 22140 0 0
T8 30624 30352 0 0
T9 40100 39868 0 0
T10 587084 586804 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7250072 7233480 0 0
T1 27604 27220 0 0
T2 31760 31508 0 0
T3 37956 37676 0 0
T4 4880 4564 0 0
T5 50424 50132 0 0
T6 1113664 1113324 0 0
T7 22364 22140 0 0
T8 30624 30352 0 0
T9 40100 39868 0 0
T10 587084 586804 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 220 220 0 0
T1 4 4 0 0
T2 4 4 0 0
T3 4 4 0 0
T4 4 4 0 0
T5 4 4 0 0
T6 4 4 0 0
T7 4 4 0 0
T8 4 4 0 0
T9 4 4 0 0
T10 4 4 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 7250072 8629 0 0
T1 6901 154 0 0
T2 7940 83 0 0
T3 9489 119 0 0
T4 1220 6 0 0
T5 12606 261 0 0
T6 278416 134 0 0
T7 5591 126 0 0
T8 7656 162 0 0
T9 10025 166 0 0
T10 146771 215 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 7250072 8629 0 0
T1 6901 154 0 0
T2 7940 83 0 0
T3 9489 119 0 0
T4 1220 6 0 0
T5 12606 261 0 0
T6 278416 134 0 0
T7 5591 126 0 0
T8 7656 162 0 0
T9 10025 166 0 0
T10 146771 215 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg
Line No.TotalCoveredPercent
TOTAL573663.16
ALWAYS8933100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN103100.00
CONT_ASSIGN109100.00
CONT_ASSIGN133100.00
CONT_ASSIGN145100.00
CONT_ASSIGN21511100.00
CONT_ASSIGN21611100.00
CONT_ASSIGN217100.00
ALWAYS22288100.00
ALWAYS24266100.00
CONT_ASSIGN25611100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN280100.00
CONT_ASSIGN281100.00
CONT_ASSIGN282100.00
ALWAYS3126350.00
ALWAYS3245360.00
CONT_ASSIGN339100.00
CONT_ASSIGN340100.00
CONT_ASSIGN341100.00
CONT_ASSIGN345100.00
CONT_ASSIGN346100.00
CONT_ASSIGN348100.00
CONT_ASSIGN355100.00
CONT_ASSIGN362100.00
CONT_ASSIGN36311100.00
CONT_ASSIGN36511100.00
ALWAYS37833100.00
CONT_ASSIGN38511100.00
CONT_ASSIGN38611100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN39800
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
89 1 1
90 1 1
91 1 1
92 unreachable
MISSING_ELSE
98 1 1
103 0 1
109 0 1
133 0 1
145 0 1
215 1 1
216 1 1
217 0 1
222 1 1
224 1 1
225 1 1
227 1 1
228 1 1
229 1 1
232 1 1
235 1 1
242 1 1
244 1 1
245 1 1
246 1 1
248 1 1
251 1 1
256 1 1
279 1 1
280 0 1
281 0 1
282 0 1
312 1 1
313 1 1
315 1 1
316 0 1
317 0 1
318 0 1
MISSING_ELSE
324 1 1
325 1 1
327 1 1
328 0 1
329 0 1
MISSING_ELSE
339 0 1
340 0 1
341 0 1
345 0 1
346 0 1
348 0 1
355 0 1
362 0 1
363 1 1
365 1 1
378 1 1
379 1 1
380 1 1
385 1 1
386 1 1
393 1 1
398 unreachable


Cond Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg
TotalCoveredPercent
Conditions331133.33
Logical331133.33
Non-Logical00
Event00

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? (((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0)) : 1'b0)
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       103
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00Not Covered
01Not Covered
10CoveredT1,T2,T3

 LINE       257
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       257
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       257
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       257
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       257
 EXPRESSION ((d_valid && vld_rd_rsp) ? rspfifo_rdata.data : '0)
             -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       257
 SUB-EXPRESSION (d_valid && vld_rd_rsp)
                 ---1---    -----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       257
 EXPRESSION ((d_valid && vld_rd_rsp) ? rspfifo_rdata.data_intg : '0)
             -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       257
 SUB-EXPRESSION (d_valid && vld_rd_rsp)
                 ---1---    -----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       257
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       282
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       349
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       393
 EXPRESSION ((((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg
Line No.TotalCoveredPercent
Branches 20 14 70.00
TERNARY 103 2 1 50.00
TERNARY 282 2 1 50.00
TERNARY 393 2 1 50.00
IF 89 3 2 66.67
IF 224 4 4 100.00
IF 244 3 3 100.00
IF 315 2 1 50.00
IF 327 2 1 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 103 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 282 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 393 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_ni)) -2-: 91 if (intg_error)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 224 if (reqfifo_rvalid) -2-: 225 if (reqfifo_rdata.error) -3-: 228 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTests
1 1 - Covered T1,T2,T3
1 0 1 Covered T1,T2,T3
1 0 0 Covered T1,T2,T3
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 244 if (reqfifo_rvalid) -2-: 245 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Covered T1,T2,T3
0 - Covered T1,T2,T3


LineNo. Expression -1-: 315 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 327 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 12 12 100.00 10 83.33
Cover properties 0 0 0
Cover sequences 0 0 0
Total 12 12 100.00 10 83.33




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 1812518 1808370 0 0
DataIntgOptions_A 55 55 0 0
ReqOutKnown_A 1812518 1808370 0 0
SramDwHasByteGranularity_A 55 55 0 0
SramDwIsMultipleOfTlulWidth_A 55 55 0 0
TlOutKnown_A 1812518 1808370 0 0
WdataOutKnown_A 1812518 1808370 0 0
WeOutKnown_A 1812518 1808370 0 0
WmaskOutKnown_A 1812518 1808370 0 0
adapterNoReadOrWrite 55 55 0 0
rvalidHighReqFifoEmpty 1812518 0 0 0
rvalidHighWhenRspFifoFull 1812518 0 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 1808370 0 0
T1 6901 6805 0 0
T2 7940 7877 0 0
T3 9489 9419 0 0
T4 1220 1141 0 0
T5 12606 12533 0 0
T6 278416 278331 0 0
T7 5591 5535 0 0
T8 7656 7588 0 0
T9 10025 9967 0 0
T10 146771 146701 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 1808370 0 0
T1 6901 6805 0 0
T2 7940 7877 0 0
T3 9489 9419 0 0
T4 1220 1141 0 0
T5 12606 12533 0 0
T6 278416 278331 0 0
T7 5591 5535 0 0
T8 7656 7588 0 0
T9 10025 9967 0 0
T10 146771 146701 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

TlOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 1808370 0 0
T1 6901 6805 0 0
T2 7940 7877 0 0
T3 9489 9419 0 0
T4 1220 1141 0 0
T5 12606 12533 0 0
T6 278416 278331 0 0
T7 5591 5535 0 0
T8 7656 7588 0 0
T9 10025 9967 0 0
T10 146771 146701 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 1808370 0 0
T1 6901 6805 0 0
T2 7940 7877 0 0
T3 9489 9419 0 0
T4 1220 1141 0 0
T5 12606 12533 0 0
T6 278416 278331 0 0
T7 5591 5535 0 0
T8 7656 7588 0 0
T9 10025 9967 0 0
T10 146771 146701 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 1808370 0 0
T1 6901 6805 0 0
T2 7940 7877 0 0
T3 9489 9419 0 0
T4 1220 1141 0 0
T5 12606 12533 0 0
T6 278416 278331 0 0
T7 5591 5535 0 0
T8 7656 7588 0 0
T9 10025 9967 0 0
T10 146771 146701 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 1808370 0 0
T1 6901 6805 0 0
T2 7940 7877 0 0
T3 9489 9419 0 0
T4 1220 1141 0 0
T5 12606 12533 0 0
T6 278416 278331 0 0
T7 5591 5535 0 0
T8 7656 7588 0 0
T9 10025 9967 0 0
T10 146771 146701 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash
Line No.TotalCoveredPercent
TOTAL595593.22
ALWAYS894375.00
CONT_ASSIGN9811100.00
CONT_ASSIGN103100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN113100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN21511100.00
CONT_ASSIGN21611100.00
CONT_ASSIGN21711100.00
ALWAYS22288100.00
ALWAYS24266100.00
CONT_ASSIGN25611100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN280100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28211100.00
ALWAYS31266100.00
ALWAYS32455100.00
CONT_ASSIGN33911100.00
CONT_ASSIGN34011100.00
CONT_ASSIGN34111100.00
CONT_ASSIGN34511100.00
CONT_ASSIGN34611100.00
CONT_ASSIGN34811100.00
CONT_ASSIGN35511100.00
CONT_ASSIGN36211100.00
CONT_ASSIGN36311100.00
CONT_ASSIGN36511100.00
ALWAYS37833100.00
CONT_ASSIGN38511100.00
CONT_ASSIGN38611100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN39800
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
89 1 1
90 1 1
91 1 1
92 0 1
MISSING_ELSE
98 1 1
103 0 1
109 1 1
113 0 1
133 1 1
145 1 1
215 1 1
216 1 1
217 1 1
222 1 1
224 1 1
225 1 1
227 1 1
228 1 1
229 1 1
232 1 1
235 1 1
242 1 1
244 1 1
245 1 1
246 1 1
248 1 1
251 1 1
256 1 1
279 1 1
280 0 1
281 1 1
282 1 1
312 1 1
313 1 1
315 1 1
316 1 1
317 1 1
318 1 1
MISSING_ELSE
324 1 1
325 1 1
327 1 1
328 1 1
329 1 1
MISSING_ELSE
339 1 1
340 1 1
341 1 1
345 1 1
346 1 1
348 1 1
355 1 1
362 1 1
363 1 1
365 1 1
378 1 1
379 1 1
380 1 1
385 1 1
386 1 1
393 1 1
398 unreachable


Cond Coverage for Instance : tb.dut.u_tl_adapter_eflash
TotalCoveredPercent
Conditions36822.22
Logical36822.22
Non-Logical00
Event00

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0Not Covered
1Not Covered

 LINE       103
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

 LINE       103
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

 LINE       257
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       257
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       257
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       257
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       257
 EXPRESSION ((d_valid && vld_rd_rsp) ? rspfifo_rdata.data : '0)
             -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       257
 SUB-EXPRESSION (d_valid && vld_rd_rsp)
                 ---1---    -----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       257
 EXPRESSION ((d_valid && vld_rd_rsp) ? rspfifo_rdata.data_intg : '0)
             -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       257
 SUB-EXPRESSION (d_valid && vld_rd_rsp)
                 ---1---    -----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       257
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       282
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       349
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       393
 EXPRESSION ((((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash
Line No.TotalCoveredPercent
Branches 20 15 75.00
TERNARY 103 2 0 0.00
TERNARY 282 2 1 50.00
TERNARY 393 2 1 50.00
IF 89 3 2 66.67
IF 224 4 4 100.00
IF 244 3 3 100.00
IF 315 2 2 100.00
IF 327 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 103 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered


LineNo. Expression -1-: 282 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 393 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_ni)) -2-: 91 if (intg_error)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 224 if (reqfifo_rvalid) -2-: 225 if (reqfifo_rdata.error) -3-: 228 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTests
1 1 - Covered T1,T2,T3
1 0 1 Covered T1,T2,T3
1 0 0 Covered T1,T2,T3
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 244 if (reqfifo_rvalid) -2-: 245 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Covered T1,T2,T3
0 - Covered T1,T2,T3


LineNo. Expression -1-: 315 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 327 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 12 12 100.00 10 83.33
Cover properties 0 0 0
Cover sequences 0 0 0
Total 12 12 100.00 10 83.33




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 1812518 1808370 0 0
DataIntgOptions_A 55 55 0 0
ReqOutKnown_A 1812518 1808370 0 0
SramDwHasByteGranularity_A 55 55 0 0
SramDwIsMultipleOfTlulWidth_A 55 55 0 0
TlOutKnown_A 1812518 1808370 0 0
WdataOutKnown_A 1812518 1808370 0 0
WeOutKnown_A 1812518 1808370 0 0
WmaskOutKnown_A 1812518 1808370 0 0
adapterNoReadOrWrite 55 55 0 0
rvalidHighReqFifoEmpty 1812518 0 0 0
rvalidHighWhenRspFifoFull 1812518 0 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 1808370 0 0
T1 6901 6805 0 0
T2 7940 7877 0 0
T3 9489 9419 0 0
T4 1220 1141 0 0
T5 12606 12533 0 0
T6 278416 278331 0 0
T7 5591 5535 0 0
T8 7656 7588 0 0
T9 10025 9967 0 0
T10 146771 146701 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 1808370 0 0
T1 6901 6805 0 0
T2 7940 7877 0 0
T3 9489 9419 0 0
T4 1220 1141 0 0
T5 12606 12533 0 0
T6 278416 278331 0 0
T7 5591 5535 0 0
T8 7656 7588 0 0
T9 10025 9967 0 0
T10 146771 146701 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

TlOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 1808370 0 0
T1 6901 6805 0 0
T2 7940 7877 0 0
T3 9489 9419 0 0
T4 1220 1141 0 0
T5 12606 12533 0 0
T6 278416 278331 0 0
T7 5591 5535 0 0
T8 7656 7588 0 0
T9 10025 9967 0 0
T10 146771 146701 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 1808370 0 0
T1 6901 6805 0 0
T2 7940 7877 0 0
T3 9489 9419 0 0
T4 1220 1141 0 0
T5 12606 12533 0 0
T6 278416 278331 0 0
T7 5591 5535 0 0
T8 7656 7588 0 0
T9 10025 9967 0 0
T10 146771 146701 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 1808370 0 0
T1 6901 6805 0 0
T2 7940 7877 0 0
T3 9489 9419 0 0
T4 1220 1141 0 0
T5 12606 12533 0 0
T6 278416 278331 0 0
T7 5591 5535 0 0
T8 7656 7588 0 0
T9 10025 9967 0 0
T10 146771 146701 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 1808370 0 0
T1 6901 6805 0 0
T2 7940 7877 0 0
T3 9489 9419 0 0
T4 1220 1141 0 0
T5 12606 12533 0 0
T6 278416 278331 0 0
T7 5591 5535 0 0
T8 7656 7588 0 0
T9 10025 9967 0 0
T10 146771 146701 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

Line Coverage for Instance : tb.dut.u_to_prog_fifo
Line No.TotalCoveredPercent
TOTAL5656100.00
ALWAYS8933100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN10311100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN21511100.00
CONT_ASSIGN21611100.00
CONT_ASSIGN21711100.00
ALWAYS22288100.00
ALWAYS24266100.00
CONT_ASSIGN25611100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28211100.00
ALWAYS31266100.00
ALWAYS32455100.00
CONT_ASSIGN33911100.00
CONT_ASSIGN34011100.00
CONT_ASSIGN34111100.00
CONT_ASSIGN34511100.00
CONT_ASSIGN34611100.00
CONT_ASSIGN34811100.00
CONT_ASSIGN35511100.00
CONT_ASSIGN36211100.00
CONT_ASSIGN36300
CONT_ASSIGN36500
ALWAYS37833100.00
CONT_ASSIGN38511100.00
CONT_ASSIGN38611100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN39800
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
89 1 1
90 1 1
91 1 1
92 unreachable
MISSING_ELSE
98 1 1
103 1 1
109 1 1
119 1 1
133 1 1
145 1 1
215 1 1
216 1 1
217 1 1
222 1 1
224 1 1
225 1 1
227 1 1
228 1 1
229 1 1
232 1 1
235 1 1
242 1 1
244 1 1
245 1 1
246 1 1
248 1 1
251 1 1
256 1 1
279 1 1
280 1 1
281 1 1
282 1 1
312 1 1
313 1 1
315 1 1
316 1 1
317 1 1
318 1 1
MISSING_ELSE
324 1 1
325 1 1
327 1 1
328 1 1
329 1 1
MISSING_ELSE
339 1 1
340 1 1
341 1 1
345 1 1
346 1 1
348 1 1
355 1 1
362 1 1
363 unreachable
365 unreachable
378 1 1
379 1 1
380 1 1
385 1 1
386 1 1
393 1 1
398 unreachable


Cond Coverage for Instance : tb.dut.u_to_prog_fifo
TotalCoveredPercent
Conditions362569.44
Logical362569.44
Non-Logical00
Event00

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       103
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       103
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3

 LINE       257
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       257
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       257
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       257
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       257
 EXPRESSION ((d_valid && vld_rd_rsp) ? rspfifo_rdata.data : '0)
             -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       257
 SUB-EXPRESSION (d_valid && vld_rd_rsp)
                 ---1---    -----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       257
 EXPRESSION ((d_valid && vld_rd_rsp) ? rspfifo_rdata.data_intg : '0)
             -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       257
 SUB-EXPRESSION (d_valid && vld_rd_rsp)
                 ---1---    -----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       257
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       282
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       349
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       393
 EXPRESSION ((((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

Branch Coverage for Instance : tb.dut.u_to_prog_fifo
Line No.TotalCoveredPercent
Branches 20 18 90.00
TERNARY 103 2 2 100.00
TERNARY 282 2 2 100.00
TERNARY 393 2 1 50.00
IF 89 3 2 66.67
IF 224 4 4 100.00
IF 244 3 3 100.00
IF 315 2 2 100.00
IF 327 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 103 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 282 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 393 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_ni)) -2-: 91 if (intg_error)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 224 if (reqfifo_rvalid) -2-: 225 if (reqfifo_rdata.error) -3-: 228 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTests
1 1 - Covered T1,T2,T3
1 0 1 Covered T1,T2,T3
1 0 0 Covered T1,T2,T3
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 244 if (reqfifo_rvalid) -2-: 245 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Covered T1,T2,T3
0 - Covered T1,T2,T3


LineNo. Expression -1-: 315 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 327 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_to_prog_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 12 12 100.00 10 83.33
Cover properties 0 0 0
Cover sequences 0 0 0
Total 12 12 100.00 10 83.33




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 1812518 1808370 0 0
DataIntgOptions_A 55 55 0 0
ReqOutKnown_A 1812518 1808370 0 0
SramDwHasByteGranularity_A 55 55 0 0
SramDwIsMultipleOfTlulWidth_A 55 55 0 0
TlOutKnown_A 1812518 1808370 0 0
WdataOutKnown_A 1812518 1808370 0 0
WeOutKnown_A 1812518 1808370 0 0
WmaskOutKnown_A 1812518 1808370 0 0
adapterNoReadOrWrite 55 55 0 0
rvalidHighReqFifoEmpty 1812518 0 0 0
rvalidHighWhenRspFifoFull 1812518 0 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 1808370 0 0
T1 6901 6805 0 0
T2 7940 7877 0 0
T3 9489 9419 0 0
T4 1220 1141 0 0
T5 12606 12533 0 0
T6 278416 278331 0 0
T7 5591 5535 0 0
T8 7656 7588 0 0
T9 10025 9967 0 0
T10 146771 146701 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 1808370 0 0
T1 6901 6805 0 0
T2 7940 7877 0 0
T3 9489 9419 0 0
T4 1220 1141 0 0
T5 12606 12533 0 0
T6 278416 278331 0 0
T7 5591 5535 0 0
T8 7656 7588 0 0
T9 10025 9967 0 0
T10 146771 146701 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

TlOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 1808370 0 0
T1 6901 6805 0 0
T2 7940 7877 0 0
T3 9489 9419 0 0
T4 1220 1141 0 0
T5 12606 12533 0 0
T6 278416 278331 0 0
T7 5591 5535 0 0
T8 7656 7588 0 0
T9 10025 9967 0 0
T10 146771 146701 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 1808370 0 0
T1 6901 6805 0 0
T2 7940 7877 0 0
T3 9489 9419 0 0
T4 1220 1141 0 0
T5 12606 12533 0 0
T6 278416 278331 0 0
T7 5591 5535 0 0
T8 7656 7588 0 0
T9 10025 9967 0 0
T10 146771 146701 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 1808370 0 0
T1 6901 6805 0 0
T2 7940 7877 0 0
T3 9489 9419 0 0
T4 1220 1141 0 0
T5 12606 12533 0 0
T6 278416 278331 0 0
T7 5591 5535 0 0
T8 7656 7588 0 0
T9 10025 9967 0 0
T10 146771 146701 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 1808370 0 0
T1 6901 6805 0 0
T2 7940 7877 0 0
T3 9489 9419 0 0
T4 1220 1141 0 0
T5 12606 12533 0 0
T6 278416 278331 0 0
T7 5591 5535 0 0
T8 7656 7588 0 0
T9 10025 9967 0 0
T10 146771 146701 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 0 0 0

Line Coverage for Instance : tb.dut.u_to_rd_fifo
Line No.TotalCoveredPercent
TOTAL5858100.00
ALWAYS8933100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN10311100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN21511100.00
CONT_ASSIGN21611100.00
CONT_ASSIGN21711100.00
ALWAYS22288100.00
ALWAYS24266100.00
CONT_ASSIGN25611100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28211100.00
ALWAYS31266100.00
ALWAYS32455100.00
CONT_ASSIGN33911100.00
CONT_ASSIGN34011100.00
CONT_ASSIGN34111100.00
CONT_ASSIGN34511100.00
CONT_ASSIGN34611100.00
CONT_ASSIGN34811100.00
CONT_ASSIGN35511100.00
CONT_ASSIGN36211100.00
CONT_ASSIGN36311100.00
CONT_ASSIGN36511100.00
ALWAYS37833100.00
CONT_ASSIGN38511100.00
CONT_ASSIGN38611100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN39800
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
89 1 1
90 1 1
91 1 1
92 unreachable
MISSING_ELSE
98 1 1
103 1 1
109 1 1
113 1 1
133 1 1
145 1 1
215 1 1
216 1 1
217 1 1
222 1 1
224 1 1
225 1 1
227 1 1
228 1 1
229 1 1
232 1 1
235 1 1
242 1 1
244 1 1
245 1 1
246 1 1
248 1 1
251 1 1
256 1 1
279 1 1
280 1 1
281 1 1
282 1 1
312 1 1
313 1 1
315 1 1
316 1 1
317 1 1
318 1 1
MISSING_ELSE
324 1 1
325 1 1
327 1 1
328 1 1
329 1 1
MISSING_ELSE
339 1 1
340 1 1
341 1 1
345 1 1
346 1 1
348 1 1
355 1 1
362 1 1
363 1 1
365 1 1
378 1 1
379 1 1
380 1 1
385 1 1
386 1 1
393 1 1
398 unreachable


Cond Coverage for Instance : tb.dut.u_to_rd_fifo
TotalCoveredPercent
Conditions362775.00
Logical362775.00
Non-Logical00
Event00

 LINE       103
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       103
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       103
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3

 LINE       257
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       257
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       257
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       257
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       257
 EXPRESSION ((d_valid && vld_rd_rsp) ? rspfifo_rdata.data : '0)
             -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       257
 SUB-EXPRESSION (d_valid && vld_rd_rsp)
                 ---1---    -----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T2,T3

 LINE       257
 EXPRESSION ((d_valid && vld_rd_rsp) ? rspfifo_rdata.data_intg : '0)
             -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       257
 SUB-EXPRESSION (d_valid && vld_rd_rsp)
                 ---1---    -----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T2,T3

 LINE       257
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       282
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       349
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       393
 EXPRESSION ((((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_to_rd_fifo
Line No.TotalCoveredPercent
Branches 20 19 95.00
TERNARY 103 2 2 100.00
TERNARY 282 2 2 100.00
TERNARY 393 2 2 100.00
IF 89 3 2 66.67
IF 224 4 4 100.00
IF 244 3 3 100.00
IF 315 2 2 100.00
IF 327 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 103 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 282 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 393 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 89 if ((!rst_ni)) -2-: 91 if (intg_error)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 224 if (reqfifo_rvalid) -2-: 225 if (reqfifo_rdata.error) -3-: 228 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTests
1 1 - Covered T1,T2,T3
1 0 1 Covered T1,T2,T3
1 0 0 Covered T1,T2,T3
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 244 if (reqfifo_rvalid) -2-: 245 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Covered T1,T2,T3
0 - Covered T1,T2,T3


LineNo. Expression -1-: 315 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 327 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_to_rd_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 12 12 100.00 12 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 12 12 100.00 12 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 1812518 1808370 0 0
DataIntgOptions_A 55 55 0 0
ReqOutKnown_A 1812518 1808370 0 0
SramDwHasByteGranularity_A 55 55 0 0
SramDwIsMultipleOfTlulWidth_A 55 55 0 0
TlOutKnown_A 1812518 1808370 0 0
WdataOutKnown_A 1812518 1808370 0 0
WeOutKnown_A 1812518 1808370 0 0
WmaskOutKnown_A 1812518 1808370 0 0
adapterNoReadOrWrite 55 55 0 0
rvalidHighReqFifoEmpty 1812518 8629 0 0
rvalidHighWhenRspFifoFull 1812518 8629 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 1808370 0 0
T1 6901 6805 0 0
T2 7940 7877 0 0
T3 9489 9419 0 0
T4 1220 1141 0 0
T5 12606 12533 0 0
T6 278416 278331 0 0
T7 5591 5535 0 0
T8 7656 7588 0 0
T9 10025 9967 0 0
T10 146771 146701 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 1808370 0 0
T1 6901 6805 0 0
T2 7940 7877 0 0
T3 9489 9419 0 0
T4 1220 1141 0 0
T5 12606 12533 0 0
T6 278416 278331 0 0
T7 5591 5535 0 0
T8 7656 7588 0 0
T9 10025 9967 0 0
T10 146771 146701 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

TlOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 1808370 0 0
T1 6901 6805 0 0
T2 7940 7877 0 0
T3 9489 9419 0 0
T4 1220 1141 0 0
T5 12606 12533 0 0
T6 278416 278331 0 0
T7 5591 5535 0 0
T8 7656 7588 0 0
T9 10025 9967 0 0
T10 146771 146701 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 1808370 0 0
T1 6901 6805 0 0
T2 7940 7877 0 0
T3 9489 9419 0 0
T4 1220 1141 0 0
T5 12606 12533 0 0
T6 278416 278331 0 0
T7 5591 5535 0 0
T8 7656 7588 0 0
T9 10025 9967 0 0
T10 146771 146701 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 1808370 0 0
T1 6901 6805 0 0
T2 7940 7877 0 0
T3 9489 9419 0 0
T4 1220 1141 0 0
T5 12606 12533 0 0
T6 278416 278331 0 0
T7 5591 5535 0 0
T8 7656 7588 0 0
T9 10025 9967 0 0
T10 146771 146701 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 1808370 0 0
T1 6901 6805 0 0
T2 7940 7877 0 0
T3 9489 9419 0 0
T4 1220 1141 0 0
T5 12606 12533 0 0
T6 278416 278331 0 0
T7 5591 5535 0 0
T8 7656 7588 0 0
T9 10025 9967 0 0
T10 146771 146701 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 8629 0 0
T1 6901 154 0 0
T2 7940 83 0 0
T3 9489 119 0 0
T4 1220 6 0 0
T5 12606 261 0 0
T6 278416 134 0 0
T7 5591 126 0 0
T8 7656 162 0 0
T9 10025 166 0 0
T10 146771 215 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812518 8629 0 0
T1 6901 154 0 0
T2 7940 83 0 0
T3 9489 119 0 0
T4 1220 6 0 0
T5 12606 261 0 0
T6 278416 134 0 0
T7 5591 126 0 0
T8 7656 162 0 0
T9 10025 166 0 0
T10 146771 215 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%