FLASH_CTRL Simulation Results

Wednesday November 24 2021 02:36:22 UTC

GitHub Revision: 42406d3b9

Branch: master

Testplan

Simulator: VCS

Test Results

Milestone Name Tests Passing Total Pass Rate
V1 smoke flash_ctrl_smoke 5 5 100.00
V1 csr_hw_reset flash_ctrl_csr_hw_reset 5 5 100.00
V1 csr_rw flash_ctrl_csr_rw 20 20 100.00
V1 csr_bit_bash flash_ctrl_csr_bit_bash 5 5 100.00
V1 csr_aliasing flash_ctrl_csr_aliasing 5 5 100.00
V1 csr_mem_rw_with_rand_reset flash_ctrl_csr_mem_rw_with_rand_reset 0 20 0.00
V1 mem_walk flash_ctrl_mem_walk 5 5 100.00
V1 mem_partial_access flash_ctrl_mem_partial_access 5 5 100.00
V1 shadow_reg_update_error flash_ctrl_shadow_reg_errors 20 20 100.00
V1 shadow_reg_read_clear_staged_value flash_ctrl_shadow_reg_errors 20 20 100.00
V1 shadow_reg_storage_error flash_ctrl_shadow_reg_errors 20 20 100.00
V1 shadowed_reset_glitch flash_ctrl_shadow_reg_errors 20 20 100.00
V1 shadow_reg_update_error_with_csr_rw flash_ctrl_shadow_reg_errors_with_csr_rw 19 20 95.00
V1 TOTAL 89 110 80.91
V2 backpressure backpressure 0 0 --
V2 all_partitions flash_ctrl_rand_ops 50 50 100.00
V2 host_read_check host_read_check 0 0 --
V2 host_illegal_access host_illegal_access 0 0 --
V2 host_outstanding_access host_outstanding_access 0 0 --
V2 intr_enabled intr_enabled 0 0 --
V2 host_ctrl_arb host_ctrl_arb 0 0 --
V2 host_read_collide host_read_collide 0 0 --
V2 en_mp_regions en_mp_regions 0 0 --
V2 redundant_pages redundant_pages 0 0 --
V2 lc_ctrl_if lc_ctrl_if 0 0 --
V2 key_mgr_if key_mgr_if 0 0 --
V2 scramble scramble 0 0 --
V2 ecc ecc 0 0 --
V2 read_ecc_metadata read_ecc_metadata 0 0 --
V2 error error 0 0 --
V2 flash_macro_timing flash_macro_timing 0 0 --
V2 stress_all flash_ctrl_stress_all 0 50 0.00
V2 flash_init flash_init 0 0 --
V2 tlul_to_vendor tlul_to_vendor 0 0 --
V2 alert_test flash_ctrl_alert_test 50 50 100.00
V2 intr_test flash_ctrl_intr_test 50 50 100.00
V2 tl_d_oob_addr_access flash_ctrl_tl_errors 20 20 100.00
V2 tl_d_illegal_access flash_ctrl_tl_errors 20 20 100.00
V2 tl_d_outstanding_access flash_ctrl_csr_hw_reset 5 5 100.00
flash_ctrl_csr_rw 20 20 100.00
flash_ctrl_csr_aliasing 5 5 100.00
flash_ctrl_same_csr_outstanding 20 20 100.00
V2 tl_d_partial_access flash_ctrl_csr_hw_reset 5 5 100.00
flash_ctrl_csr_rw 20 20 100.00
flash_ctrl_csr_aliasing 5 5 100.00
flash_ctrl_same_csr_outstanding 20 20 100.00
V2 TOTAL 190 240 79.17
V2S tl_intg_err flash_ctrl_tl_intg_err 0 20 0.00
V2S TOTAL 0 20 0.00
V3 stress_all_with_rand_reset flash_ctrl_stress_all_with_rand_reset 0 50 0.00
V3 TOTAL 0 50 0.00
TOTAL 279 420 66.43

Testplan Progress

Items Total Written Passing Progress
V1 10 10 8 80.00
V2 24 6 5 20.83
V2S 1 1 0 0.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
64.94 96.10 89.98 16.99 34.84 94.65 85.56 36.46

Failure Buckets

Past Results