Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
0.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 10 0 0.00
Crosses 24 24 0 0.00


Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 6 6 0 0.00 100 1 1 0
cp_intr_en 2 2 0 0.00 100 1 1 2
cp_intr_state 2 2 0 0.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_cg_cc 24 24 0 0.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 6 0 0.00


User Defined Bins for cp_intr

Uncovered bins
NAMECOUNTAT LEASTNUMBER
all_values_0 0 1 1
all_values_1 0 1 1
all_values_2 0 1 1
all_values_3 0 1 1
all_values_4 0 1 1
all_values_5 0 1 1



Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for cp_intr_en

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[0] - auto[1]] -- -- 2



Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for cp_intr_state

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[0] - auto[1]] -- -- 2



Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 24 24 0 0.00 24


Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins
cp_intrcp_intr_encp_intr_stateCOUNTAT LEASTNUMBER
* * * -- -- 24

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%