Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 50.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_eflash_tl_agent.cov::m_tl_a_chan_cov_cg 0.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_eflash_tl_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
0.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_eflash_tl_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 134 0 0.00
Crosses 3 3 0 0.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_eflash_tl_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 1 0 0.00 100 1 1 0
cp_opcode 3 3 0 0.00 100 1 1 0
cp_size 1 1 0 0.00 100 1 1 0
cp_source 129 129 0 0.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_eflash_tl_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 3 0 0.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for cp_mask

Uncovered bins
NAMECOUNTAT LEASTNUMBER
all_enables 0 1 1


Excluded/Illegal bins
NAMECOUNTSTATUS
others 0 Excluded



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 3 0 0.00


User Defined Bins for cp_opcode

Uncovered bins
NAMECOUNTAT LEASTNUMBER
values_4 0 1 1
values_0 0 1 1
values_1 0 1 1



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for cp_size

Uncovered bins
NAMECOUNTAT LEASTNUMBER
biggest_size 0 1 1


Excluded/Illegal bins
NAMECOUNTSTATUS
others 0 Excluded



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 129 0 0.00


User Defined Bins for cp_source

Uncovered bins
NAMECOUNTAT LEASTNUMBER
valid_sources_00 0 1 1
valid_sources_01 0 1 1
valid_sources_02 0 1 1
valid_sources_03 0 1 1
valid_sources_04 0 1 1
valid_sources_05 0 1 1
valid_sources_06 0 1 1
valid_sources_07 0 1 1
valid_sources_08 0 1 1
valid_sources_09 0 1 1
valid_sources_0a 0 1 1
valid_sources_0b 0 1 1
valid_sources_0c 0 1 1
valid_sources_0d 0 1 1
valid_sources_0e 0 1 1
valid_sources_0f 0 1 1
valid_sources_10 0 1 1
valid_sources_11 0 1 1
valid_sources_12 0 1 1
valid_sources_13 0 1 1
valid_sources_14 0 1 1
valid_sources_15 0 1 1
valid_sources_16 0 1 1
valid_sources_17 0 1 1
valid_sources_18 0 1 1
valid_sources_19 0 1 1
valid_sources_1a 0 1 1
valid_sources_1b 0 1 1
valid_sources_1c 0 1 1
valid_sources_1d 0 1 1
valid_sources_1e 0 1 1
valid_sources_1f 0 1 1
valid_sources_20 0 1 1
valid_sources_21 0 1 1
valid_sources_22 0 1 1
valid_sources_23 0 1 1
valid_sources_24 0 1 1
valid_sources_25 0 1 1
valid_sources_26 0 1 1
valid_sources_27 0 1 1
valid_sources_28 0 1 1
valid_sources_29 0 1 1
valid_sources_2a 0 1 1
valid_sources_2b 0 1 1
valid_sources_2c 0 1 1
valid_sources_2d 0 1 1
valid_sources_2e 0 1 1
valid_sources_2f 0 1 1
valid_sources_30 0 1 1
valid_sources_31 0 1 1
valid_sources_32 0 1 1
valid_sources_33 0 1 1
valid_sources_34 0 1 1
valid_sources_35 0 1 1
valid_sources_36 0 1 1
valid_sources_37 0 1 1
valid_sources_38 0 1 1
valid_sources_39 0 1 1
valid_sources_3a 0 1 1
valid_sources_3b 0 1 1
valid_sources_3c 0 1 1
valid_sources_3d 0 1 1
valid_sources_3e 0 1 1
valid_sources_3f 0 1 1
valid_sources_40 0 1 1
valid_sources_41 0 1 1
valid_sources_42 0 1 1
valid_sources_43 0 1 1
valid_sources_44 0 1 1
valid_sources_45 0 1 1
valid_sources_46 0 1 1
valid_sources_47 0 1 1
valid_sources_48 0 1 1
valid_sources_49 0 1 1
valid_sources_4a 0 1 1
valid_sources_4b 0 1 1
valid_sources_4c 0 1 1
valid_sources_4d 0 1 1
valid_sources_4e 0 1 1
valid_sources_4f 0 1 1
valid_sources_50 0 1 1
valid_sources_51 0 1 1
valid_sources_52 0 1 1
valid_sources_53 0 1 1
valid_sources_54 0 1 1
valid_sources_55 0 1 1
valid_sources_56 0 1 1
valid_sources_57 0 1 1
valid_sources_58 0 1 1
valid_sources_59 0 1 1
valid_sources_5a 0 1 1
valid_sources_5b 0 1 1
valid_sources_5c 0 1 1
valid_sources_5d 0 1 1
valid_sources_5e 0 1 1
valid_sources_5f 0 1 1
valid_sources_60 0 1 1
valid_sources_61 0 1 1
valid_sources_62 0 1 1
valid_sources_63 0 1 1
valid_sources_64 0 1 1
valid_sources_65 0 1 1
valid_sources_66 0 1 1
valid_sources_67 0 1 1
valid_sources_68 0 1 1
valid_sources_69 0 1 1
valid_sources_6a 0 1 1
valid_sources_6b 0 1 1
valid_sources_6c 0 1 1
valid_sources_6d 0 1 1
valid_sources_6e 0 1 1
valid_sources_6f 0 1 1
valid_sources_70 0 1 1
valid_sources_71 0 1 1
valid_sources_72 0 1 1
valid_sources_73 0 1 1
valid_sources_74 0 1 1
valid_sources_75 0 1 1
valid_sources_76 0 1 1
valid_sources_77 0 1 1
valid_sources_78 0 1 1
valid_sources_79 0 1 1
valid_sources_7a 0 1 1
valid_sources_7b 0 1 1
valid_sources_7c 0 1 1
valid_sources_7d 0 1 1
valid_sources_7e 0 1 1
valid_sources_7f 0 1 1
valid_sources_80 0 1 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 3 0 0.00 3


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Uncovered bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTNUMBER
* * * -- -- 3


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1263880 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 800030 1 T1 19669 T2 5682 T3 139



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values_4 1631860 1 T1 37869 T2 10363 T3 114
values_0 215050 1 T1 518 T2 340 T3 60
values_1 217000 1 T1 493 T2 360 T3 70



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 925056 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 1138854 1 T1 23359 T2 6753 T3 161



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources_00 8180 1 T2 40 T3 1 T6 46
valid_sources_01 7229 1 T2 40 T4 3 T6 41
valid_sources_02 7088 1 T2 46 T3 1 T5 11
valid_sources_03 10031 1 T2 41 T4 1 T6 42
valid_sources_04 7690 1 T2 45 T4 4 T5 10
valid_sources_05 8003 1 T2 43 T4 7 T6 36
valid_sources_06 7185 1 T2 45 T5 3 T6 40
valid_sources_07 7650 1 T2 45 T4 1 T6 46
valid_sources_08 7769 1 T2 33 T4 10 T5 10
valid_sources_09 7557 1 T2 58 T6 43 T7 3
valid_sources_0a 7449 1 T2 53 T4 13 T6 42
valid_sources_0b 7186 1 T2 40 T6 49 T7 11
valid_sources_0c 6654 1 T2 49 T3 3 T5 13
valid_sources_0d 6876 1 T2 47 T5 6 T6 42
valid_sources_0e 7321 1 T2 34 T4 2 T5 3
valid_sources_0f 8687 1 T2 45 T5 5 T6 37
valid_sources_10 14210 1 T2 49 T4 17 T5 5
valid_sources_11 7559 1 T2 37 T4 11 T6 30
valid_sources_12 7547 1 T2 65 T3 3 T4 2
valid_sources_13 9659 1 T2 50 T4 4 T5 12
valid_sources_14 7336 1 T2 29 T4 4 T5 7
valid_sources_15 7412 1 T2 31 T4 1 T5 38
valid_sources_16 7526 1 T2 37 T3 2 T4 1
valid_sources_17 6855 1 T2 35 T3 1 T6 32
valid_sources_18 8056 1 T2 43 T5 18 T6 40
valid_sources_19 6819 1 T2 52 T3 2 T4 2
valid_sources_1a 16491 1 T2 43 T4 10 T5 6
valid_sources_1b 7445 1 T2 55 T6 28 T7 5
valid_sources_1c 7046 1 T2 45 T4 1 T5 5
valid_sources_1d 7545 1 T2 36 T4 1 T6 25
valid_sources_1e 7288 1 T2 34 T3 8 T4 1
valid_sources_1f 8315 1 T2 52 T4 1 T6 54
valid_sources_20 7030 1 T2 47 T4 11 T6 38
valid_sources_21 7908 1 T2 27 T3 1 T4 2
valid_sources_22 7616 1 T2 33 T3 6 T4 1
valid_sources_23 7059 1 T2 34 T6 37 T7 6
valid_sources_24 7890 1 T2 45 T4 1 T5 4
valid_sources_25 8216 1 T2 39 T3 1 T4 1
valid_sources_26 7998 1 T2 31 T4 1 T5 28
valid_sources_27 7193 1 T2 46 T4 4 T5 16
valid_sources_28 7166 1 T2 62 T4 1 T6 41
valid_sources_29 6883 1 T2 47 T4 5 T6 42
valid_sources_2a 7525 1 T2 38 T3 1 T6 40
valid_sources_2b 7278 1 T2 38 T3 1 T5 25
valid_sources_2c 6572 1 T2 30 T3 2 T4 6
valid_sources_2d 7871 1 T2 45 T3 1 T6 58
valid_sources_2e 7607 1 T2 41 T4 4 T6 41
valid_sources_2f 7838 1 T2 25 T4 2 T5 2
valid_sources_30 7719 1 T2 34 T3 1 T4 3
valid_sources_31 7560 1 T2 31 T5 8 T6 41
valid_sources_32 7440 1 T2 49 T3 1 T6 43
valid_sources_33 7367 1 T2 53 T6 46 T7 9
valid_sources_34 7192 1 T2 35 T3 1 T4 2
valid_sources_35 7708 1 T2 48 T4 3 T6 37
valid_sources_36 6899 1 T2 52 T4 4 T6 59
valid_sources_37 7059 1 T2 42 T3 4 T4 3
valid_sources_38 7988 1 T2 37 T3 1 T4 1
valid_sources_39 7325 1 T2 47 T3 2 T4 4
valid_sources_3a 7455 1 T2 50 T3 3 T4 4
valid_sources_3b 9299 1 T2 28 T4 3 T5 1
valid_sources_3c 7290 1 T2 39 T3 1 T4 1
valid_sources_3d 6822 1 T2 54 T3 1 T6 41
valid_sources_3e 7509 1 T2 40 T3 3 T4 6
valid_sources_3f 7821 1 T2 38 T4 3 T6 24
valid_sources_40 7655 1 T2 48 T3 2 T4 3
valid_sources_41 7585 1 T2 45 T4 7 T5 1
valid_sources_42 7504 1 T2 36 T4 4 T5 2
valid_sources_43 7882 1 T2 51 T5 5 T6 36
valid_sources_44 6664 1 T2 34 T4 3 T6 21
valid_sources_45 7173 1 T2 45 T4 1 T5 1
valid_sources_46 8057 1 T2 33 T3 1 T4 4
valid_sources_47 7318 1 T2 55 T3 1 T4 7
valid_sources_48 7184 1 T2 51 T3 2 T4 6
valid_sources_49 7406 1 T2 45 T3 1 T5 2
valid_sources_4a 8070 1 T2 51 T3 3 T4 8
valid_sources_4b 7267 1 T2 42 T3 3 T5 3
valid_sources_4c 13895 1 T2 43 T6 40 T7 8
valid_sources_4d 7006 1 T2 51 T3 2 T4 1
valid_sources_4e 7751 1 T2 48 T4 7 T5 2
valid_sources_4f 7470 1 T2 41 T3 2 T5 2
valid_sources_50 7337 1 T2 39 T4 8 T5 5
valid_sources_51 8075 1 T2 58 T3 1 T5 12
valid_sources_52 7171 1 T2 36 T4 8 T5 3
valid_sources_53 7241 1 T2 47 T3 1 T4 8
valid_sources_54 7080 1 T2 47 T4 1 T6 39
valid_sources_55 8459 1 T2 24 T3 1 T4 8
valid_sources_56 7458 1 T2 40 T3 6 T4 4
valid_sources_57 8223 1 T2 41 T3 2 T6 42
valid_sources_58 7080 1 T2 43 T6 40 T7 5
valid_sources_59 7015 1 T2 38 T4 4 T5 10
valid_sources_5a 7831 1 T2 39 T3 1 T4 8
valid_sources_5b 7588 1 T2 28 T3 1 T4 3
valid_sources_5c 8059 1 T2 40 T4 1 T5 23
valid_sources_5d 8678 1 T2 32 T4 14 T6 40
valid_sources_5e 8139 1 T2 52 T4 1 T5 3
valid_sources_5f 7458 1 T2 47 T4 1 T5 16
valid_sources_60 6874 1 T2 26 T4 1 T6 39
valid_sources_61 7865 1 T2 59 T4 1 T6 45
valid_sources_62 7259 1 T2 59 T4 4 T5 5
valid_sources_63 7466 1 T2 37 T3 2 T6 30
valid_sources_64 8251 1 T2 50 T3 2 T4 16
valid_sources_65 7828 1 T2 44 T3 1 T4 3
valid_sources_66 7100 1 T2 43 T6 43 T7 2
valid_sources_67 7008 1 T2 44 T3 1 T4 5
valid_sources_68 8260 1 T2 42 T3 1 T4 10
valid_sources_69 7751 1 T2 45 T4 2 T5 5
valid_sources_6a 6992 1 T2 44 T3 7 T5 13
valid_sources_6b 7467 1 T2 27 T3 4 T4 3
valid_sources_6c 45565 1 T1 38880 T2 33 T3 1
valid_sources_6d 7483 1 T2 64 T5 3 T6 38
valid_sources_6e 7016 1 T2 54 T3 2 T5 1
valid_sources_6f 7764 1 T2 26 T4 3 T6 38
valid_sources_70 7594 1 T2 61 T3 2 T5 11
valid_sources_71 11193 1 T2 32 T4 2 T5 3
valid_sources_72 6748 1 T2 40 T4 4 T5 15
valid_sources_73 7790 1 T2 40 T4 12 T6 36
valid_sources_74 7081 1 T2 38 T4 7 T6 44
valid_sources_75 8560 1 T2 25 T3 1 T4 1
valid_sources_76 15141 1 T2 40 T4 2 T5 22
valid_sources_77 7424 1 T2 33 T3 2 T4 4
valid_sources_78 7390 1 T2 36 T3 1 T4 8
valid_sources_79 7040 1 T2 55 T3 2 T4 2
valid_sources_7a 7516 1 T2 55 T3 5 T5 2
valid_sources_7b 7574 1 T2 47 T6 36 T7 4
valid_sources_7c 7146 1 T2 45 T4 11 T6 39
valid_sources_7d 7919 1 T2 42 T4 6 T6 35
valid_sources_7e 8203 1 T2 29 T4 1 T6 39
valid_sources_7f 6978 1 T2 33 T4 13 T6 40
valid_sources_80 7280 1 T2 47 T3 5 T4 8



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values_4 all_enables biggest_size 637361 1 T1 19018 T2 5232 T3 67
values_0 all_enables biggest_size 98935 1 T1 346 T2 234 T3 44
values_1 all_enables biggest_size 63734 1 T1 305 T2 216 T3 28

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%