Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}
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Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
0.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 10 0 0.00
Crosses 24 24 0 0.00


Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr_pin 6 6 0 0.00 100 1 1 0
cp_intr_pin_value 4 4 0 0.00 100 1 1 0


Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_intr_pins_all_values 24 24 0 0.00 100 1 1 0


Summary for Variable cp_intr_pin

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 6 0 0.00


User Defined Bins for cp_intr_pin

Uncovered bins
NAMECOUNTAT LEASTNUMBER
all_pins_0 0 1 1
all_pins_1 0 1 1
all_pins_2 0 1 1
all_pins_3 0 1 1
all_pins_4 0 1 1
all_pins_5 0 1 1



Summary for Variable cp_intr_pin_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 4 0 0.00


User Defined Bins for cp_intr_pin_value

Uncovered bins
NAMECOUNTAT LEASTNUMBER
values_0 0 1 1
values_1 0 1 1
transitions:0->1 0 1 1
transitions:1->0 0 1 1



Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 24 24 0 0.00 24


Automatically Generated Cross Bins for cp_intr_pins_all_values

Uncovered bins
cp_intr_pincp_intr_pin_valueCOUNTAT LEASTNUMBER
* * -- -- 24

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%