Group : cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
35.71 35.71 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_cgs_wrap[flash_ctrl_core_reg_block] 35.71 1 100 1 64 64




Group Instance : tl_intg_err_cgs_wrap[flash_ctrl_core_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
35.71 1 100 1 64 64




Summary for Group Instance tl_intg_err_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 14 9 5 35.71


Variables for Group Instance tl_intg_err_cgs_wrap[flash_ctrl_core_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_is_mem 2 0 2 100.00 100 1 1 2
cp_num_cmd_err_bits 4 3 1 25.00 100 1 1 0
cp_num_data_err_bits 4 3 1 25.00 100 1 1 0
cp_tl_intg_err_type 4 3 1 25.00 100 1 1 0


Summary for Variable cp_is_mem

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_is_mem

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2056727 1 T1 38318 T2 10739 T3 190
auto[1] 25335 1 T1 562 T2 324 T3 54



Summary for Variable cp_num_cmd_err_bits

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 3 1 25.00


User Defined Bins for cp_num_cmd_err_bits

Uncovered bins
NAMECOUNTAT LEASTNUMBER
values_1 0 1 1
values_2 0 1 1
values_3 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values_0 2082062 1 T1 38880 T2 11063 T3 244



Summary for Variable cp_num_data_err_bits

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 3 1 25.00


User Defined Bins for cp_num_data_err_bits

Uncovered bins
NAMECOUNTAT LEASTNUMBER
values_1 0 1 1
values_2 0 1 1
values_3 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values_0 2082062 1 T1 38880 T2 11063 T3 244



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 3 1 25.00


Automatically Generated Bins for cp_tl_intg_err_type

Uncovered bins
NAMECOUNTAT LEASTNUMBER
auto_TlIntgErrCmd 0 1 1
auto_TlIntgErrData 0 1 1
auto_TlIntgErrBoth 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto_TlIntgErrNone 2082062 1 T1 38880 T2 11063 T3 244

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