Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
35.29	35.29	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	35.29	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
35.29	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	3	8	72.73
Crosses	40	30	10	25.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	5	0	5	100.00	100	1	1	0
cp_tl_intg_err_type	4	3	1	25.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	40	30	10	25.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values_0	229835	1		T1	7102		T2	1875		T3	16
values_1	740936	1		T1	8329		T2	2351		T3	59
values_2	194622	1		T1	2505		T2	757		T3	21
values_3	115840	1		T1	1275		T2	398		T3	9
values_4	800829	1		T1	19669		T2	5682		T3	139

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	3	1	25.00

Automatically Generated Bins for cp_tl_intg_err_type

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
auto_TlIntgErrCmd	0	1	1
auto_TlIntgErrData	0	1	1
auto_TlIntgErrBoth	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto_TlIntgErrNone	2082062	1		T1	38880		T2	11063		T3	244

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1634347	1		T1	37869		T2	10363		T3	114
auto[1]	447715	1		T1	1011		T2	700		T3	130

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	30	10	25.00	30

Automatically Generated Cross Bins for cr_all

Element holes

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER
[auto_TlIntgErrCmd , auto_TlIntgErrData , auto_TlIntgErrBoth]	*	*	--	--	30

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto_TlIntgErrNone	values_0	auto[0]	228410	1		T1	7102		T2	1875		T3	16
auto_TlIntgErrNone	values_0	auto[1]	1425	1		T16	36		T17	113		T18	81
auto_TlIntgErrNone	values_1	auto[0]	643143	1		T1	8200		T2	2262		T3	27
auto_TlIntgErrNone	values_1	auto[1]	97793	1		T1	129		T2	89		T3	32
auto_TlIntgErrNone	values_2	auto[0]	81301	1		T1	2364		T2	662		T3	3
auto_TlIntgErrNone	values_2	auto[1]	113321	1		T1	141		T2	95		T3	18
auto_TlIntgErrNone	values_3	auto[0]	43978	1		T1	1185		T2	332		T3	1
auto_TlIntgErrNone	values_3	auto[1]	71862	1		T1	90		T2	66		T3	8
auto_TlIntgErrNone	values_4	auto[0]	637515	1		T1	19018		T2	5232		T3	67
auto_TlIntgErrNone	values_4	auto[1]	163314	1		T1	651		T2	450		T3	72