Group : tl_agent_pkg::pending_req_on_rst_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::pending_req_on_rst_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
50.00 50.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_eflash_tl_agent.cov::m_pending_req_on_rst_cg 50.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::m_pending_req_on_rst_cg 50.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_eflash_tl_agent.cov::m_pending_req_on_rst_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_eflash_tl_agent.cov::m_pending_req_on_rst_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_eflash_tl_agent.cov::m_pending_req_on_rst_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_pending 2 1 1 50.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::m_pending_req_on_rst_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::m_pending_req_on_rst_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::m_pending_req_on_rst_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_req_pending 2 1 1 50.00 100 1 1 0


Summary for Variable cp_req_pending

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 1 1 50.00


User Defined Bins for cp_req_pending

Uncovered bins
NAMECOUNTAT LEASTNUMBER
values_1 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values_0 5228 1 T13 2 T14 84 T15 91


Summary for Variable cp_req_pending

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 1 1 50.00


User Defined Bins for cp_req_pending

Uncovered bins
NAMECOUNTAT LEASTNUMBER
values_1 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values_0 5228 1 T13 2 T14 84 T15 91

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