Unified Coverage Report :: Module :: prim_generic_flash_bank

Module : prim_generic_flash_bank

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.46	99.29	77.78		61.54	95.24

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank	83.46	99.29	77.78		61.54	95.24
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank	83.46	99.29	77.78		61.54	95.24

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.46	99.29	77.78		61.54	95.24

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
76.86	83.26	86.67		61.54	81.40	71.43

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	83.33				100.00		gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_info_types[0].u_info_mem	32.54	14.29				33.33	50.00
gen_info_types[0].u_info_mem_meta	32.54	14.29				33.33	50.00
gen_info_types[1].u_info_mem	32.54	14.29				33.33	50.00
gen_info_types[1].u_info_mem_meta	32.54	14.29				33.33	50.00
gen_info_types[2].u_info_mem	32.54	14.29				33.33	50.00
gen_info_types[2].u_info_mem_meta	32.54	14.29				33.33	50.00
u_cmd_fifo	97.50	100.00	100.00			90.00	100.00
u_mem	95.24	85.71				100.00	100.00
u_mem_meta	95.24	85.71				100.00	100.00

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.46	99.29	77.78		61.54	95.24

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
76.86	83.26	86.67		61.54	81.40	71.43

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	83.33				100.00		gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_info_types[0].u_info_mem	32.54	14.29				33.33	50.00
gen_info_types[0].u_info_mem_meta	32.54	14.29				33.33	50.00
gen_info_types[1].u_info_mem	32.54	14.29				33.33	50.00
gen_info_types[1].u_info_mem_meta	32.54	14.29				33.33	50.00
gen_info_types[2].u_info_mem	32.54	14.29				33.33	50.00
gen_info_types[2].u_info_mem_meta	32.54	14.29				33.33	50.00
u_cmd_fifo	97.50	100.00	100.00			90.00	100.00
u_mem	95.24	85.71				100.00	100.00
u_mem_meta	95.24	85.71				100.00	100.00

Line Coverage for Module : prim_generic_flash_bank

	Line No.	Total	Covered	Percent
TOTAL		141	140	99.29
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
ALWAYS	164	3	3	100.00
ALWAYS	169	9	9	100.00
ALWAYS	185	4	4	100.00
ALWAYS	196	6	6	100.00
CONT_ASSIGN	207	1	1	100.00
ALWAYS	215	13	12	92.31
ALWAYS	230	85	85	100.00
CONT_ASSIGN	381	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	457	1	1	100.00
CONT_ASSIGN	458	1	1	100.00
CONT_ASSIGN	461	1	1	100.00
CONT_ASSIGN	464	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv' or '../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
128	1	1
129	1	1
150	1	1
151	1	1
152	1	1
153	1	1
156	1	1
157	1	1
158	1	1
159	1	1
161	1	1
164	2	2
165	1	1
169	1	1
170	1	1
171	1	1
172	1	1
173	1	1
175	1	1
176	1	1
177	1	1
178	1	1
185	1	1
186	1	1
187	1	1
188	1	1
			MISSING_ELSE
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
			MISSING_ELSE
207	1	1
215	1	1
216	1	1
217	1	1
219	2	2
220	1	2
221	2	2
			MISSING_ELSE
223	2	2
224	2	2
			MISSING_ELSE
230	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
246	1	1
247	1	1
248	1	1
250	1	1
252	1	1
253	1	1
254	1	1
			MISSING_ELSE
260	1	1
261	1	1
262	1	1
263	1	1
265	1	1
266	1	1
271	1	1
272	1	1
273	1	1
274	1	1
275	1	1
276	1	1
277	1	1
278	1	1
279	1	1
280	1	1
281	1	1
282	1	1
283	1	1
284	1	1
285	1	1
286	1	1
287	1	1
			MISSING_ELSE
292	1	1
293	1	1
295	1	1
296	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
305	1	1
306	1	1
309	1	1
311	1	1
312	1	1
313	1	1
			MISSING_ELSE
319	1	1
320	1	1
321	1	1
322	1	1
323	1	1
325	1	1
326	1	1
327	1	1
328	1	1
334	1	1
335	1	1
336	1	1
337	1	1
338	1	1
339	1	1
340	1	1
341	1	1
342	1	1
343	1	1
344	1	1
345	1	1
347	1	1
348	1	1
349	1	1
350	1	1
351	1	1
361	1	1
362	1	1
			MISSING_ELSE
381	1	1
420	3	3
456	1	1
457	1	1
458	1	1
461	1	1
464	1	1

---

Cond Coverage for Module : prim_generic_flash_bank

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       253
 EXPRESSION (init_i && flash_power_ready_h_i && ((!flash_power_down_h_i)))
             ---1--    ----------2----------    ------------3------------

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Unreachable
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       340
 EXPRESSION ((index_cnt < index_limit_q) || (time_cnt < time_limit_q))
             -------------1-------------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Not Covered
1	0	Covered	T1,T2,T6

 LINE       361
 EXPRESSION (((!flash_power_ready_h_i)) || flash_power_down_h_i)
             -------------1------------    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       458
 EXPRESSION ((rd_part_q == FlashPartData) ? rd_data_main : rd_data_info)
             --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

FSM Coverage for Module : prim_generic_flash_bank

Summary for FSM :: st_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	13	8	61.54
Sequences	0	0

State, Transition and Sequence Details for FSM :: st_q

---

states	Line No.	Covered	Tests
StErase	281	Covered	T1,T2,T6
StIdle	265	Covered	T1,T2,T3
StInit	254	Covered	T1,T2,T3
StProg	313	Covered	T1,T2,T3
StRead	275	Covered	T1,T2,T3
StReset	164	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StErase->StIdle	335	Covered	T1,T2,T6
StErase->StReset	164	Not Covered
StIdle->StErase	281	Covered	T1,T2,T6
StIdle->StRead	275	Covered	T1,T2,T3
StIdle->StReset	164	Not Covered
StInit->StIdle	265	Covered	T1,T2,T3
StInit->StReset	164	Not Covered
StProg->StIdle	325	Covered	T1,T2,T3
StProg->StReset	164	Not Covered
StRead->StIdle	306	Covered	T1,T2,T3
StRead->StProg	313	Covered	T1,T2,T3
StRead->StReset	164	Not Covered
StReset->StInit	254	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_generic_flash_bank

	Line No.	Total	Covered	Percent
Branches		42	40	95.24
TERNARY	458	2	1	50.00
IF	164	2	2	100.00
IF	169	2	2	100.00
IF	185	3	3	100.00
IF	196	3	3	100.00
IF	215	8	7	87.50
CASE	250	20	20	100.00
IF	361	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv' or '../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	458	((rd_part_q == FlashPartData)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	169	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	185	if ((!rst_ni))
-2-:	187	if (mem_rd_q)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	196	if ((!rst_ni))
-2-:	199	if (mem_rd_d)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	215	if ((!rst_ni))
-2-:	219	if (time_cnt_inc)
-3-:	220	if (time_cnt_set1)
-4-:	221	if (time_cnt_clr)
-5-:	223	if (index_cnt_inc)
-6-:	224	if (index_cnt_clr)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	-	Covered	T1,T2,T3
0	0	1	-	-	-	Not Covered
0	0	0	1	-	-	Covered	T1,T2,T3
0	0	0	0	-	-	Covered	T1,T2,T3
0	-	-	-	1	-	Covered	T1,T2,T3
0	-	-	-	0	1	Covered	T1,T2,T3
0	-	-	-	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	250	case (st_q)
-2-:	253	if (((init_i && flash_power_ready_h_i) && (!flash_power_down_h_i)))
-3-:	261	if ((index_cnt < InitCycles))
-4-:	271	if (rd_req)
-5-:	276	if (prog_req)
-6-:	280	if (pg_erase_req)
-7-:	284	if (bk_erase_req)
-8-:	292	if ((time_cnt < ReadCycles))
-9-:	295	if ((!prog_pend_q))
-10-:	299	if (rd_req)
-11-:	309	if (prog_pend_q)
-12-:	320	if ((time_cnt < ProgCycles))
-13-:	334	if (erase_suspend_req_i)
-14-:	340	if (((index_cnt < index_limit_q) || (time_cnt < time_limit_q)))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
StReset	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StReset	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StInit	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StInit	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	-	-	0	0	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	-	-	0	0	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
StRead	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T2,T3
StRead	-	-	-	-	-	-	0	1	1	-	-	-	-	Covered	T1,T2,T3
StRead	-	-	-	-	-	-	0	1	0	-	-	-	-	Covered	T1,T2,T3
StRead	-	-	-	-	-	-	0	0	-	1	-	-	-	Covered	T1,T2,T3
StRead	-	-	-	-	-	-	0	0	-	0	-	-	-	Covered	T1,T2,T3
StProg	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T1,T2,T3
StProg	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
StErase	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T2,T3
StErase	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T2,T3
StErase	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	361	if (((!flash_power_ready_h_i) || flash_power_down_h_i))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank

	Line No.	Total	Covered	Percent
TOTAL		141	140	99.29
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
ALWAYS	164	3	3	100.00
ALWAYS	169	9	9	100.00
ALWAYS	185	4	4	100.00
ALWAYS	196	6	6	100.00
CONT_ASSIGN	207	1	1	100.00
ALWAYS	215	13	12	92.31
ALWAYS	230	85	85	100.00
CONT_ASSIGN	381	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	457	1	1	100.00
CONT_ASSIGN	458	1	1	100.00
CONT_ASSIGN	461	1	1	100.00
CONT_ASSIGN	464	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv' or '../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
128	1	1
129	1	1
150	1	1
151	1	1
152	1	1
153	1	1
156	1	1
157	1	1
158	1	1
159	1	1
161	1	1
164	2	2
165	1	1
169	1	1
170	1	1
171	1	1
172	1	1
173	1	1
175	1	1
176	1	1
177	1	1
178	1	1
185	1	1
186	1	1
187	1	1
188	1	1
			MISSING_ELSE
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
			MISSING_ELSE
207	1	1
215	1	1
216	1	1
217	1	1
219	2	2
220	1	2
221	2	2
			MISSING_ELSE
223	2	2
224	2	2
			MISSING_ELSE
230	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
246	1	1
247	1	1
248	1	1
250	1	1
252	1	1
253	1	1
254	1	1
			MISSING_ELSE
260	1	1
261	1	1
262	1	1
263	1	1
265	1	1
266	1	1
271	1	1
272	1	1
273	1	1
274	1	1
275	1	1
276	1	1
277	1	1
278	1	1
279	1	1
280	1	1
281	1	1
282	1	1
283	1	1
284	1	1
285	1	1
286	1	1
287	1	1
			MISSING_ELSE
292	1	1
293	1	1
295	1	1
296	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
305	1	1
306	1	1
309	1	1
311	1	1
312	1	1
313	1	1
			MISSING_ELSE
319	1	1
320	1	1
321	1	1
322	1	1
323	1	1
325	1	1
326	1	1
327	1	1
328	1	1
334	1	1
335	1	1
336	1	1
337	1	1
338	1	1
339	1	1
340	1	1
341	1	1
342	1	1
343	1	1
344	1	1
345	1	1
347	1	1
348	1	1
349	1	1
350	1	1
351	1	1
361	1	1
362	1	1
			MISSING_ELSE
381	1	1
420	3	3
456	1	1
457	1	1
458	1	1
461	1	1
464	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       253
 EXPRESSION (init_i && flash_power_ready_h_i && ((!flash_power_down_h_i)))
             ---1--    ----------2----------    ------------3------------

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Unreachable
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       340
 EXPRESSION ((index_cnt < index_limit_q) || (time_cnt < time_limit_q))
             -------------1-------------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T24,T25
0	1	Not Covered
1	0	Covered	T2,T24,T25

 LINE       361
 EXPRESSION (((!flash_power_ready_h_i)) || flash_power_down_h_i)
             -------------1------------    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       458
 EXPRESSION ((rd_part_q == FlashPartData) ? rd_data_main : rd_data_info)
             --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank

Summary for FSM :: st_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	13	8	61.54
Sequences	0	0

State, Transition and Sequence Details for FSM :: st_q

---

states	Line No.	Covered	Tests
StErase	281	Covered	T2,T24,T25
StIdle	265	Covered	T1,T2,T3
StInit	254	Covered	T1,T2,T3
StProg	313	Covered	T1,T2,T3
StRead	275	Covered	T1,T2,T3
StReset	164	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StErase->StIdle	335	Covered	T2,T24,T25
StErase->StReset	164	Not Covered
StIdle->StErase	281	Covered	T2,T24,T25
StIdle->StRead	275	Covered	T1,T2,T3
StIdle->StReset	164	Not Covered
StInit->StIdle	265	Covered	T1,T2,T3
StInit->StReset	164	Not Covered
StProg->StIdle	325	Covered	T1,T2,T3
StProg->StReset	164	Not Covered
StRead->StIdle	306	Covered	T1,T2,T3
StRead->StProg	313	Covered	T1,T2,T3
StRead->StReset	164	Not Covered
StReset->StInit	254	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank

	Line No.	Total	Covered	Percent
Branches		42	40	95.24
TERNARY	458	2	1	50.00
IF	164	2	2	100.00
IF	169	2	2	100.00
IF	185	3	3	100.00
IF	196	3	3	100.00
IF	215	8	7	87.50
CASE	250	20	20	100.00
IF	361	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv' or '../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	458	((rd_part_q == FlashPartData)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	169	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	185	if ((!rst_ni))
-2-:	187	if (mem_rd_q)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	196	if ((!rst_ni))
-2-:	199	if (mem_rd_d)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	215	if ((!rst_ni))
-2-:	219	if (time_cnt_inc)
-3-:	220	if (time_cnt_set1)
-4-:	221	if (time_cnt_clr)
-5-:	223	if (index_cnt_inc)
-6-:	224	if (index_cnt_clr)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	-	Covered	T1,T2,T3
0	0	1	-	-	-	Not Covered
0	0	0	1	-	-	Covered	T1,T2,T3
0	0	0	0	-	-	Covered	T1,T2,T3
0	-	-	-	1	-	Covered	T1,T2,T3
0	-	-	-	0	1	Covered	T1,T2,T3
0	-	-	-	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	250	case (st_q)
-2-:	253	if (((init_i && flash_power_ready_h_i) && (!flash_power_down_h_i)))
-3-:	261	if ((index_cnt < InitCycles))
-4-:	271	if (rd_req)
-5-:	276	if (prog_req)
-6-:	280	if (pg_erase_req)
-7-:	284	if (bk_erase_req)
-8-:	292	if ((time_cnt < ReadCycles))
-9-:	295	if ((!prog_pend_q))
-10-:	299	if (rd_req)
-11-:	309	if (prog_pend_q)
-12-:	320	if ((time_cnt < ProgCycles))
-13-:	334	if (erase_suspend_req_i)
-14-:	340	if (((index_cnt < index_limit_q) || (time_cnt < time_limit_q)))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
StReset	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StReset	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StInit	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StInit	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	-	-	0	0	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	-	-	0	0	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
StRead	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T2,T3
StRead	-	-	-	-	-	-	0	1	1	-	-	-	-	Covered	T1,T2,T3
StRead	-	-	-	-	-	-	0	1	0	-	-	-	-	Covered	T1,T2,T3
StRead	-	-	-	-	-	-	0	0	-	1	-	-	-	Covered	T1,T2,T3
StRead	-	-	-	-	-	-	0	0	-	0	-	-	-	Covered	T1,T2,T3
StProg	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T1,T2,T3
StProg	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
StErase	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T2,T3
StErase	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T2,T3
StErase	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	361	if (((!flash_power_ready_h_i) || flash_power_down_h_i))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank

	Line No.	Total	Covered	Percent
TOTAL		141	140	99.29
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
ALWAYS	164	3	3	100.00
ALWAYS	169	9	9	100.00
ALWAYS	185	4	4	100.00
ALWAYS	196	6	6	100.00
CONT_ASSIGN	207	1	1	100.00
ALWAYS	215	13	12	92.31
ALWAYS	230	85	85	100.00
CONT_ASSIGN	381	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	457	1	1	100.00
CONT_ASSIGN	458	1	1	100.00
CONT_ASSIGN	461	1	1	100.00
CONT_ASSIGN	464	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv' or '../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
128	1	1
129	1	1
150	1	1
151	1	1
152	1	1
153	1	1
156	1	1
157	1	1
158	1	1
159	1	1
161	1	1
164	2	2
165	1	1
169	1	1
170	1	1
171	1	1
172	1	1
173	1	1
175	1	1
176	1	1
177	1	1
178	1	1
185	1	1
186	1	1
187	1	1
188	1	1
			MISSING_ELSE
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
			MISSING_ELSE
207	1	1
215	1	1
216	1	1
217	1	1
219	2	2
220	1	2
221	2	2
			MISSING_ELSE
223	2	2
224	2	2
			MISSING_ELSE
230	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
246	1	1
247	1	1
248	1	1
250	1	1
252	1	1
253	1	1
254	1	1
			MISSING_ELSE
260	1	1
261	1	1
262	1	1
263	1	1
265	1	1
266	1	1
271	1	1
272	1	1
273	1	1
274	1	1
275	1	1
276	1	1
277	1	1
278	1	1
279	1	1
280	1	1
281	1	1
282	1	1
283	1	1
284	1	1
285	1	1
286	1	1
287	1	1
			MISSING_ELSE
292	1	1
293	1	1
295	1	1
296	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
305	1	1
306	1	1
309	1	1
311	1	1
312	1	1
313	1	1
			MISSING_ELSE
319	1	1
320	1	1
321	1	1
322	1	1
323	1	1
325	1	1
326	1	1
327	1	1
328	1	1
334	1	1
335	1	1
336	1	1
337	1	1
338	1	1
339	1	1
340	1	1
341	1	1
342	1	1
343	1	1
344	1	1
345	1	1
347	1	1
348	1	1
349	1	1
350	1	1
351	1	1
361	1	1
362	1	1
			MISSING_ELSE
381	1	1
420	3	3
456	1	1
457	1	1
458	1	1
461	1	1
464	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       253
 EXPRESSION (init_i && flash_power_ready_h_i && ((!flash_power_down_h_i)))
             ---1--    ----------2----------    ------------3------------

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Unreachable
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       340
 EXPRESSION ((index_cnt < index_limit_q) || (time_cnt < time_limit_q))
             -------------1-------------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T10
0	1	Not Covered
1	0	Covered	T1,T6,T10

 LINE       361
 EXPRESSION (((!flash_power_ready_h_i)) || flash_power_down_h_i)
             -------------1------------    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       458
 EXPRESSION ((rd_part_q == FlashPartData) ? rd_data_main : rd_data_info)
             --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank

Summary for FSM :: st_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	13	8	61.54
Sequences	0	0

State, Transition and Sequence Details for FSM :: st_q

---

states	Line No.	Covered	Tests
StErase	281	Covered	T1,T6,T10
StIdle	265	Covered	T1,T2,T3
StInit	254	Covered	T1,T2,T3
StProg	313	Covered	T1,T2,T4
StRead	275	Covered	T1,T2,T4
StReset	164	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StErase->StIdle	335	Covered	T1,T6,T10
StErase->StReset	164	Not Covered
StIdle->StErase	281	Covered	T1,T6,T10
StIdle->StRead	275	Covered	T1,T2,T4
StIdle->StReset	164	Not Covered
StInit->StIdle	265	Covered	T1,T2,T3
StInit->StReset	164	Not Covered
StProg->StIdle	325	Covered	T1,T2,T4
StProg->StReset	164	Not Covered
StRead->StIdle	306	Covered	T1,T2,T4
StRead->StProg	313	Covered	T1,T2,T4
StRead->StReset	164	Not Covered
StReset->StInit	254	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank

	Line No.	Total	Covered	Percent
Branches		42	40	95.24
TERNARY	458	2	1	50.00
IF	164	2	2	100.00
IF	169	2	2	100.00
IF	185	3	3	100.00
IF	196	3	3	100.00
IF	215	8	7	87.50
CASE	250	20	20	100.00
IF	361	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv' or '../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	458	((rd_part_q == FlashPartData)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	169	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	185	if ((!rst_ni))
-2-:	187	if (mem_rd_q)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	196	if ((!rst_ni))
-2-:	199	if (mem_rd_d)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	215	if ((!rst_ni))
-2-:	219	if (time_cnt_inc)
-3-:	220	if (time_cnt_set1)
-4-:	221	if (time_cnt_clr)
-5-:	223	if (index_cnt_inc)
-6-:	224	if (index_cnt_clr)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	-	Covered	T1,T2,T4
0	0	1	-	-	-	Not Covered
0	0	0	1	-	-	Covered	T1,T2,T4
0	0	0	0	-	-	Covered	T1,T2,T3
0	-	-	-	1	-	Covered	T1,T2,T3
0	-	-	-	0	1	Covered	T1,T2,T3
0	-	-	-	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	250	case (st_q)
-2-:	253	if (((init_i && flash_power_ready_h_i) && (!flash_power_down_h_i)))
-3-:	261	if ((index_cnt < InitCycles))
-4-:	271	if (rd_req)
-5-:	276	if (prog_req)
-6-:	280	if (pg_erase_req)
-7-:	284	if (bk_erase_req)
-8-:	292	if ((time_cnt < ReadCycles))
-9-:	295	if ((!prog_pend_q))
-10-:	299	if (rd_req)
-11-:	309	if (prog_pend_q)
-12-:	320	if ((time_cnt < ProgCycles))
-13-:	334	if (erase_suspend_req_i)
-14-:	340	if (((index_cnt < index_limit_q) || (time_cnt < time_limit_q)))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
StReset	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StReset	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StInit	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StInit	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	-	-	0	0	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	-	-	0	0	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
StRead	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T2,T3
StRead	-	-	-	-	-	-	0	1	1	-	-	-	-	Covered	T1,T2,T3
StRead	-	-	-	-	-	-	0	1	0	-	-	-	-	Covered	T1,T2,T3
StRead	-	-	-	-	-	-	0	0	-	1	-	-	-	Covered	T1,T2,T3
StRead	-	-	-	-	-	-	0	0	-	0	-	-	-	Covered	T1,T2,T3
StProg	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T1,T2,T3
StProg	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
StErase	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T2,T3
StErase	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T2,T3
StErase	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	361	if (((!flash_power_ready_h_i) || flash_power_down_h_i))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3