Unified Coverage Report :: Module :: flash_ctrl_info_cfg

Module : flash_ctrl_info_cfg

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg	100.00						100.00
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg	100.00	100.00					100.00
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg	100.00	100.00					100.00
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg	100.00	100.00					100.00
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg	100.00	100.00					100.00
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg	100.00	100.00					100.00

---

Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
52.48	52.48						u_region_cfg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
52.48	52.48						u_region_cfg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
52.48	52.48						u_region_cfg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
52.48	52.48						u_region_cfg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
52.48	52.48						u_region_cfg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
52.48	52.48						u_region_cfg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : flash_ctrl_info_cfg ( parameter Bank=0,InfoSel=1 + Bank=1,InfoSel=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg

SCORE	LINE
100.00	100.00

tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	51	0	0
CONT_ASSIGN	51	0	0
CONT_ASSIGN	51	0	0
CONT_ASSIGN	51	0	0
CONT_ASSIGN	51	0	0
CONT_ASSIGN	51	0	0
CONT_ASSIGN	51	0	0
CONT_ASSIGN	51	0	0
CONT_ASSIGN	74	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
51		unreachable
74	1	1

---

Line Coverage for Module : flash_ctrl_info_cfg ( parameter Bank=0,InfoSel=2 + Bank=1,InfoSel=2 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg

SCORE	LINE
100.00	100.00

tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	51	0	0
CONT_ASSIGN	51	0	0
CONT_ASSIGN	51	0	0
CONT_ASSIGN	51	0	0
CONT_ASSIGN	51	0	0
CONT_ASSIGN	51	0	0
CONT_ASSIGN	51	0	0
CONT_ASSIGN	74	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
51		unreachable
74	1	1

---

Line Coverage for Module : flash_ctrl_info_cfg ( parameter Bank=1,InfoSel=0 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	74	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
74	1	1

---

Assert Coverage for Module : flash_ctrl_info_cfg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
InfoNoBiggerThanData_A	330	330	0	0

InfoNoBiggerThanData_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	330	330	0	0
T1	6	6	0	0
T2	6	6	0	0
T3	6	6	0	0
T4	6	6	0	0
T5	6	6	0	0
T6	6	6	0	0
T7	6	6	0	0
T8	6	6	0	0
T9	6	6	0	0
T10	6	6	0	0

Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
InfoNoBiggerThanData_A	55	55	0	0

InfoNoBiggerThanData_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55	55	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	51	0	0
CONT_ASSIGN	51	0	0
CONT_ASSIGN	51	0	0
CONT_ASSIGN	51	0	0
CONT_ASSIGN	51	0	0
CONT_ASSIGN	51	0	0
CONT_ASSIGN	51	0	0
CONT_ASSIGN	51	0	0
CONT_ASSIGN	74	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
51		unreachable
74	1	1

---

Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
InfoNoBiggerThanData_A	55	55	0	0

InfoNoBiggerThanData_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55	55	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	51	0	0
CONT_ASSIGN	51	0	0
CONT_ASSIGN	51	0	0
CONT_ASSIGN	51	0	0
CONT_ASSIGN	51	0	0
CONT_ASSIGN	51	0	0
CONT_ASSIGN	51	0	0
CONT_ASSIGN	74	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
51		unreachable
74	1	1

---

Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
InfoNoBiggerThanData_A	55	55	0	0

InfoNoBiggerThanData_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55	55	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	74	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
74	1	1

---

Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
InfoNoBiggerThanData_A	55	55	0	0

InfoNoBiggerThanData_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55	55	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	51	0	0
CONT_ASSIGN	51	0	0
CONT_ASSIGN	51	0	0
CONT_ASSIGN	51	0	0
CONT_ASSIGN	51	0	0
CONT_ASSIGN	51	0	0
CONT_ASSIGN	51	0	0
CONT_ASSIGN	51	0	0
CONT_ASSIGN	74	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
51		unreachable
74	1	1

---

Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
InfoNoBiggerThanData_A	55	55	0	0

InfoNoBiggerThanData_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55	55	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	51	0	0
CONT_ASSIGN	51	0	0
CONT_ASSIGN	51	0	0
CONT_ASSIGN	51	0	0
CONT_ASSIGN	51	0	0
CONT_ASSIGN	51	0	0
CONT_ASSIGN	51	0	0
CONT_ASSIGN	74	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
51		unreachable
74	1	1

---

Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
InfoNoBiggerThanData_A	55	55	0	0

InfoNoBiggerThanData_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55	55	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0