Line Coverage for Module :
flash_phy_prog
| Line No. | Total | Covered | Percent |
TOTAL | | 86 | 81 | 94.19 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 87 | 1 | 1 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
ALWAYS | 91 | 6 | 6 | 100.00 |
ALWAYS | 103 | 3 | 3 | 100.00 |
ALWAYS | 118 | 47 | 47 | 100.00 |
ALWAYS | 229 | 12 | 9 | 75.00 |
CONT_ASSIGN | 244 | 1 | 1 | 100.00 |
ALWAYS | 253 | 4 | 4 | 100.00 |
CONT_ASSIGN | 261 | 1 | 1 | 100.00 |
CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
CONT_ASSIGN | 288 | 1 | 1 | 100.00 |
CONT_ASSIGN | 298 | 1 | 1 | 100.00 |
ALWAYS | 300 | 6 | 4 | 66.67 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
84 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
91 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
95 |
1 |
1 |
96 |
1 |
1 |
98 |
1 |
1 |
|
|
|
MISSING_ELSE |
103 |
1 |
1 |
104 |
1 |
1 |
106 |
1 |
1 |
118 |
1 |
1 |
120 |
1 |
1 |
121 |
1 |
1 |
122 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
126 |
1 |
1 |
127 |
1 |
1 |
129 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
141 |
1 |
1 |
142 |
1 |
1 |
143 |
1 |
1 |
|
|
|
MISSING_ELSE |
148 |
1 |
1 |
149 |
1 |
1 |
151 |
1 |
1 |
153 |
1 |
1 |
154 |
1 |
1 |
156 |
1 |
1 |
157 |
1 |
1 |
158 |
1 |
1 |
|
|
|
MISSING_ELSE |
164 |
1 |
1 |
165 |
1 |
1 |
168 |
1 |
1 |
169 |
1 |
1 |
|
|
|
MISSING_ELSE |
174 |
1 |
1 |
175 |
1 |
1 |
179 |
1 |
1 |
181 |
1 |
1 |
182 |
1 |
1 |
|
|
|
MISSING_ELSE |
187 |
1 |
1 |
189 |
1 |
1 |
190 |
1 |
1 |
|
|
|
MISSING_ELSE |
195 |
1 |
1 |
199 |
1 |
1 |
200 |
1 |
1 |
206 |
1 |
1 |
207 |
1 |
1 |
209 |
1 |
1 |
210 |
1 |
1 |
216 |
1 |
1 |
217 |
1 |
1 |
218 |
1 |
1 |
|
|
|
MISSING_ELSE |
229 |
1 |
1 |
230 |
1 |
1 |
231 |
1 |
1 |
232 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
235 |
0 |
1 |
236 |
0 |
1 |
237 |
1 |
1 |
238 |
0 |
1 |
239 |
1 |
1 |
240 |
1 |
1 |
|
|
|
MISSING_ELSE |
244 |
1 |
1 |
253 |
1 |
1 |
254 |
1 |
1 |
255 |
1 |
1 |
256 |
1 |
1 |
|
|
|
MISSING_ELSE |
261 |
1 |
1 |
285 |
1 |
1 |
288 |
1 |
1 |
298 |
1 |
1 |
300 |
1 |
1 |
301 |
1 |
1 |
302 |
1 |
1 |
303 |
0 |
1 |
304 |
1 |
1 |
305 |
0 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Module :
flash_phy_prog
| Total | Covered | Percent |
Conditions | 37 | 27 | 72.97 |
Logical | 37 | 27 | 72.97 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 84
EXPRESSION ((data_sel == Actual) ? data_i : ({flash_phy_pkg::BusWidth {1'b1}}))
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 88
EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 93
EXPRESSION (pack_valid && (idx == MaxIdx))
-----1---- -------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 132
EXPRESSION (req_i && ((|sel_i)))
--1-- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 151
EXPRESSION (req_i && (idx == MaxIdx))
--1-- -------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 154
EXPRESSION (req_i && last_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 175
EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 207
EXPRESSION (ack_i ? StWaitFlash : StReqFlash)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 210
EXPRESSION (ack_i ? StIdle : StReqFlash)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 232
EXPRESSION (req_o && ack_i)
--1-- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 234
EXPRESSION (calc_req_o && calc_ack_i)
-----1---- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 237
EXPRESSION (scramble_req_o && scramble_ack_i)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 288
EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 298
EXPRESSION (req_i && ack_o && last_i)
--1-- --2-- ---3--
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
FSM Coverage for Module :
flash_phy_prog
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
10 |
7 |
70.00 |
(Not included in score) |
Transitions |
21 |
10 |
47.62 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
StCalcEcc |
190 |
Not Covered |
|
StCalcMask |
175 |
Not Covered |
|
StCalcPlainEcc |
153 |
Covered |
T1,T2,T3 |
StIdle |
104 |
Covered |
T1,T2,T3 |
StPackData |
135 |
Covered |
T1,T2,T3 |
StPostPack |
156 |
Covered |
T1,T2,T3 |
StPrePack |
133 |
Covered |
T1,T2,T3 |
StReqFlash |
175 |
Covered |
T1,T2,T3 |
StScrambleData |
182 |
Not Covered |
|
StWaitFlash |
207 |
Covered |
T1,T2,T3 |
transitions | Line No. | Covered | Tests |
StCalcEcc->StIdle |
104 |
Not Covered |
|
StCalcEcc->StReqFlash |
195 |
Not Covered |
|
StCalcMask->StIdle |
104 |
Not Covered |
|
StCalcMask->StScrambleData |
182 |
Not Covered |
|
StCalcPlainEcc->StCalcMask |
175 |
Not Covered |
|
StCalcPlainEcc->StIdle |
104 |
Not Covered |
|
StCalcPlainEcc->StReqFlash |
175 |
Covered |
T1,T2,T3 |
StIdle->StPackData |
135 |
Covered |
T1,T2,T3 |
StIdle->StPrePack |
133 |
Covered |
T1,T2,T3 |
StPackData->StCalcPlainEcc |
153 |
Covered |
T1,T2,T3 |
StPackData->StIdle |
104 |
Not Covered |
|
StPackData->StPostPack |
156 |
Covered |
T1,T2,T3 |
StPostPack->StCalcPlainEcc |
169 |
Covered |
T1,T2,T3 |
StPostPack->StIdle |
104 |
Not Covered |
|
StPrePack->StIdle |
104 |
Not Covered |
|
StPrePack->StPackData |
143 |
Covered |
T1,T2,T3 |
StReqFlash->StIdle |
104 |
Covered |
T1,T2,T3 |
StReqFlash->StWaitFlash |
207 |
Covered |
T1,T2,T3 |
StScrambleData->StCalcEcc |
190 |
Not Covered |
|
StScrambleData->StIdle |
104 |
Not Covered |
|
StWaitFlash->StIdle |
104 |
Covered |
T1,T2,T3 |
Branch Coverage for Module :
flash_phy_prog
| Line No. | Total | Covered | Percent |
Branches |
|
50 |
44 |
88.00 |
TERNARY |
84 |
2 |
2 |
100.00 |
TERNARY |
88 |
2 |
2 |
100.00 |
TERNARY |
288 |
2 |
1 |
50.00 |
IF |
91 |
4 |
4 |
100.00 |
IF |
103 |
2 |
2 |
100.00 |
CASE |
129 |
25 |
24 |
96.00 |
IF |
229 |
6 |
4 |
66.67 |
IF |
253 |
3 |
3 |
100.00 |
IF |
300 |
4 |
2 |
50.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 84 ((data_sel == Actual)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 88 ((idx > '0)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 288 (ecc_i) ?
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 91 if ((!rst_ni))
-2-: 93 if ((pack_valid && (idx == MaxIdx)))
-3-: 96 if (pack_valid)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 103 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 129 case (state_q)
-2-: 132 if ((req_i && (|sel_i)))
-3-: 134 if (req_i)
-4-: 142 if ((idx == align_next))
-5-: 151 if ((req_i && (idx == MaxIdx)))
-6-: 154 if ((req_i && last_i))
-7-: 157 if (req_i)
-8-: 168 if ((idx == MaxIdx))
-9-: 175 (scramble_i) ?
-10-: 181 if (calc_ack_i)
-11-: 189 if (scramble_ack_i)
-12-: 206 if (last_i)
-13-: 207 (ack_i) ?
-14-: 210 (ack_i) ?
-15-: 216 if (done_i)
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | -15- | Status | Tests |
StIdle |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StIdle |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StIdle |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StPrePack |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StPrePack |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StPackData |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StPackData |
- |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StPackData |
- |
- |
- |
0 |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StPackData |
- |
- |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StPostPack |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StPostPack |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StCalcPlainEcc |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
Not Covered |
|
StCalcPlainEcc |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StCalcMask |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StCalcMask |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StScrambleData |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StScrambleData |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StCalcEcc |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StReqFlash |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
Covered |
T1,T2,T3 |
StReqFlash |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
Covered |
T1,T2,T3 |
StReqFlash |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
1 |
- |
Covered |
T1,T2,T3 |
StReqFlash |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
0 |
- |
Covered |
T1,T2,T3 |
StWaitFlash |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T1,T2,T3 |
StWaitFlash |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T1,T2,T3 |
default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 229 if ((!rst_ni))
-2-: 232 if ((req_o && ack_i))
-3-: 234 if ((calc_req_o && calc_ack_i))
-4-: 237 if ((scramble_req_o && scramble_ack_i))
-5-: 239 if (pack_valid)
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
- |
- |
Not Covered |
|
0 |
0 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 253 if ((!rst_ni))
-2-: 255 if (plain_ecc_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 300 if (rst_ni)
-2-: 302 if (txn_done)
-3-: 304 if (done_i)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
1 |
Not Covered |
|
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
flash_phy_prog
Assertion Details
OneDonePerTxn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
4579462 |
1063 |
0 |
0 |
T1 |
156764 |
36 |
0 |
0 |
T2 |
155332 |
28 |
0 |
0 |
T3 |
3084 |
5 |
0 |
0 |
T4 |
11226 |
13 |
0 |
0 |
T5 |
3118 |
10 |
0 |
0 |
T6 |
70494 |
13 |
0 |
0 |
T7 |
19784 |
13 |
0 |
0 |
T8 |
27716 |
23 |
0 |
0 |
T9 |
35604 |
41 |
0 |
0 |
T10 |
67480 |
1 |
0 |
0 |
T11 |
422264 |
15 |
0 |
0 |
T12 |
27718 |
42 |
0 |
0 |
PostPackRule_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
4579462 |
591 |
0 |
0 |
T1 |
156764 |
15 |
0 |
0 |
T2 |
155332 |
18 |
0 |
0 |
T3 |
3084 |
2 |
0 |
0 |
T4 |
11226 |
9 |
0 |
0 |
T5 |
3118 |
3 |
0 |
0 |
T6 |
70494 |
5 |
0 |
0 |
T7 |
19784 |
7 |
0 |
0 |
T8 |
27716 |
12 |
0 |
0 |
T9 |
35604 |
19 |
0 |
0 |
T11 |
422264 |
10 |
0 |
0 |
T12 |
27718 |
24 |
0 |
0 |
T27 |
10238 |
14 |
0 |
0 |
PrePackRule_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
4579462 |
450 |
0 |
0 |
T1 |
156764 |
13 |
0 |
0 |
T2 |
77666 |
14 |
0 |
0 |
T3 |
3084 |
2 |
0 |
0 |
T4 |
5613 |
4 |
0 |
0 |
T5 |
3118 |
7 |
0 |
0 |
T6 |
70494 |
8 |
0 |
0 |
T7 |
19784 |
7 |
0 |
0 |
T8 |
27716 |
9 |
0 |
0 |
T9 |
35604 |
22 |
0 |
0 |
T11 |
422264 |
8 |
0 |
0 |
T12 |
27718 |
19 |
0 |
0 |
T25 |
5060 |
1 |
0 |
0 |
T27 |
10238 |
4 |
0 |
0 |
T28 |
14131 |
11 |
0 |
0 |
WidthCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
110 |
110 |
0 |
0 |
T1 |
2 |
2 |
0 |
0 |
T2 |
2 |
2 |
0 |
0 |
T3 |
2 |
2 |
0 |
0 |
T4 |
2 |
2 |
0 |
0 |
T5 |
2 |
2 |
0 |
0 |
T6 |
2 |
2 |
0 |
0 |
T7 |
2 |
2 |
0 |
0 |
T8 |
2 |
2 |
0 |
0 |
T9 |
2 |
2 |
0 |
0 |
T10 |
2 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog
| Line No. | Total | Covered | Percent |
TOTAL | | 86 | 81 | 94.19 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 87 | 1 | 1 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
ALWAYS | 91 | 6 | 6 | 100.00 |
ALWAYS | 103 | 3 | 3 | 100.00 |
ALWAYS | 118 | 47 | 47 | 100.00 |
ALWAYS | 229 | 12 | 9 | 75.00 |
CONT_ASSIGN | 244 | 1 | 1 | 100.00 |
ALWAYS | 253 | 4 | 4 | 100.00 |
CONT_ASSIGN | 261 | 1 | 1 | 100.00 |
CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
CONT_ASSIGN | 288 | 1 | 1 | 100.00 |
CONT_ASSIGN | 298 | 1 | 1 | 100.00 |
ALWAYS | 300 | 6 | 4 | 66.67 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
84 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
91 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
95 |
1 |
1 |
96 |
1 |
1 |
98 |
1 |
1 |
|
|
|
MISSING_ELSE |
103 |
1 |
1 |
104 |
1 |
1 |
106 |
1 |
1 |
118 |
1 |
1 |
120 |
1 |
1 |
121 |
1 |
1 |
122 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
126 |
1 |
1 |
127 |
1 |
1 |
129 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
141 |
1 |
1 |
142 |
1 |
1 |
143 |
1 |
1 |
|
|
|
MISSING_ELSE |
148 |
1 |
1 |
149 |
1 |
1 |
151 |
1 |
1 |
153 |
1 |
1 |
154 |
1 |
1 |
156 |
1 |
1 |
157 |
1 |
1 |
158 |
1 |
1 |
|
|
|
MISSING_ELSE |
164 |
1 |
1 |
165 |
1 |
1 |
168 |
1 |
1 |
169 |
1 |
1 |
|
|
|
MISSING_ELSE |
174 |
1 |
1 |
175 |
1 |
1 |
179 |
1 |
1 |
181 |
1 |
1 |
182 |
1 |
1 |
|
|
|
MISSING_ELSE |
187 |
1 |
1 |
189 |
1 |
1 |
190 |
1 |
1 |
|
|
|
MISSING_ELSE |
195 |
1 |
1 |
199 |
1 |
1 |
200 |
1 |
1 |
206 |
1 |
1 |
207 |
1 |
1 |
209 |
1 |
1 |
210 |
1 |
1 |
216 |
1 |
1 |
217 |
1 |
1 |
218 |
1 |
1 |
|
|
|
MISSING_ELSE |
229 |
1 |
1 |
230 |
1 |
1 |
231 |
1 |
1 |
232 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
235 |
0 |
1 |
236 |
0 |
1 |
237 |
1 |
1 |
238 |
0 |
1 |
239 |
1 |
1 |
240 |
1 |
1 |
|
|
|
MISSING_ELSE |
244 |
1 |
1 |
253 |
1 |
1 |
254 |
1 |
1 |
255 |
1 |
1 |
256 |
1 |
1 |
|
|
|
MISSING_ELSE |
261 |
1 |
1 |
285 |
1 |
1 |
288 |
1 |
1 |
298 |
1 |
1 |
300 |
1 |
1 |
301 |
1 |
1 |
302 |
1 |
1 |
303 |
0 |
1 |
304 |
1 |
1 |
305 |
0 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog
| Total | Covered | Percent |
Conditions | 37 | 27 | 72.97 |
Logical | 37 | 27 | 72.97 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 84
EXPRESSION ((data_sel == Actual) ? data_i : ({flash_phy_pkg::BusWidth {1'b1}}))
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 88
EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 93
EXPRESSION (pack_valid && (idx == MaxIdx))
-----1---- -------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 132
EXPRESSION (req_i && ((|sel_i)))
--1-- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 151
EXPRESSION (req_i && (idx == MaxIdx))
--1-- -------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 154
EXPRESSION (req_i && last_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 175
EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 207
EXPRESSION (ack_i ? StWaitFlash : StReqFlash)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 210
EXPRESSION (ack_i ? StIdle : StReqFlash)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 232
EXPRESSION (req_o && ack_i)
--1-- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 234
EXPRESSION (calc_req_o && calc_ack_i)
-----1---- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 237
EXPRESSION (scramble_req_o && scramble_ack_i)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 288
EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 298
EXPRESSION (req_i && ack_o && last_i)
--1-- --2-- ---3--
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
10 |
7 |
70.00 |
(Not included in score) |
Transitions |
21 |
10 |
47.62 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
StCalcEcc |
190 |
Not Covered |
|
StCalcMask |
175 |
Not Covered |
|
StCalcPlainEcc |
153 |
Covered |
T1,T2,T3 |
StIdle |
104 |
Covered |
T1,T2,T3 |
StPackData |
135 |
Covered |
T1,T2,T3 |
StPostPack |
156 |
Covered |
T1,T2,T3 |
StPrePack |
133 |
Covered |
T1,T2,T3 |
StReqFlash |
175 |
Covered |
T1,T2,T3 |
StScrambleData |
182 |
Not Covered |
|
StWaitFlash |
207 |
Covered |
T1,T2,T3 |
transitions | Line No. | Covered | Tests |
StCalcEcc->StIdle |
104 |
Not Covered |
|
StCalcEcc->StReqFlash |
195 |
Not Covered |
|
StCalcMask->StIdle |
104 |
Not Covered |
|
StCalcMask->StScrambleData |
182 |
Not Covered |
|
StCalcPlainEcc->StCalcMask |
175 |
Not Covered |
|
StCalcPlainEcc->StIdle |
104 |
Not Covered |
|
StCalcPlainEcc->StReqFlash |
175 |
Covered |
T1,T2,T3 |
StIdle->StPackData |
135 |
Covered |
T1,T2,T3 |
StIdle->StPrePack |
133 |
Covered |
T1,T2,T3 |
StPackData->StCalcPlainEcc |
153 |
Covered |
T1,T2,T3 |
StPackData->StIdle |
104 |
Not Covered |
|
StPackData->StPostPack |
156 |
Covered |
T1,T2,T3 |
StPostPack->StCalcPlainEcc |
169 |
Covered |
T1,T2,T3 |
StPostPack->StIdle |
104 |
Not Covered |
|
StPrePack->StIdle |
104 |
Not Covered |
|
StPrePack->StPackData |
143 |
Covered |
T1,T2,T3 |
StReqFlash->StIdle |
104 |
Covered |
T1,T2,T3 |
StReqFlash->StWaitFlash |
207 |
Covered |
T1,T2,T3 |
StScrambleData->StCalcEcc |
190 |
Not Covered |
|
StScrambleData->StIdle |
104 |
Not Covered |
|
StWaitFlash->StIdle |
104 |
Covered |
T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog
| Line No. | Total | Covered | Percent |
Branches |
|
50 |
44 |
88.00 |
TERNARY |
84 |
2 |
2 |
100.00 |
TERNARY |
88 |
2 |
2 |
100.00 |
TERNARY |
288 |
2 |
1 |
50.00 |
IF |
91 |
4 |
4 |
100.00 |
IF |
103 |
2 |
2 |
100.00 |
CASE |
129 |
25 |
24 |
96.00 |
IF |
229 |
6 |
4 |
66.67 |
IF |
253 |
3 |
3 |
100.00 |
IF |
300 |
4 |
2 |
50.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 84 ((data_sel == Actual)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 88 ((idx > '0)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 288 (ecc_i) ?
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 91 if ((!rst_ni))
-2-: 93 if ((pack_valid && (idx == MaxIdx)))
-3-: 96 if (pack_valid)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 103 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 129 case (state_q)
-2-: 132 if ((req_i && (|sel_i)))
-3-: 134 if (req_i)
-4-: 142 if ((idx == align_next))
-5-: 151 if ((req_i && (idx == MaxIdx)))
-6-: 154 if ((req_i && last_i))
-7-: 157 if (req_i)
-8-: 168 if ((idx == MaxIdx))
-9-: 175 (scramble_i) ?
-10-: 181 if (calc_ack_i)
-11-: 189 if (scramble_ack_i)
-12-: 206 if (last_i)
-13-: 207 (ack_i) ?
-14-: 210 (ack_i) ?
-15-: 216 if (done_i)
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | -15- | Status | Tests |
StIdle |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StIdle |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StIdle |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StPrePack |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StPrePack |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StPackData |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StPackData |
- |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StPackData |
- |
- |
- |
0 |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StPackData |
- |
- |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StPostPack |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StPostPack |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StCalcPlainEcc |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
Not Covered |
|
StCalcPlainEcc |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StCalcMask |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StCalcMask |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StScrambleData |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StScrambleData |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StCalcEcc |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StReqFlash |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
Covered |
T1,T2,T3 |
StReqFlash |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
Covered |
T1,T2,T3 |
StReqFlash |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
1 |
- |
Covered |
T1,T2,T3 |
StReqFlash |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
0 |
- |
Covered |
T1,T2,T3 |
StWaitFlash |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T1,T2,T3 |
StWaitFlash |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T1,T2,T3 |
default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 229 if ((!rst_ni))
-2-: 232 if ((req_o && ack_i))
-3-: 234 if ((calc_req_o && calc_ack_i))
-4-: 237 if ((scramble_req_o && scramble_ack_i))
-5-: 239 if (pack_valid)
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
- |
- |
Not Covered |
|
0 |
0 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 253 if ((!rst_ni))
-2-: 255 if (plain_ecc_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 300 if (rst_ni)
-2-: 302 if (txn_done)
-3-: 304 if (done_i)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
1 |
Not Covered |
|
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog
Assertion Details
OneDonePerTxn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2289731 |
593 |
0 |
0 |
T1 |
78382 |
15 |
0 |
0 |
T2 |
77666 |
26 |
0 |
0 |
T3 |
3084 |
5 |
0 |
0 |
T4 |
5613 |
11 |
0 |
0 |
T6 |
70494 |
13 |
0 |
0 |
T7 |
9892 |
11 |
0 |
0 |
T8 |
13858 |
5 |
0 |
0 |
T9 |
17802 |
9 |
0 |
0 |
T11 |
211132 |
7 |
0 |
0 |
T12 |
13859 |
32 |
0 |
0 |
PostPackRule_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2289731 |
339 |
0 |
0 |
T1 |
78382 |
4 |
0 |
0 |
T2 |
77666 |
16 |
0 |
0 |
T3 |
3084 |
2 |
0 |
0 |
T4 |
5613 |
7 |
0 |
0 |
T6 |
70494 |
5 |
0 |
0 |
T7 |
9892 |
6 |
0 |
0 |
T8 |
13858 |
4 |
0 |
0 |
T9 |
17802 |
5 |
0 |
0 |
T11 |
211132 |
4 |
0 |
0 |
T12 |
13859 |
18 |
0 |
0 |
PrePackRule_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2289731 |
253 |
0 |
0 |
T1 |
78382 |
5 |
0 |
0 |
T2 |
77666 |
14 |
0 |
0 |
T3 |
3084 |
2 |
0 |
0 |
T4 |
5613 |
4 |
0 |
0 |
T6 |
70494 |
8 |
0 |
0 |
T7 |
9892 |
5 |
0 |
0 |
T8 |
13858 |
1 |
0 |
0 |
T9 |
17802 |
5 |
0 |
0 |
T11 |
211132 |
3 |
0 |
0 |
T12 |
13859 |
15 |
0 |
0 |
WidthCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
55 |
55 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog
| Line No. | Total | Covered | Percent |
TOTAL | | 86 | 81 | 94.19 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 87 | 1 | 1 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
ALWAYS | 91 | 6 | 6 | 100.00 |
ALWAYS | 103 | 3 | 3 | 100.00 |
ALWAYS | 118 | 47 | 47 | 100.00 |
ALWAYS | 229 | 12 | 9 | 75.00 |
CONT_ASSIGN | 244 | 1 | 1 | 100.00 |
ALWAYS | 253 | 4 | 4 | 100.00 |
CONT_ASSIGN | 261 | 1 | 1 | 100.00 |
CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
CONT_ASSIGN | 288 | 1 | 1 | 100.00 |
CONT_ASSIGN | 298 | 1 | 1 | 100.00 |
ALWAYS | 300 | 6 | 4 | 66.67 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
84 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
91 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
95 |
1 |
1 |
96 |
1 |
1 |
98 |
1 |
1 |
|
|
|
MISSING_ELSE |
103 |
1 |
1 |
104 |
1 |
1 |
106 |
1 |
1 |
118 |
1 |
1 |
120 |
1 |
1 |
121 |
1 |
1 |
122 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
126 |
1 |
1 |
127 |
1 |
1 |
129 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
141 |
1 |
1 |
142 |
1 |
1 |
143 |
1 |
1 |
|
|
|
MISSING_ELSE |
148 |
1 |
1 |
149 |
1 |
1 |
151 |
1 |
1 |
153 |
1 |
1 |
154 |
1 |
1 |
156 |
1 |
1 |
157 |
1 |
1 |
158 |
1 |
1 |
|
|
|
MISSING_ELSE |
164 |
1 |
1 |
165 |
1 |
1 |
168 |
1 |
1 |
169 |
1 |
1 |
|
|
|
MISSING_ELSE |
174 |
1 |
1 |
175 |
1 |
1 |
179 |
1 |
1 |
181 |
1 |
1 |
182 |
1 |
1 |
|
|
|
MISSING_ELSE |
187 |
1 |
1 |
189 |
1 |
1 |
190 |
1 |
1 |
|
|
|
MISSING_ELSE |
195 |
1 |
1 |
199 |
1 |
1 |
200 |
1 |
1 |
206 |
1 |
1 |
207 |
1 |
1 |
209 |
1 |
1 |
210 |
1 |
1 |
216 |
1 |
1 |
217 |
1 |
1 |
218 |
1 |
1 |
|
|
|
MISSING_ELSE |
229 |
1 |
1 |
230 |
1 |
1 |
231 |
1 |
1 |
232 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
235 |
0 |
1 |
236 |
0 |
1 |
237 |
1 |
1 |
238 |
0 |
1 |
239 |
1 |
1 |
240 |
1 |
1 |
|
|
|
MISSING_ELSE |
244 |
1 |
1 |
253 |
1 |
1 |
254 |
1 |
1 |
255 |
1 |
1 |
256 |
1 |
1 |
|
|
|
MISSING_ELSE |
261 |
1 |
1 |
285 |
1 |
1 |
288 |
1 |
1 |
298 |
1 |
1 |
300 |
1 |
1 |
301 |
1 |
1 |
302 |
1 |
1 |
303 |
0 |
1 |
304 |
1 |
1 |
305 |
0 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog
| Total | Covered | Percent |
Conditions | 37 | 27 | 72.97 |
Logical | 37 | 27 | 72.97 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 84
EXPRESSION ((data_sel == Actual) ? data_i : ({flash_phy_pkg::BusWidth {1'b1}}))
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 88
EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 93
EXPRESSION (pack_valid && (idx == MaxIdx))
-----1---- -------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T4,T7 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 132
EXPRESSION (req_i && ((|sel_i)))
--1-- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T5,T7 |
LINE 151
EXPRESSION (req_i && (idx == MaxIdx))
--1-- -------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 154
EXPRESSION (req_i && last_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 175
EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Not Covered | |
LINE 207
EXPRESSION (ack_i ? StWaitFlash : StReqFlash)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 210
EXPRESSION (ack_i ? StIdle : StReqFlash)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 232
EXPRESSION (req_o && ack_i)
--1-- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 234
EXPRESSION (calc_req_o && calc_ack_i)
-----1---- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 237
EXPRESSION (scramble_req_o && scramble_ack_i)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 288
EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 298
EXPRESSION (req_i && ack_o && last_i)
--1-- --2-- ---3--
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T4 |
1 | 1 | 0 | Covered | T1,T2,T4 |
1 | 1 | 1 | Covered | T1,T2,T4 |
FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
10 |
7 |
70.00 |
(Not included in score) |
Transitions |
21 |
10 |
47.62 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
StCalcEcc |
190 |
Not Covered |
|
StCalcMask |
175 |
Not Covered |
|
StCalcPlainEcc |
153 |
Covered |
T1,T2,T4 |
StIdle |
104 |
Covered |
T1,T2,T3 |
StPackData |
135 |
Covered |
T1,T2,T4 |
StPostPack |
156 |
Covered |
T1,T2,T4 |
StPrePack |
133 |
Covered |
T1,T5,T7 |
StReqFlash |
175 |
Covered |
T1,T2,T4 |
StScrambleData |
182 |
Not Covered |
|
StWaitFlash |
207 |
Covered |
T1,T2,T4 |
transitions | Line No. | Covered | Tests |
StCalcEcc->StIdle |
104 |
Not Covered |
|
StCalcEcc->StReqFlash |
195 |
Not Covered |
|
StCalcMask->StIdle |
104 |
Not Covered |
|
StCalcMask->StScrambleData |
182 |
Not Covered |
|
StCalcPlainEcc->StCalcMask |
175 |
Not Covered |
|
StCalcPlainEcc->StIdle |
104 |
Not Covered |
|
StCalcPlainEcc->StReqFlash |
175 |
Covered |
T1,T2,T4 |
StIdle->StPackData |
135 |
Covered |
T1,T2,T4 |
StIdle->StPrePack |
133 |
Covered |
T1,T5,T7 |
StPackData->StCalcPlainEcc |
153 |
Covered |
T1,T2,T4 |
StPackData->StIdle |
104 |
Not Covered |
|
StPackData->StPostPack |
156 |
Covered |
T1,T2,T4 |
StPostPack->StCalcPlainEcc |
169 |
Covered |
T1,T2,T4 |
StPostPack->StIdle |
104 |
Not Covered |
|
StPrePack->StIdle |
104 |
Not Covered |
|
StPrePack->StPackData |
143 |
Covered |
T1,T5,T7 |
StReqFlash->StIdle |
104 |
Covered |
T1,T2,T4 |
StReqFlash->StWaitFlash |
207 |
Covered |
T1,T2,T4 |
StScrambleData->StCalcEcc |
190 |
Not Covered |
|
StScrambleData->StIdle |
104 |
Not Covered |
|
StWaitFlash->StIdle |
104 |
Covered |
T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog
| Line No. | Total | Covered | Percent |
Branches |
|
50 |
44 |
88.00 |
TERNARY |
84 |
2 |
2 |
100.00 |
TERNARY |
88 |
2 |
2 |
100.00 |
TERNARY |
288 |
2 |
1 |
50.00 |
IF |
91 |
4 |
4 |
100.00 |
IF |
103 |
2 |
2 |
100.00 |
CASE |
129 |
25 |
24 |
96.00 |
IF |
229 |
6 |
4 |
66.67 |
IF |
253 |
3 |
3 |
100.00 |
IF |
300 |
4 |
2 |
50.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 84 ((data_sel == Actual)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 88 ((idx > '0)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 288 (ecc_i) ?
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 91 if ((!rst_ni))
-2-: 93 if ((pack_valid && (idx == MaxIdx)))
-3-: 96 if (pack_valid)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T4 |
0 |
0 |
1 |
Covered |
T1,T2,T4 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 103 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 129 case (state_q)
-2-: 132 if ((req_i && (|sel_i)))
-3-: 134 if (req_i)
-4-: 142 if ((idx == align_next))
-5-: 151 if ((req_i && (idx == MaxIdx)))
-6-: 154 if ((req_i && last_i))
-7-: 157 if (req_i)
-8-: 168 if ((idx == MaxIdx))
-9-: 175 (scramble_i) ?
-10-: 181 if (calc_ack_i)
-11-: 189 if (scramble_ack_i)
-12-: 206 if (last_i)
-13-: 207 (ack_i) ?
-14-: 210 (ack_i) ?
-15-: 216 if (done_i)
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | -15- | Status | Tests |
StIdle |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StIdle |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StIdle |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StPrePack |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StPrePack |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StPackData |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StPackData |
- |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StPackData |
- |
- |
- |
0 |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StPackData |
- |
- |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StPostPack |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StPostPack |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StCalcPlainEcc |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
Not Covered |
|
StCalcPlainEcc |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T4 |
StCalcMask |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StCalcMask |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StScrambleData |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StScrambleData |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StCalcEcc |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StReqFlash |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
Covered |
T1,T2,T4 |
StReqFlash |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
Covered |
T1,T2,T4 |
StReqFlash |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
1 |
- |
Covered |
T1,T2,T4 |
StReqFlash |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
0 |
- |
Covered |
T1,T2,T4 |
StWaitFlash |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T1,T2,T3 |
StWaitFlash |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T1,T2,T3 |
default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 229 if ((!rst_ni))
-2-: 232 if ((req_o && ack_i))
-3-: 234 if ((calc_req_o && calc_ack_i))
-4-: 237 if ((scramble_req_o && scramble_ack_i))
-5-: 239 if (pack_valid)
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T1,T2,T4 |
0 |
0 |
1 |
- |
- |
Not Covered |
|
0 |
0 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
0 |
0 |
1 |
Covered |
T1,T2,T4 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 253 if ((!rst_ni))
-2-: 255 if (plain_ecc_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T4 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 300 if (rst_ni)
-2-: 302 if (txn_done)
-3-: 304 if (done_i)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
1 |
Not Covered |
|
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog
Assertion Details
OneDonePerTxn_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2289731 |
470 |
0 |
0 |
T1 |
78382 |
21 |
0 |
0 |
T2 |
77666 |
2 |
0 |
0 |
T4 |
5613 |
2 |
0 |
0 |
T5 |
3118 |
10 |
0 |
0 |
T7 |
9892 |
2 |
0 |
0 |
T8 |
13858 |
18 |
0 |
0 |
T9 |
17802 |
32 |
0 |
0 |
T10 |
67480 |
1 |
0 |
0 |
T11 |
211132 |
8 |
0 |
0 |
T12 |
13859 |
10 |
0 |
0 |
PostPackRule_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2289731 |
252 |
0 |
0 |
T1 |
78382 |
11 |
0 |
0 |
T2 |
77666 |
2 |
0 |
0 |
T4 |
5613 |
2 |
0 |
0 |
T5 |
3118 |
3 |
0 |
0 |
T7 |
9892 |
1 |
0 |
0 |
T8 |
13858 |
8 |
0 |
0 |
T9 |
17802 |
14 |
0 |
0 |
T11 |
211132 |
6 |
0 |
0 |
T12 |
13859 |
6 |
0 |
0 |
T27 |
10238 |
14 |
0 |
0 |
PrePackRule_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2289731 |
197 |
0 |
0 |
T1 |
78382 |
8 |
0 |
0 |
T5 |
3118 |
7 |
0 |
0 |
T7 |
9892 |
2 |
0 |
0 |
T8 |
13858 |
8 |
0 |
0 |
T9 |
17802 |
17 |
0 |
0 |
T11 |
211132 |
5 |
0 |
0 |
T12 |
13859 |
4 |
0 |
0 |
T25 |
5060 |
1 |
0 |
0 |
T27 |
10238 |
4 |
0 |
0 |
T28 |
14131 |
11 |
0 |
0 |
WidthCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
55 |
55 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |