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Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
fifo_h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
fifo_h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dfifo[0].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dfifo[0].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dfifo[1].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dfifo[1].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dfifo[2].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dfifo[2].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo
Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5100
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 1 1
43 1 1
46 1 1
47 1 1
51 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 11024752 2991458 0 0
DepthKnown_A 11024752 10612960 0 0
RvalidKnown_A 11024752 10612960 0 0
WreadyKnown_A 11024752 10612960 0 0
gen_passthru_fifo.paramCheckPass 280 280 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11024752 2991458 0 0
T1 78382 39175 0 0
T2 77666 11073 0 0
T3 3084 244 0 0
T4 5613 741 0 0
T5 3118 1492 0 0
T6 70494 9957 0 0
T7 9892 1358 0 0
T8 13858 1303 0 0
T9 17802 2535 0 0
T10 67480 9496 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11024752 10612960 0 0
T1 78382 78297 0 0
T2 77666 77594 0 0
T3 3084 3004 0 0
T4 5613 5552 0 0
T5 3118 3061 0 0
T6 70494 70419 0 0
T7 9892 9818 0 0
T8 13858 13758 0 0
T9 17802 17741 0 0
T10 67480 67414 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11024752 10612960 0 0
T1 78382 78297 0 0
T2 77666 77594 0 0
T3 3084 3004 0 0
T4 5613 5552 0 0
T5 3118 3061 0 0
T6 70494 70419 0 0
T7 9892 9818 0 0
T8 13858 13758 0 0
T9 17802 17741 0 0
T10 67480 67414 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11024752 10612960 0 0
T1 78382 78297 0 0
T2 77666 77594 0 0
T3 3084 3004 0 0
T4 5613 5552 0 0
T5 3118 3061 0 0
T6 70494 70419 0 0
T7 9892 9818 0 0
T8 13858 13758 0 0
T9 17802 17741 0 0
T10 67480 67414 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 280 280 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5100
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 1 1
43 1 1
46 1 1
47 1 1
51 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 11024752 3626823 0 0
DepthKnown_A 11024752 10612960 0 0
RvalidKnown_A 11024752 10612960 0 0
WreadyKnown_A 11024752 10612960 0 0
gen_passthru_fifo.paramCheckPass 280 280 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11024752 3626823 0 0
T1 78382 38880 0 0
T2 77666 11063 0 0
T3 3084 1098 0 0
T4 5613 739 0 0
T5 3118 1382 0 0
T6 70494 9954 0 0
T7 9892 1347 0 0
T8 13858 5957 0 0
T9 17802 2521 0 0
T10 67480 9496 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11024752 10612960 0 0
T1 78382 78297 0 0
T2 77666 77594 0 0
T3 3084 3004 0 0
T4 5613 5552 0 0
T5 3118 3061 0 0
T6 70494 70419 0 0
T7 9892 9818 0 0
T8 13858 13758 0 0
T9 17802 17741 0 0
T10 67480 67414 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11024752 10612960 0 0
T1 78382 78297 0 0
T2 77666 77594 0 0
T3 3084 3004 0 0
T4 5613 5552 0 0
T5 3118 3061 0 0
T6 70494 70419 0 0
T7 9892 9818 0 0
T8 13858 13758 0 0
T9 17802 17741 0 0
T10 67480 67414 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11024752 10612960 0 0
T1 78382 78297 0 0
T2 77666 77594 0 0
T3 3084 3004 0 0
T4 5613 5552 0 0
T5 3118 3061 0 0
T6 70494 70419 0 0
T7 9892 9818 0 0
T8 13858 13758 0 0
T9 17802 17741 0 0
T10 67480 67414 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 280 280 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5100
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 1 1
43 1 1
46 1 1
47 1 1
51 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 11024752 13632 0 0
DepthKnown_A 11024752 10612960 0 0
RvalidKnown_A 11024752 10612960 0 0
WreadyKnown_A 11024752 10612960 0 0
gen_passthru_fifo.paramCheckPass 280 280 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11024752 13632 0 0
T1 78382 296 0 0
T2 77666 210 0 0
T3 3084 30 0 0
T4 5613 45 0 0
T5 3118 60 0 0
T6 70494 53 0 0
T7 9892 152 0 0
T8 13858 227 0 0
T9 17802 325 0 0
T10 67480 4 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11024752 10612960 0 0
T1 78382 78297 0 0
T2 77666 77594 0 0
T3 3084 3004 0 0
T4 5613 5552 0 0
T5 3118 3061 0 0
T6 70494 70419 0 0
T7 9892 9818 0 0
T8 13858 13758 0 0
T9 17802 17741 0 0
T10 67480 67414 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11024752 10612960 0 0
T1 78382 78297 0 0
T2 77666 77594 0 0
T3 3084 3004 0 0
T4 5613 5552 0 0
T5 3118 3061 0 0
T6 70494 70419 0 0
T7 9892 9818 0 0
T8 13858 13758 0 0
T9 17802 17741 0 0
T10 67480 67414 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11024752 10612960 0 0
T1 78382 78297 0 0
T2 77666 77594 0 0
T3 3084 3004 0 0
T4 5613 5552 0 0
T5 3118 3061 0 0
T6 70494 70419 0 0
T7 9892 9818 0 0
T8 13858 13758 0 0
T9 17802 17741 0 0
T10 67480 67414 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 280 280 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5100
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 1 1
43 1 1
46 1 1
47 1 1
51 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 11024752 26161 0 0
DepthKnown_A 11024752 10612960 0 0
RvalidKnown_A 11024752 10612960 0 0
WreadyKnown_A 11024752 10612960 0 0
gen_passthru_fifo.paramCheckPass 280 280 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11024752 26161 0 0
T1 78382 296 0 0
T2 77666 210 0 0
T3 3084 125 0 0
T4 5613 45 0 0
T5 3118 60 0 0
T6 70494 53 0 0
T7 9892 152 0 0
T8 13858 1046 0 0
T9 17802 325 0 0
T10 67480 4 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11024752 10612960 0 0
T1 78382 78297 0 0
T2 77666 77594 0 0
T3 3084 3004 0 0
T4 5613 5552 0 0
T5 3118 3061 0 0
T6 70494 70419 0 0
T7 9892 9818 0 0
T8 13858 13758 0 0
T9 17802 17741 0 0
T10 67480 67414 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11024752 10612960 0 0
T1 78382 78297 0 0
T2 77666 77594 0 0
T3 3084 3004 0 0
T4 5613 5552 0 0
T5 3118 3061 0 0
T6 70494 70419 0 0
T7 9892 9818 0 0
T8 13858 13758 0 0
T9 17802 17741 0 0
T10 67480 67414 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11024752 10612960 0 0
T1 78382 78297 0 0
T2 77666 77594 0 0
T3 3084 3004 0 0
T4 5613 5552 0 0
T5 3118 3061 0 0
T6 70494 70419 0 0
T7 9892 9818 0 0
T8 13858 13758 0 0
T9 17802 17741 0 0
T10 67480 67414 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 280 280 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5100
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 1 1
43 1 1
46 1 1
47 1 1
51 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 11024752 18478 0 0
DepthKnown_A 11024752 10612960 0 0
RvalidKnown_A 11024752 10612960 0 0
WreadyKnown_A 11024752 10612960 0 0
gen_passthru_fifo.paramCheckPass 280 280 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11024752 18478 0 0
T1 78382 561 0 0
T2 77666 124 0 0
T3 3084 24 0 0
T4 5613 127 0 0
T5 3118 215 0 0
T6 70494 21 0 0
T7 9892 259 0 0
T8 13858 206 0 0
T9 17802 366 0 0
T10 67480 4 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11024752 10612960 0 0
T1 78382 78297 0 0
T2 77666 77594 0 0
T3 3084 3004 0 0
T4 5613 5552 0 0
T5 3118 3061 0 0
T6 70494 70419 0 0
T7 9892 9818 0 0
T8 13858 13758 0 0
T9 17802 17741 0 0
T10 67480 67414 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11024752 10612960 0 0
T1 78382 78297 0 0
T2 77666 77594 0 0
T3 3084 3004 0 0
T4 5613 5552 0 0
T5 3118 3061 0 0
T6 70494 70419 0 0
T7 9892 9818 0 0
T8 13858 13758 0 0
T9 17802 17741 0 0
T10 67480 67414 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11024752 10612960 0 0
T1 78382 78297 0 0
T2 77666 77594 0 0
T3 3084 3004 0 0
T4 5613 5552 0 0
T5 3118 3061 0 0
T6 70494 70419 0 0
T7 9892 9818 0 0
T8 13858 13758 0 0
T9 17802 17741 0 0
T10 67480 67414 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 280 280 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5100
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 1 1
43 1 1
46 1 1
47 1 1
51 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 11024752 25638 0 0
DepthKnown_A 11024752 10612960 0 0
RvalidKnown_A 11024752 10612960 0 0
WreadyKnown_A 11024752 10612960 0 0
gen_passthru_fifo.paramCheckPass 280 280 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11024752 25638 0 0
T1 78382 266 0 0
T2 77666 114 0 0
T3 3084 103 0 0
T4 5613 125 0 0
T5 3118 105 0 0
T6 70494 18 0 0
T7 9892 248 0 0
T8 13858 915 0 0
T9 17802 352 0 0
T10 67480 4 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11024752 10612960 0 0
T1 78382 78297 0 0
T2 77666 77594 0 0
T3 3084 3004 0 0
T4 5613 5552 0 0
T5 3118 3061 0 0
T6 70494 70419 0 0
T7 9892 9818 0 0
T8 13858 13758 0 0
T9 17802 17741 0 0
T10 67480 67414 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11024752 10612960 0 0
T1 78382 78297 0 0
T2 77666 77594 0 0
T3 3084 3004 0 0
T4 5613 5552 0 0
T5 3118 3061 0 0
T6 70494 70419 0 0
T7 9892 9818 0 0
T8 13858 13758 0 0
T9 17802 17741 0 0
T10 67480 67414 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11024752 10612960 0 0
T1 78382 78297 0 0
T2 77666 77594 0 0
T3 3084 3004 0 0
T4 5613 5552 0 0
T5 3118 3061 0 0
T6 70494 70419 0 0
T7 9892 9818 0 0
T8 13858 13758 0 0
T9 17802 17741 0 0
T10 67480 67414 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 280 280 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5100
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 1 1
43 1 1
46 1 1
47 1 1
51 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 11024752 2948106 0 0
DepthKnown_A 11024752 10612960 0 0
RvalidKnown_A 11024752 10612960 0 0
WreadyKnown_A 11024752 10612960 0 0
gen_passthru_fifo.paramCheckPass 280 280 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11024752 2948106 0 0
T1 78382 38318 0 0
T2 77666 10739 0 0
T3 3084 190 0 0
T4 5613 569 0 0
T5 3118 1217 0 0
T6 70494 9883 0 0
T7 9892 947 0 0
T8 13858 870 0 0
T9 17802 1844 0 0
T10 67480 9488 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11024752 10612960 0 0
T1 78382 78297 0 0
T2 77666 77594 0 0
T3 3084 3004 0 0
T4 5613 5552 0 0
T5 3118 3061 0 0
T6 70494 70419 0 0
T7 9892 9818 0 0
T8 13858 13758 0 0
T9 17802 17741 0 0
T10 67480 67414 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11024752 10612960 0 0
T1 78382 78297 0 0
T2 77666 77594 0 0
T3 3084 3004 0 0
T4 5613 5552 0 0
T5 3118 3061 0 0
T6 70494 70419 0 0
T7 9892 9818 0 0
T8 13858 13758 0 0
T9 17802 17741 0 0
T10 67480 67414 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11024752 10612960 0 0
T1 78382 78297 0 0
T2 77666 77594 0 0
T3 3084 3004 0 0
T4 5613 5552 0 0
T5 3118 3061 0 0
T6 70494 70419 0 0
T7 9892 9818 0 0
T8 13858 13758 0 0
T9 17802 17741 0 0
T10 67480 67414 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 280 280 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5100
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 1 1
43 1 1
46 1 1
47 1 1
51 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 11024752 3575024 0 0
DepthKnown_A 11024752 10612960 0 0
RvalidKnown_A 11024752 10612960 0 0
WreadyKnown_A 11024752 10612960 0 0
gen_passthru_fifo.paramCheckPass 280 280 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11024752 3575024 0 0
T1 78382 38318 0 0
T2 77666 10739 0 0
T3 3084 870 0 0
T4 5613 569 0 0
T5 3118 1217 0 0
T6 70494 9883 0 0
T7 9892 947 0 0
T8 13858 3996 0 0
T9 17802 1844 0 0
T10 67480 9488 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11024752 10612960 0 0
T1 78382 78297 0 0
T2 77666 77594 0 0
T3 3084 3004 0 0
T4 5613 5552 0 0
T5 3118 3061 0 0
T6 70494 70419 0 0
T7 9892 9818 0 0
T8 13858 13758 0 0
T9 17802 17741 0 0
T10 67480 67414 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11024752 10612960 0 0
T1 78382 78297 0 0
T2 77666 77594 0 0
T3 3084 3004 0 0
T4 5613 5552 0 0
T5 3118 3061 0 0
T6 70494 70419 0 0
T7 9892 9818 0 0
T8 13858 13758 0 0
T9 17802 17741 0 0
T10 67480 67414 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11024752 10612960 0 0
T1 78382 78297 0 0
T2 77666 77594 0 0
T3 3084 3004 0 0
T4 5613 5552 0 0
T5 3118 3061 0 0
T6 70494 70419 0 0
T7 9892 9818 0 0
T8 13858 13758 0 0
T9 17802 17741 0 0
T10 67480 67414 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 280 280 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%