Module Definition
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Module : flash_ctrl_lcmgr
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.26 90.59 13.46 0.00 68.97

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_flash_hw_if 43.26 90.59 13.46 0.00 68.97



Module Instance : tb.dut.u_flash_hw_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.26 90.59 13.46 0.00 68.97


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.00 92.33 25.61 0.00 72.04 25.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
66.52 91.74 69.23 13.28 75.00 83.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_addr_sync_reqack 63.64 100.00 90.91 0.00
u_data_sync_reqack 63.64 100.00 90.91 0.00
u_page_cnt 56.91 91.67 53.85 57.14 25.00
u_state_regs 100.00 100.00 100.00
u_sync_flash_init 100.00 100.00 100.00
u_sync_rma_req 100.00 100.00 100.00 100.00
u_word_cnt 47.24 77.78 41.18 50.00 20.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : flash_ctrl_lcmgr
Line No.TotalCoveredPercent
TOTAL20218390.59
CONT_ASSIGN12311100.00
CONT_ASSIGN12411100.00
ALWAYS12777100.00
ALWAYS1406466.67
ALWAYS1516466.67
CONT_ASSIGN16311100.00
CONT_ASSIGN16411100.00
ALWAYS1674250.00
CONT_ASSIGN17911100.00
CONT_ASSIGN18011100.00
ALWAYS2529555.56
ALWAYS2756565100.00
CONT_ASSIGN45411100.00
CONT_ASSIGN46111100.00
ALWAYS50755100.00
ALWAYS5174375.00
ALWAYS52510550.00
ALWAYS5422150.00
ALWAYS5514375.00
CONT_ASSIGN56511100.00
CONT_ASSIGN56911100.00
CONT_ASSIGN57011100.00
ALWAYS5775555100.00
CONT_ASSIGN67711100.00
CONT_ASSIGN67811100.00
CONT_ASSIGN67911100.00
CONT_ASSIGN68011100.00
CONT_ASSIGN68100
CONT_ASSIGN68200
CONT_ASSIGN68311100.00
CONT_ASSIGN68411100.00
CONT_ASSIGN68711100.00
CONT_ASSIGN68911100.00
CONT_ASSIGN69011100.00
CONT_ASSIGN692100.00
CONT_ASSIGN69311100.00
CONT_ASSIGN69511100.00
CONT_ASSIGN69811100.00
CONT_ASSIGN70111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
123 1 1
124 1 1
127 1 1
128 1 1
129 1 1
130 1 1
132 1 1
133 1 1
134 1 1
140 1 1
141 1 1
142 1 1
143 0 1
144 1 1
145 0 1
MISSING_ELSE
151 1 1
152 1 1
153 1 1
154 0 1
155 1 1
156 0 1
MISSING_ELSE
163 1 1
164 1 1
167 1 1
168 0 1
170 1 1
171 0 1
MISSING_ELSE
179 1 1
180 1 1
252 1 1
253 1 1
254 1 1
256 1 1
257 0 1
258 0 1
MISSING_ELSE
261 1 1
262 0 1
263 0 1
MISSING_ELSE
275 1 1
278 1 1
279 1 1
280 1 1
281 1 1
284 1 1
285 1 1
286 1 1
287 1 1
288 1 1
291 1 1
293 1 1
294 1 1
295 1 1
298 1 1
300 1 1
301 1 1
304 1 1
305 1 1
308 1 1
309 1 1
311 1 1
314 1 1
315 1 1
MISSING_ELSE
320 1 1
321 1 1
322 1 1
323 1 1
MISSING_ELSE
328 1 1
329 1 1
330 1 1
332 1 1
MISSING_ELSE
339 1 1
342 1 1
343 1 1
344 1 1
347 1 1
348 1 1
349 1 1
352 1 1
353 1 1
360 1 1
361 1 1
362 1 1
366 1 1
367 1 1
368 1 1
370 1 1
MISSING_ELSE
377 1 1
378 1 1
379 1 1
MISSING_ELSE
385 1 1
386 1 1
387 1 1
==> MISSING_ELSE
392 1 1
393 1 1
394 1 1
396 1 1
400 1 1
401 1 1
402 1 1
MISSING_ELSE
412 1 1
413 1 1
414 1 1
416 1 1
454 1 1
461 1 1
507 1 1
508 1 1
509 1 1
511 1 1
512 1 1
517 1 1
518 1 1
519 1 1
520 0 1
MISSING_ELSE
525 1 1
526 1 1
527 1 1
528 0 1
529 1 1
530 0 1
531 0 1
==> MISSING_ELSE
533 1 1
534 0 1
535 0 1
==> MISSING_ELSE
MISSING_ELSE
542 1 1
543 0 1
MISSING_ELSE
551 1 1
552 1 1
553 1 1
554 0 1
MISSING_ELSE
565 1 1
569 1 1
570 1 1
577 1 1
578 1 1
579 1 1
580 1 1
581 1 1
582 1 1
583 1 1
584 1 1
585 1 1
586 1 1
587 1 1
588 1 1
589 1 1
590 1 1
591 1 1
593 1 1
596 1 1
597 1 1
598 1 1
MISSING_ELSE
603 1 1
604 1 1
606 1 1
607 1 1
608 1 1
613 1 1
614 1 1
615 1 1
616 1 1
617 1 1
618 1 1
MISSING_ELSE
623 1 1
624 1 1
626 1 1
627 1 1
628 1 1
633 1 1
634 1 1
635 1 1
637 1 1
638 1 1
MISSING_ELSE
643 1 1
644 1 1
646 1 1
647 1 1
648 1 1
649 1 1
MISSING_ELSE
654 1 1
655 1 1
656 1 1
658 1 1
659 1 1
660 1 1
661 1 1
MISSING_ELSE
664 1 1
665 1 1
MISSING_ELSE
677 1 1
678 1 1
679 1 1
680 1 1
681 unreachable
682 unreachable
683 1 1
684 1 1
687 1 1
689 1 1
690 1 1
692 0 1
693 1 1
695 1 1
698 1 1
701 1 1


Cond Coverage for Module : flash_ctrl_lcmgr
TotalCoveredPercent
Conditions52713.46
Logical52713.46
Non-Logical00
Event00

 LINE       167
 EXPRESSION (seed_phase && validate_q && rvalid_i)
             -----1----    -----2----    ----3---
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered

 LINE       170
 EXPRESSION (seed_phase && rvalid_i)
             -----1----    ----2---
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       256
 EXPRESSION (addr_key_req_d && addr_key_ack_q)
             -------1------    -------2------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       261
 EXPRESSION (data_key_req_d && data_key_ack_q)
             -------1------    -------2------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       332
 EXPRESSION (provision_en_i ? StReadSeeds : StWait)
             -------1------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       396
 EXPRESSION ((rma_wipe_idx == MaxWipeEntry[(WipeIdxWidth - 1):0]) && rma_wipe_done)
             --------------------------1-------------------------    ------2------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       400
 EXPRESSION ((err_sts != On) ? StInvalid : StRmaRsp)
             -------1-------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       530
 EXPRESSION (wvalid_o && wready_i)
             ----1---    ----2---
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       534
 EXPRESSION (rvalid_i && rready_o)
             ----1---    ----2---
-1--2-StatusTests
01Not Covered
10Unreachable
11Not Covered

 LINE       542
 EXPRESSION (prog_cnt_en && wvalid_o && wready_i)
             -----1-----    ----2---    ----3---
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered

 LINE       553
 EXPRESSION (err_sts_set && (err_sts != Off))
             -----1-----    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       637
 EXPRESSION ((beat_cnt == MaxBeatCnt[0]) && wready_i)
             -------------1-------------    ----2---
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       658
 EXPRESSION ((beat_cnt == MaxBeatCnt[0]) && done_i)
             -------------1-------------    ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       664
 EXPRESSION (rvalid_i && rready_o)
             ----1---    ----2---
-1--2-StatusTests
01Not Covered
10Unreachable
11Not Covered

 LINE       679
 EXPRESSION (seed_phase ? start : rma_start)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       680
 EXPRESSION (seed_phase ? op : rma_op)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       683
 EXPRESSION (seed_phase ? part_sel : rma_part_sel)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       684
 EXPRESSION (seed_phase ? info_sel : rma_info_sel)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       685
 EXPRESSION (seed_phase ? num_words : rma_num_words)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       687
 EXPRESSION (seed_phase ? (32'({addr, {flash_ctrl_pkg::BusByteWidth {1'b0}}})) : (32'({rma_addr, {flash_ctrl_pkg::BusByteWidth {1'b0}}})))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

FSM Coverage for Module : flash_ctrl_lcmgr
Summary for FSM :: state_q
TotalCoveredPercent
States 9 1 11.11 (Not included in score)
Transitions 18 0 0.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StEntropyReseed 379 Not Covered
StIdle 128 Covered T1,T2,T3
StInvalid 400 Not Covered
StReadSeeds 332 Not Covered
StReqAddrKey 315 Not Covered
StReqDataKey 323 Not Covered
StRmaRsp 400 Not Covered
StRmaWipe 387 Not Covered
StWait 332 Not Covered


transitionsLine No.CoveredTests
StEntropyReseed->StIdle 128 Not Covered
StEntropyReseed->StRmaWipe 387 Not Covered
StIdle->StReqAddrKey 315 Not Covered
StInvalid->StIdle 128 Not Covered
StReadSeeds->StIdle 128 Not Covered
StReadSeeds->StWait 349 Not Covered
StReqAddrKey->StIdle 128 Not Covered
StReqAddrKey->StReqDataKey 323 Not Covered
StReqDataKey->StIdle 128 Not Covered
StReqDataKey->StReadSeeds 332 Not Covered
StReqDataKey->StWait 332 Not Covered
StRmaRsp->StIdle 128 Not Covered
StRmaRsp->StInvalid 414 Not Covered
StRmaWipe->StIdle 128 Not Covered
StRmaWipe->StInvalid 400 Not Covered
StRmaWipe->StRmaRsp 400 Not Covered
StWait->StEntropyReseed 379 Not Covered
StWait->StIdle 128 Not Covered



Branch Coverage for Module : flash_ctrl_lcmgr
Line No.TotalCoveredPercent
Branches 87 60 68.97
TERNARY 679 2 1 50.00
TERNARY 680 2 1 50.00
TERNARY 683 2 1 50.00
TERNARY 684 2 1 50.00
TERNARY 685 2 1 50.00
TERNARY 687 2 1 50.00
IF 127 2 2 100.00
IF 140 4 2 50.00
IF 151 4 2 50.00
IF 167 3 1 33.33
IF 252 5 3 60.00
CASE 311 23 18 78.26
IF 507 2 2 100.00
IF 517 3 2 66.67
IF 525 7 2 28.57
IF 542 2 1 50.00
IF 551 3 2 66.67
CASE 593 17 17 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 679 (seed_phase) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 680 (seed_phase) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 683 (seed_phase) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 684 (seed_phase) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 685 (seed_phase) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 687 (seed_phase) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 127 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 140 if ((!rst_ni)) -2-: 142 if (seed_cnt_clr) -3-: 144 if (seed_cnt_en)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 151 if ((!rst_ni)) -2-: 153 if (addr_cnt_clr) -3-: 155 if (addr_cnt_en)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 167 if (((seed_phase && validate_q) && rvalid_i)) -2-: 170 if ((seed_phase && rvalid_i))

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 252 if ((!rst_ni)) -2-: 256 if ((addr_key_req_d && addr_key_ack_q)) -3-: 261 if ((data_key_req_d && data_key_ack_q))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Not Covered
0 0 - Covered T1,T2,T3
0 - 1 Not Covered
0 - 0 Covered T1,T2,T3


LineNo. Expression -1-: 311 case (state_q) -2-: 314 if (init_q) -3-: 322 if (addr_key_ack_q) -4-: 330 if (data_key_ack_q) -5-: 332 (provision_en_i) ? -6-: 347 if ((seed_cnt_q == flash_ctrl_pkg::NumSeeds)) -7-: 352 if ((!done_i)) -8-: 360 if (done_i) -9-: 366 if (validate_q) -10-: 378 if ((rma_req[0] == On)) -11-: 386 if (edn_ack_i) -12-: 396 if (((rma_wipe_idx == MaxWipeEntry[(WipeIdxWidth - 1):0]) && rma_wipe_done)) -13-: 400 ((err_sts != On)) ? -14-: 401 if (rma_wipe_done) -15-: 413 if ((err_sts != On))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15-StatusTests
StIdle 1 - - - - - - - - - - - - - Covered T1,T2,T3
StIdle 0 - - - - - - - - - - - - - Covered T1,T2,T3
StReqAddrKey - 1 - - - - - - - - - - - - Covered T1,T2,T3
StReqAddrKey - 0 - - - - - - - - - - - - Covered T1,T2,T3
StReqDataKey - - 1 1 - - - - - - - - - - Not Covered
StReqDataKey - - 1 0 - - - - - - - - - - Not Covered
StReqDataKey - - 0 - - - - - - - - - - - Covered T1,T2,T3
StReadSeeds - - - - 1 - - - - - - - - - Covered T1,T2,T3
StReadSeeds - - - - 0 1 - - - - - - - - Covered T1,T2,T3
StReadSeeds - - - - 0 0 1 1 - - - - - - Covered T1,T2,T3
StReadSeeds - - - - 0 0 1 0 - - - - - - Covered T1,T2,T3
StReadSeeds - - - - 0 0 0 - - - - - - - Covered T1,T2,T3
StWait - - - - - - - - 1 - - - - - Covered T1,T2,T3
StWait - - - - - - - - 0 - - - - - Covered T1,T2,T3
StEntropyReseed - - - - - - - - - 1 - - - - Covered T1,T2,T3
StEntropyReseed - - - - - - - - - 0 - - - - Not Covered
StRmaWipe - - - - - - - - - - 1 1 - - Not Covered
StRmaWipe - - - - - - - - - - 1 0 - - Not Covered
StRmaWipe - - - - - - - - - - 0 - 1 - Covered T1,T2,T3
StRmaWipe - - - - - - - - - - 0 - 0 - Covered T1,T2,T3
StRmaRsp - - - - - - - - - - - - - 1 Covered T1,T2,T3
StRmaRsp - - - - - - - - - - - - - 0 Covered T1,T2,T3
default - - - - - - - - - - - - - - Covered T1,T2,T3


LineNo. Expression -1-: 507 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 517 if ((!rst_ni)) -2-: 519 if (rma_wipe_idx_incr)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 525 if ((!rst_ni)) -2-: 527 if (beat_cnt_clr) -3-: 529 if (prog_cnt_en) -4-: 530 if ((wvalid_o && wready_i)) -5-: 533 if (rd_cnt_en) -6-: 534 if ((rvalid_i && rready_o))

Branches:
-1--2--3--4--5--6-StatusTests
1 - - - - - Covered T1,T2,T3
0 1 - - - - Not Covered
0 0 1 1 - - Not Covered
0 0 1 0 - - Not Covered
0 0 0 - 1 1 Not Covered
0 0 0 - 1 0 Not Covered
0 0 0 - 0 - Covered T1,T2,T3


LineNo. Expression -1-: 542 if (((prog_cnt_en && wvalid_o) && wready_i))

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 551 if ((!rst_ni)) -2-: 553 if ((err_sts_set && (err_sts != Off)))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 593 case (rma_state_q) -2-: 596 if (rma_wipe_req) -3-: 603 if ((page_cnt < end_page)) -4-: 615 if (done_i) -5-: 623 if ((word_cnt < flash_ctrl_pkg::BusWordsPerPage)) -6-: 637 if (((beat_cnt == MaxBeatCnt[0]) && wready_i)) -7-: 646 if (done_i) -8-: 658 if (((beat_cnt == MaxBeatCnt[0]) && done_i)) -9-: 664 if ((rvalid_i && rready_o))

Branches:
-1--2--3--4--5--6--7--8--9-StatusTests
StRmaIdle 1 - - - - - - - Covered T1,T2,T3
StRmaIdle 0 - - - - - - - Covered T1,T2,T3
StRmaPageSel - 1 - - - - - - Covered T1,T2,T3
StRmaPageSel - 0 - - - - - - Covered T1,T2,T3
StRmaErase - - 1 - - - - - Covered T1,T2,T3
StRmaErase - - 0 - - - - - Covered T1,T2,T3
StRmaWordSel - - - 1 - - - - Covered T1,T2,T3
StRmaWordSel - - - 0 - - - - Covered T1,T2,T3
StRmaProgram - - - - 1 - - - Covered T1,T2,T3
StRmaProgram - - - - 0 - - - Covered T1,T2,T3
StRmaProgramWait - - - - - 1 - - Covered T1,T2,T3
StRmaProgramWait - - - - - 0 - - Covered T1,T2,T3
StRmaRdVerify - - - - - - 1 - Covered T1,T2,T3
StRmaRdVerify - - - - - - 0 - Covered T1,T2,T3
StRmaRdVerify - - - - - - - 1 Covered T1,T2,T3
StRmaRdVerify - - - - - - - 0 Covered T1,T2,T3
default - - - - - - - - Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%