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Module Instance : tb.dut.u_reg_core.u_intr_state_prog_empty.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_intr_state_prog_empty


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_intr_state_prog_lvl.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_intr_state_prog_lvl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_intr_state_rd_full.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_intr_state_rd_full


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_intr_state_rd_lvl.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_intr_state_rd_lvl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_intr_state_op_done.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_intr_state_op_done


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_intr_state_corr_err.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_intr_state_corr_err


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_intr_enable_prog_empty.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_intr_enable_prog_empty


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_intr_enable_prog_lvl.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_intr_enable_prog_lvl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_intr_enable_rd_full.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_intr_enable_rd_full


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_intr_enable_rd_lvl.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_intr_enable_rd_lvl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_intr_enable_op_done.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_intr_enable_op_done


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_intr_enable_corr_err.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_intr_enable_corr_err


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_dis.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_dis


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_exec.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_exec


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_init.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_init


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_control_start.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_control_start


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_control_op.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_control_op


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_control_prog_sel.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_control_prog_sel


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_control_erase_sel.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_control_erase_sel


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_control_partition_sel.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_control_partition_sel


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_control_info_sel.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_control_info_sel


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_control_num.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_control_num


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_addr.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_addr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_prog_type_en_normal.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prog_type_en_normal


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_prog_type_en_repair.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prog_type_en_repair


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_erase_suspend.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 100.00 50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 100.00 50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.75 87.50 80.00 u_erase_suspend


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_reg_core.u_intr_state_prog_empty.wr_en_data_arb
tb.dut.u_reg_core.u_intr_state_prog_lvl.wr_en_data_arb
tb.dut.u_reg_core.u_intr_state_rd_full.wr_en_data_arb
tb.dut.u_reg_core.u_intr_state_rd_lvl.wr_en_data_arb
tb.dut.u_reg_core.u_intr_state_op_done.wr_en_data_arb
tb.dut.u_reg_core.u_intr_state_corr_err.wr_en_data_arb
tb.dut.u_reg_core.u_intr_enable_prog_empty.wr_en_data_arb
tb.dut.u_reg_core.u_intr_enable_prog_lvl.wr_en_data_arb
tb.dut.u_reg_core.u_intr_enable_rd_full.wr_en_data_arb
tb.dut.u_reg_core.u_intr_enable_rd_lvl.wr_en_data_arb
tb.dut.u_reg_core.u_intr_enable_op_done.wr_en_data_arb
tb.dut.u_reg_core.u_intr_enable_corr_err.wr_en_data_arb
tb.dut.u_reg_core.u_dis.wr_en_data_arb
tb.dut.u_reg_core.u_exec.wr_en_data_arb
tb.dut.u_reg_core.u_init.wr_en_data_arb
tb.dut.u_reg_core.u_control_start.wr_en_data_arb
tb.dut.u_reg_core.u_control_op.wr_en_data_arb
tb.dut.u_reg_core.u_control_prog_sel.wr_en_data_arb
tb.dut.u_reg_core.u_control_erase_sel.wr_en_data_arb
tb.dut.u_reg_core.u_control_partition_sel.wr_en_data_arb
tb.dut.u_reg_core.u_control_info_sel.wr_en_data_arb
tb.dut.u_reg_core.u_control_num.wr_en_data_arb
tb.dut.u_reg_core.u_addr.wr_en_data_arb
tb.dut.u_reg_core.u_prog_type_en_normal.wr_en_data_arb
tb.dut.u_reg_core.u_prog_type_en_repair.wr_en_data_arb
tb.dut.u_reg_core.u_erase_suspend.wr_en_data_arb
Line Coverage for Instance : tb.dut.u_reg_core.u_intr_state_prog_empty.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1

Line Coverage for Instance : tb.dut.u_reg_core.u_intr_state_prog_lvl.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1

Line Coverage for Instance : tb.dut.u_reg_core.u_intr_state_rd_full.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1

Line Coverage for Instance : tb.dut.u_reg_core.u_intr_state_rd_lvl.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1

Line Coverage for Instance : tb.dut.u_reg_core.u_intr_state_op_done.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1

Line Coverage for Instance : tb.dut.u_reg_core.u_intr_state_corr_err.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1

Line Coverage for Instance : tb.dut.u_reg_core.u_intr_enable_prog_empty.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
35 1 1


Cond Coverage for Instance : tb.dut.u_reg_core.u_intr_enable_prog_empty.wr_en_data_arb
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       32
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT13,T14,T15

Branch Coverage for Instance : tb.dut.u_reg_core.u_intr_enable_prog_empty.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 32 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 32 ((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T13,T14,T15
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_core.u_intr_enable_prog_lvl.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
35 1 1


Cond Coverage for Instance : tb.dut.u_reg_core.u_intr_enable_prog_lvl.wr_en_data_arb
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       32
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT13,T14,T15

Branch Coverage for Instance : tb.dut.u_reg_core.u_intr_enable_prog_lvl.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 32 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 32 ((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T13,T14,T15
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_core.u_intr_enable_rd_full.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
35 1 1


Cond Coverage for Instance : tb.dut.u_reg_core.u_intr_enable_rd_full.wr_en_data_arb
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       32
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT13,T14,T15

Branch Coverage for Instance : tb.dut.u_reg_core.u_intr_enable_rd_full.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 32 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 32 ((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T13,T14,T15
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_core.u_intr_enable_rd_lvl.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
35 1 1


Cond Coverage for Instance : tb.dut.u_reg_core.u_intr_enable_rd_lvl.wr_en_data_arb
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       32
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT13,T14,T15

Branch Coverage for Instance : tb.dut.u_reg_core.u_intr_enable_rd_lvl.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 32 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 32 ((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T13,T14,T15
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_core.u_intr_enable_op_done.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
35 1 1


Cond Coverage for Instance : tb.dut.u_reg_core.u_intr_enable_op_done.wr_en_data_arb
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       32
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT13,T14,T15

Branch Coverage for Instance : tb.dut.u_reg_core.u_intr_enable_op_done.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 32 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 32 ((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T13,T14,T15
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_core.u_intr_enable_corr_err.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
35 1 1


Cond Coverage for Instance : tb.dut.u_reg_core.u_intr_enable_corr_err.wr_en_data_arb
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       32
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT13,T14,T15

Branch Coverage for Instance : tb.dut.u_reg_core.u_intr_enable_corr_err.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 32 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 32 ((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T13,T14,T15
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_core.u_dis.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1

Line Coverage for Instance : tb.dut.u_reg_core.u_exec.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
35 1 1


Cond Coverage for Instance : tb.dut.u_reg_core.u_exec.wr_en_data_arb
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       32
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT13,T14,T15

Branch Coverage for Instance : tb.dut.u_reg_core.u_exec.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 32 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 32 ((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T13,T14,T15
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_core.u_init.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1

Line Coverage for Instance : tb.dut.u_reg_core.u_control_start.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
35 1 1


Cond Coverage for Instance : tb.dut.u_reg_core.u_control_start.wr_en_data_arb
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       32
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_core.u_control_start.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 32 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 32 ((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_core.u_control_op.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
35 1 1


Cond Coverage for Instance : tb.dut.u_reg_core.u_control_op.wr_en_data_arb
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       32
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_core.u_control_op.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 32 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 32 ((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_core.u_control_prog_sel.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
35 1 1


Cond Coverage for Instance : tb.dut.u_reg_core.u_control_prog_sel.wr_en_data_arb
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       32
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_core.u_control_prog_sel.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 32 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 32 ((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_core.u_control_erase_sel.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
35 1 1


Cond Coverage for Instance : tb.dut.u_reg_core.u_control_erase_sel.wr_en_data_arb
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       32
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_core.u_control_erase_sel.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 32 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 32 ((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_core.u_control_partition_sel.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
35 1 1


Cond Coverage for Instance : tb.dut.u_reg_core.u_control_partition_sel.wr_en_data_arb
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       32
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_core.u_control_partition_sel.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 32 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 32 ((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_core.u_control_info_sel.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
35 1 1


Cond Coverage for Instance : tb.dut.u_reg_core.u_control_info_sel.wr_en_data_arb
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       32
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_core.u_control_info_sel.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 32 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 32 ((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_core.u_control_num.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
35 1 1


Cond Coverage for Instance : tb.dut.u_reg_core.u_control_num.wr_en_data_arb
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       32
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_core.u_control_num.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 32 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 32 ((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_core.u_addr.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
35 1 1


Cond Coverage for Instance : tb.dut.u_reg_core.u_addr.wr_en_data_arb
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       32
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_core.u_addr.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 32 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 32 ((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg_core.u_prog_type_en_normal.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1

Line Coverage for Instance : tb.dut.u_reg_core.u_prog_type_en_repair.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1

Line Coverage for Instance : tb.dut.u_reg_core.u_erase_suspend.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
35 1 1


Cond Coverage for Instance : tb.dut.u_reg_core.u_erase_suspend.wr_en_data_arb
TotalCoveredPercent
Conditions2150.00
Logical2150.00
Non-Logical00
Event00

 LINE       32
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

Branch Coverage for Instance : tb.dut.u_reg_core.u_erase_suspend.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 1 50.00
TERNARY 32 2 1 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 32 ((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%