Module Definition
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Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
62.04 100.00 27.78 58.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
59.01 87.23 28.57 25.10 54.17 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
69.44 98.61 58.33 60.00 70.27 60.00 gen_flash_cores[0].u_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_cipher 25.10 25.10
u_mult 65.59 82.35 30.00 50.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
62.04 100.00 27.78 58.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
59.01 87.23 28.57 25.10 54.17 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
69.44 98.61 58.33 60.00 70.27 60.00 gen_flash_cores[1].u_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_cipher 25.10 25.10
u_mult 65.59 82.35 30.00 50.00 100.00

Line Coverage for Module : flash_phy_scramble
Line No.TotalCoveredPercent
TOTAL1313100.00
ALWAYS4144100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN7011100.00
ALWAYS7744100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
43 1 1
44 1 1
==> MISSING_ELSE
48 1 1
51 1 1
70 1 1
77 1 1
78 1 1
79 1 1
80 1 1
==> MISSING_ELSE
105 1 1
108 1 1


Cond Coverage for Module : flash_phy_scramble
TotalCoveredPercent
Conditions18527.78
Logical18527.78
Non-Logical00
Event00

 LINE       43
 EXPRESSION (((!calc_req_i)) || (calc_req_i && calc_ack_o))
             -------1-------    -------------2------------
-1--2-StatusTests
00Not Covered
01Not Covered
10CoveredT1,T2,T3

 LINE       43
 SUB-EXPRESSION (calc_req_i && calc_ack_o)
                 -----1----    -----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       48
 EXPRESSION (addr_key_sel ? rand_addr_key_i : addr_key_i)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       79
 EXPRESSION (((!op_req_i)) || (op_req_i && op_ack_o))
             ------1------    -----------2----------
-1--2-StatusTests
00Not Covered
01Not Covered
10CoveredT1,T2,T3

 LINE       79
 SUB-EXPRESSION (op_req_i && op_ack_o)
                 ----1---    ----2---
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       105
 EXPRESSION (dec ? data : scrambled_data_i)
             -1-
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       108
 EXPRESSION (dec ? plain_data_i : data)
             -1-
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Branch Coverage for Module : flash_phy_scramble
Line No.TotalCoveredPercent
Branches 12 7 58.33
TERNARY 48 2 1 50.00
TERNARY 105 2 1 50.00
TERNARY 108 2 1 50.00
IF 41 3 2 66.67
IF 77 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 48 (addr_key_sel) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 105 (dec) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 108 (dec) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 41 if ((!rst_ni)) -2-: 43 if (((!calc_req_i) || (calc_req_i && calc_ack_o)))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Not Covered


LineNo. Expression -1-: 77 if ((!rst_ni)) -2-: 79 if (((!op_req_i) || (op_req_i && op_ack_o)))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Not Covered

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble
Line No.TotalCoveredPercent
TOTAL1313100.00
ALWAYS4144100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN7011100.00
ALWAYS7744100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
43 1 1
44 1 1
==> MISSING_ELSE
48 1 1
51 1 1
70 1 1
77 1 1
78 1 1
79 1 1
80 1 1
==> MISSING_ELSE
105 1 1
108 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble
TotalCoveredPercent
Conditions18527.78
Logical18527.78
Non-Logical00
Event00

 LINE       43
 EXPRESSION (((!calc_req_i)) || (calc_req_i && calc_ack_o))
             -------1-------    -------------2------------
-1--2-StatusTests
00Not Covered
01Not Covered
10CoveredT1,T2,T3

 LINE       43
 SUB-EXPRESSION (calc_req_i && calc_ack_o)
                 -----1----    -----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       48
 EXPRESSION (addr_key_sel ? rand_addr_key_i : addr_key_i)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       79
 EXPRESSION (((!op_req_i)) || (op_req_i && op_ack_o))
             ------1------    -----------2----------
-1--2-StatusTests
00Not Covered
01Not Covered
10CoveredT1,T2,T3

 LINE       79
 SUB-EXPRESSION (op_req_i && op_ack_o)
                 ----1---    ----2---
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       105
 EXPRESSION (dec ? data : scrambled_data_i)
             -1-
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       108
 EXPRESSION (dec ? plain_data_i : data)
             -1-
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble
Line No.TotalCoveredPercent
Branches 12 7 58.33
TERNARY 48 2 1 50.00
TERNARY 105 2 1 50.00
TERNARY 108 2 1 50.00
IF 41 3 2 66.67
IF 77 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 48 (addr_key_sel) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 105 (dec) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 108 (dec) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 41 if ((!rst_ni)) -2-: 43 if (((!calc_req_i) || (calc_req_i && calc_ack_o)))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Not Covered


LineNo. Expression -1-: 77 if ((!rst_ni)) -2-: 79 if (((!op_req_i) || (op_req_i && op_ack_o)))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Not Covered

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble
Line No.TotalCoveredPercent
TOTAL1313100.00
ALWAYS4144100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN7011100.00
ALWAYS7744100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
43 1 1
44 1 1
==> MISSING_ELSE
48 1 1
51 1 1
70 1 1
77 1 1
78 1 1
79 1 1
80 1 1
==> MISSING_ELSE
105 1 1
108 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble
TotalCoveredPercent
Conditions18527.78
Logical18527.78
Non-Logical00
Event00

 LINE       43
 EXPRESSION (((!calc_req_i)) || (calc_req_i && calc_ack_o))
             -------1-------    -------------2------------
-1--2-StatusTests
00Not Covered
01Not Covered
10CoveredT1,T2,T3

 LINE       43
 SUB-EXPRESSION (calc_req_i && calc_ack_o)
                 -----1----    -----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       48
 EXPRESSION (addr_key_sel ? rand_addr_key_i : addr_key_i)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       79
 EXPRESSION (((!op_req_i)) || (op_req_i && op_ack_o))
             ------1------    -----------2----------
-1--2-StatusTests
00Not Covered
01Not Covered
10CoveredT1,T2,T3

 LINE       79
 SUB-EXPRESSION (op_req_i && op_ack_o)
                 ----1---    ----2---
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       105
 EXPRESSION (dec ? data : scrambled_data_i)
             -1-
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       108
 EXPRESSION (dec ? plain_data_i : data)
             -1-
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble
Line No.TotalCoveredPercent
Branches 12 7 58.33
TERNARY 48 2 1 50.00
TERNARY 105 2 1 50.00
TERNARY 108 2 1 50.00
IF 41 3 2 66.67
IF 77 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 48 (addr_key_sel) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 105 (dec) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 108 (dec) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 41 if ((!rst_ni)) -2-: 43 if (((!calc_req_i) || (calc_req_i && calc_ack_o)))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Not Covered


LineNo. Expression -1-: 77 if ((!rst_ni)) -2-: 79 if (((!op_req_i) || (op_req_i && op_ack_o)))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Not Covered

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%