Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	50.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_eflash_tl_agent.cov::m_tl_a_chan_cov_cg	0.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_eflash_tl_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_eflash_tl_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	134	0	0.00
Crosses	3	3	0	0.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_eflash_tl_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	1	0	0.00	100	1	1	0
cp_opcode	3	3	0	0.00	100	1	1	0
cp_size	1	1	0	0.00	100	1	1	0
cp_source	129	129	0	0.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_eflash_tl_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	3	0	0.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	1	0	0.00

User Defined Bins for cp_mask

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
all_enables	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Excluded

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for cp_opcode

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
values_4	0	1	1
values_0	0	1	1
values_1	0	1	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	1	0	0.00

User Defined Bins for cp_size

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
biggest_size	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Excluded

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	129	0	0.00

User Defined Bins for cp_source

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
valid_sources_00	0	1	1
valid_sources_01	0	1	1
valid_sources_02	0	1	1
valid_sources_03	0	1	1
valid_sources_04	0	1	1
valid_sources_05	0	1	1
valid_sources_06	0	1	1
valid_sources_07	0	1	1
valid_sources_08	0	1	1
valid_sources_09	0	1	1
valid_sources_0a	0	1	1
valid_sources_0b	0	1	1
valid_sources_0c	0	1	1
valid_sources_0d	0	1	1
valid_sources_0e	0	1	1
valid_sources_0f	0	1	1
valid_sources_10	0	1	1
valid_sources_11	0	1	1
valid_sources_12	0	1	1
valid_sources_13	0	1	1
valid_sources_14	0	1	1
valid_sources_15	0	1	1
valid_sources_16	0	1	1
valid_sources_17	0	1	1
valid_sources_18	0	1	1
valid_sources_19	0	1	1
valid_sources_1a	0	1	1
valid_sources_1b	0	1	1
valid_sources_1c	0	1	1
valid_sources_1d	0	1	1
valid_sources_1e	0	1	1
valid_sources_1f	0	1	1
valid_sources_20	0	1	1
valid_sources_21	0	1	1
valid_sources_22	0	1	1
valid_sources_23	0	1	1
valid_sources_24	0	1	1
valid_sources_25	0	1	1
valid_sources_26	0	1	1
valid_sources_27	0	1	1
valid_sources_28	0	1	1
valid_sources_29	0	1	1
valid_sources_2a	0	1	1
valid_sources_2b	0	1	1
valid_sources_2c	0	1	1
valid_sources_2d	0	1	1
valid_sources_2e	0	1	1
valid_sources_2f	0	1	1
valid_sources_30	0	1	1
valid_sources_31	0	1	1
valid_sources_32	0	1	1
valid_sources_33	0	1	1
valid_sources_34	0	1	1
valid_sources_35	0	1	1
valid_sources_36	0	1	1
valid_sources_37	0	1	1
valid_sources_38	0	1	1
valid_sources_39	0	1	1
valid_sources_3a	0	1	1
valid_sources_3b	0	1	1
valid_sources_3c	0	1	1
valid_sources_3d	0	1	1
valid_sources_3e	0	1	1
valid_sources_3f	0	1	1
valid_sources_40	0	1	1
valid_sources_41	0	1	1
valid_sources_42	0	1	1
valid_sources_43	0	1	1
valid_sources_44	0	1	1
valid_sources_45	0	1	1
valid_sources_46	0	1	1
valid_sources_47	0	1	1
valid_sources_48	0	1	1
valid_sources_49	0	1	1
valid_sources_4a	0	1	1
valid_sources_4b	0	1	1
valid_sources_4c	0	1	1
valid_sources_4d	0	1	1
valid_sources_4e	0	1	1
valid_sources_4f	0	1	1
valid_sources_50	0	1	1
valid_sources_51	0	1	1
valid_sources_52	0	1	1
valid_sources_53	0	1	1
valid_sources_54	0	1	1
valid_sources_55	0	1	1
valid_sources_56	0	1	1
valid_sources_57	0	1	1
valid_sources_58	0	1	1
valid_sources_59	0	1	1
valid_sources_5a	0	1	1
valid_sources_5b	0	1	1
valid_sources_5c	0	1	1
valid_sources_5d	0	1	1
valid_sources_5e	0	1	1
valid_sources_5f	0	1	1
valid_sources_60	0	1	1
valid_sources_61	0	1	1
valid_sources_62	0	1	1
valid_sources_63	0	1	1
valid_sources_64	0	1	1
valid_sources_65	0	1	1
valid_sources_66	0	1	1
valid_sources_67	0	1	1
valid_sources_68	0	1	1
valid_sources_69	0	1	1
valid_sources_6a	0	1	1
valid_sources_6b	0	1	1
valid_sources_6c	0	1	1
valid_sources_6d	0	1	1
valid_sources_6e	0	1	1
valid_sources_6f	0	1	1
valid_sources_70	0	1	1
valid_sources_71	0	1	1
valid_sources_72	0	1	1
valid_sources_73	0	1	1
valid_sources_74	0	1	1
valid_sources_75	0	1	1
valid_sources_76	0	1	1
valid_sources_77	0	1	1
valid_sources_78	0	1	1
valid_sources_79	0	1	1
valid_sources_7a	0	1	1
valid_sources_7b	0	1	1
valid_sources_7c	0	1	1
valid_sources_7d	0	1	1
valid_sources_7e	0	1	1
valid_sources_7f	0	1	1
valid_sources_80	0	1	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	3	0	0.00	3

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Uncovered bins

cp_opcode	cp_mask	cp_size	COUNT	AT LEAST	NUMBER
*	*	*	--	--	3

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1265374	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	811576	1		T1	1026		T2	54772		T3	1215

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values_4	1634433	1		T1	786		T2	107498		T3	1194
values_0	219881	1		T1	380		T2	577		T3	440
values_1	222636	1		T1	366		T2	606		T3	446

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	926433	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	1150517	1		T1	1162		T2	64778		T3	1429

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources_00	7585	1		T1	11		T2	448		T3	4
valid_sources_01	7446	1		T1	14		T2	435		T3	8
valid_sources_02	7024	1		T1	6		T2	457		T3	14
valid_sources_03	8622	1		T1	3		T2	441		T3	13
valid_sources_04	7641	1		T1	11		T2	460		T3	7
valid_sources_05	7357	1		T1	1		T2	470		T3	11
valid_sources_06	8041	1		T1	4		T2	451		T3	8
valid_sources_07	8715	1		T1	4		T2	416		T3	7
valid_sources_08	7915	1		T1	3		T2	419		T3	7
valid_sources_09	8247	1		T1	5		T2	418		T3	10
valid_sources_0a	8202	1		T1	6		T2	436		T3	11
valid_sources_0b	7663	1		T1	7		T2	403		T3	6
valid_sources_0c	7331	1		T1	3		T2	467		T3	10
valid_sources_0d	7751	1		T1	7		T2	413		T3	6
valid_sources_0e	7267	1		T1	11		T2	377		T3	10
valid_sources_0f	8258	1		T1	3		T2	406		T3	10
valid_sources_10	7655	1		T1	1		T2	411		T3	10
valid_sources_11	7955	1		T1	6		T2	409		T3	7
valid_sources_12	8262	1		T1	14		T2	424		T3	16
valid_sources_13	7355	1		T1	12		T2	404		T3	12
valid_sources_14	8876	1		T1	2		T2	429		T3	6
valid_sources_15	8237	1		T1	1		T2	477		T3	5
valid_sources_16	7851	1		T1	5		T2	399		T3	5
valid_sources_17	19388	1		T1	3		T2	463		T3	11
valid_sources_18	7644	1		T1	6		T2	446		T3	6
valid_sources_19	7219	1		T1	14		T2	403		T3	5
valid_sources_1a	8118	1		T1	1		T2	452		T3	11
valid_sources_1b	8200	1		T1	4		T2	409		T3	6
valid_sources_1c	7913	1		T1	4		T2	382		T3	7
valid_sources_1d	7764	1		T1	10		T2	469		T3	6
valid_sources_1e	7306	1		T1	1		T2	427		T3	6
valid_sources_1f	9221	1		T1	14		T2	452		T3	7
valid_sources_20	7954	1		T1	23		T2	375		T3	12
valid_sources_21	7506	1		T1	4		T2	429		T3	7
valid_sources_22	7224	1		T1	5		T2	412		T3	5
valid_sources_23	8316	1		T1	4		T2	408		T3	9
valid_sources_24	7385	1		T1	8		T2	438		T3	12
valid_sources_25	7990	1		T1	5		T2	426		T3	7
valid_sources_26	8534	1		T1	2		T2	454		T3	7
valid_sources_27	7723	1		T1	5		T2	448		T3	11
valid_sources_28	8389	1		T1	9		T2	458		T3	1
valid_sources_29	7908	1		T1	1		T2	438		T3	10
valid_sources_2a	8172	1		T1	5		T2	433		T3	2
valid_sources_2b	7623	1		T1	1		T2	394		T3	5
valid_sources_2c	8361	1		T2	447		T3	9		T5	4
valid_sources_2d	7988	1		T1	7		T2	445		T3	16
valid_sources_2e	7490	1		T1	1		T2	437		T3	12
valid_sources_2f	7841	1		T1	7		T2	438		T3	10
valid_sources_30	7772	1		T2	392		T3	7		T5	1
valid_sources_31	8023	1		T1	10		T2	398		T3	5
valid_sources_32	8442	1		T2	394		T3	9		T4	1
valid_sources_33	7854	1		T1	17		T2	412		T3	9
valid_sources_34	8191	1		T1	11		T2	398		T3	3
valid_sources_35	7881	1		T1	17		T2	419		T3	7
valid_sources_36	7759	1		T2	420		T3	7		T5	1
valid_sources_37	7618	1		T1	9		T2	437		T3	1
valid_sources_38	8284	1		T1	1		T2	384		T3	9
valid_sources_39	12686	1		T1	6		T2	395		T3	4
valid_sources_3a	7532	1		T1	7		T2	474		T3	7
valid_sources_3b	7986	1		T1	5		T2	400		T3	7
valid_sources_3c	8791	1		T1	6		T2	416		T3	5
valid_sources_3d	7466	1		T1	20		T2	421		T3	3
valid_sources_3e	7988	1		T2	399		T3	5		T5	1
valid_sources_3f	7414	1		T1	5		T2	422		T3	5
valid_sources_40	7894	1		T1	9		T2	447		T3	7
valid_sources_41	7708	1		T1	1		T2	445		T3	9
valid_sources_42	11859	1		T1	9		T2	444		T3	12
valid_sources_43	7555	1		T1	15		T2	437		T3	1
valid_sources_44	8082	1		T1	4		T2	441		T3	6
valid_sources_45	7643	1		T1	2		T2	425		T3	9
valid_sources_46	7463	1		T1	6		T2	410		T3	5
valid_sources_47	7440	1		T1	5		T2	438		T3	7
valid_sources_48	7429	1		T1	11		T2	417		T3	6
valid_sources_49	7635	1		T1	12		T2	370		T3	10
valid_sources_4a	7958	1		T1	9		T2	429		T3	5
valid_sources_4b	7161	1		T1	6		T2	450		T3	13
valid_sources_4c	7887	1		T2	430		T3	14		T5	2
valid_sources_4d	7744	1		T1	5		T2	392		T3	18
valid_sources_4e	7794	1		T1	12		T2	407		T3	12
valid_sources_4f	10765	1		T1	6		T2	430		T3	9
valid_sources_50	7916	1		T1	8		T2	393		T3	10
valid_sources_51	7814	1		T1	7		T2	467		T3	9
valid_sources_52	7740	1		T1	3		T2	424		T3	13
valid_sources_53	8344	1		T2	425		T3	4		T4	2
valid_sources_54	7466	1		T1	7		T2	427		T3	6
valid_sources_55	7192	1		T2	429		T3	16		T5	3
valid_sources_56	8062	1		T1	6		T2	395		T3	9
valid_sources_57	7649	1		T1	14		T2	429		T3	10
valid_sources_58	6897	1		T1	1		T2	435		T3	4
valid_sources_59	7793	1		T1	7		T2	401		T3	6
valid_sources_5a	7809	1		T2	421		T3	10		T4	1
valid_sources_5b	7485	1		T1	4		T2	445		T3	8
valid_sources_5c	8198	1		T1	8		T2	448		T3	9
valid_sources_5d	7484	1		T1	7		T2	390		T3	13
valid_sources_5e	8198	1		T1	4		T2	439		T3	6
valid_sources_5f	7005	1		T1	1		T2	417		T3	8
valid_sources_60	7400	1		T1	11		T2	404		T3	9
valid_sources_61	8009	1		T1	6		T2	420		T3	3
valid_sources_62	7290	1		T1	5		T2	442		T3	6
valid_sources_63	7608	1		T1	3		T2	430		T3	6
valid_sources_64	7447	1		T1	3		T2	426		T3	9
valid_sources_65	8422	1		T1	5		T2	379		T3	7
valid_sources_66	7703	1		T2	438		T3	5		T4	1
valid_sources_67	7496	1		T1	8		T2	435		T3	7
valid_sources_68	8292	1		T1	3		T2	451		T3	6
valid_sources_69	8727	1		T1	7		T2	412		T3	7
valid_sources_6a	7794	1		T1	4		T2	402		T3	4
valid_sources_6b	7418	1		T1	13		T2	421		T3	6
valid_sources_6c	7930	1		T1	4		T2	374		T3	12
valid_sources_6d	7885	1		T1	1		T2	415		T3	5
valid_sources_6e	7833	1		T1	3		T2	414		T3	9
valid_sources_6f	7863	1		T1	14		T2	416		T3	12
valid_sources_70	7861	1		T1	20		T2	437		T3	4
valid_sources_71	7465	1		T1	16		T2	439		T3	9
valid_sources_72	6827	1		T1	32		T2	429		T3	7
valid_sources_73	7636	1		T1	9		T2	415		T3	11
valid_sources_74	7578	1		T1	10		T2	400		T3	5
valid_sources_75	7108	1		T1	3		T2	399		T3	15
valid_sources_76	7517	1		T1	1		T2	390		T3	11
valid_sources_77	8241	1		T1	4		T2	412		T3	9
valid_sources_78	8473	1		T1	10		T2	420		T3	16
valid_sources_79	7526	1		T1	1		T2	416		T3	9
valid_sources_7a	12744	1		T1	9		T2	457		T3	4
valid_sources_7b	7628	1		T2	442		T3	8		T4	3
valid_sources_7c	8180	1		T1	4		T2	379		T3	7
valid_sources_7d	7779	1		T1	8		T2	447		T3	5
valid_sources_7e	8540	1		T1	8		T2	406		T3	7
valid_sources_7f	7840	1		T1	3		T2	388		T3	4
valid_sources_80	7358	1		T1	7		T2	385		T3	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values_4

all_enables

biggest_size

644085

1

T1

502

T2

53931

T3

648

values_0

all_enables

biggest_size

101755

1

T1

276

T2

421

T3

303

values_1

all_enables

biggest_size

65736

1

T1

248

T2

420

T3

264