Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
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Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
35.29 35.29 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block] 35.29 1 100 1 64 64




Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
35.29 1 100 1 64 64




Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 11 3 8 72.73
Crosses 40 30 10 25.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 5 0 5 100.00 100 1 1 0
cp_tl_intg_err_type 4 3 1 25.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 40 30 10 25.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values_0 231825 1 T1 94 T2 20181 T3 199
values_1 738083 1 T1 209 T2 23338 T3 350
values_2 198999 1 T1 128 T2 6943 T3 196
values_3 117846 1 T1 75 T2 3447 T3 120
values_4 812491 1 T1 1026 T2 54772 T3 1215



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 3 1 25.00


Automatically Generated Bins for cp_tl_intg_err_type

Uncovered bins
NAMECOUNTAT LEASTNUMBER
auto_TlIntgErrCmd 0 1 1
auto_TlIntgErrData 0 1 1
auto_TlIntgErrBoth 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto_TlIntgErrNone 2099244 1 T1 1532 T2 108681 T3 2080



Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1637651 1 T1 786 T2 107498 T3 1194
auto[1] 461593 1 T1 746 T2 1183 T3 886



Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 40 30 10 25.00 30


Automatically Generated Cross Bins for cr_all

Element holes
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTNUMBER
[auto_TlIntgErrCmd , auto_TlIntgErrData , auto_TlIntgErrBoth] * * -- -- 30


Covered bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto_TlIntgErrNone values_0 auto[0] 230034 1 T1 94 T2 20181 T3 199
auto_TlIntgErrNone values_0 auto[1] 1791 1 T16 45 T17 148 T18 87
auto_TlIntgErrNone values_1 auto[0] 636566 1 T1 133 T2 23215 T3 256
auto_TlIntgErrNone values_1 auto[1] 101517 1 T1 76 T2 123 T3 94
auto_TlIntgErrNone values_2 auto[0] 82140 1 T1 39 T2 6815 T3 63
auto_TlIntgErrNone values_2 auto[1] 116859 1 T1 89 T2 128 T3 133
auto_TlIntgErrNone values_3 auto[0] 44594 1 T1 18 T2 3356 T3 28
auto_TlIntgErrNone values_3 auto[1] 73252 1 T1 57 T2 91 T3 92
auto_TlIntgErrNone values_4 auto[0] 644317 1 T1 502 T2 53931 T3 648
auto_TlIntgErrNone values_4 auto[1] 168174 1 T1 524 T2 841 T3 567

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