Group : dv_lib_pkg::bit_toggle_cg_wrap::bit_toggle_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : dv_lib_pkg::bit_toggle_cg_wrap::bit_toggle_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 44.64 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv

14 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
uvm_test_top.env.m_eflash_tl_agent.cov::PutFullData_mask_not_match_size 0.00 1 100 1 64 64
uvm_test_top.env.m_eflash_tl_agent.cov::addr_not_align_mask 0.00 1 100 1 64 64
uvm_test_top.env.m_eflash_tl_agent.cov::addr_not_align_size 0.00 1 100 1 64 64
uvm_test_top.env.m_eflash_tl_agent.cov::invalid_a_opcode 0.00 1 100 1 64 64
uvm_test_top.env.m_eflash_tl_agent.cov::m_outstanding_item_w_same_addr_cov_obj 0.00 1 100 1 64 64
uvm_test_top.env.m_eflash_tl_agent.cov::mask_not_in_enabled_lanes 0.00 1 100 1 64 64
uvm_test_top.env.m_eflash_tl_agent.cov::size_over_max 0.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::m_outstanding_item_w_same_addr_cov_obj 25.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::PutFullData_mask_not_match_size 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::addr_not_align_mask 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::addr_not_align_size 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::invalid_a_opcode 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::mask_not_in_enabled_lanes 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::size_over_max 100.00 1 100 1 64 64




Group Instance : uvm_test_top.env.m_eflash_tl_agent.cov::PutFullData_mask_not_match_size
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
0.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_eflash_tl_agent.cov::PutFullData_mask_not_match_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 4 0 0.00


Variables for Group Instance uvm_test_top.env.m_eflash_tl_agent.cov::PutFullData_mask_not_match_size
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 2 0 0.00 100 1 1 0
cp_value 2 2 0 0.00 100 1 1 2



Group Instance : uvm_test_top.env.m_eflash_tl_agent.cov::addr_not_align_mask
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
0.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_eflash_tl_agent.cov::addr_not_align_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 4 0 0.00


Variables for Group Instance uvm_test_top.env.m_eflash_tl_agent.cov::addr_not_align_mask
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 2 0 0.00 100 1 1 0
cp_value 2 2 0 0.00 100 1 1 2



Group Instance : uvm_test_top.env.m_eflash_tl_agent.cov::addr_not_align_size
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
0.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_eflash_tl_agent.cov::addr_not_align_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 4 0 0.00


Variables for Group Instance uvm_test_top.env.m_eflash_tl_agent.cov::addr_not_align_size
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 2 0 0.00 100 1 1 0
cp_value 2 2 0 0.00 100 1 1 2



Group Instance : uvm_test_top.env.m_eflash_tl_agent.cov::invalid_a_opcode
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
0.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_eflash_tl_agent.cov::invalid_a_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 4 0 0.00


Variables for Group Instance uvm_test_top.env.m_eflash_tl_agent.cov::invalid_a_opcode
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 2 0 0.00 100 1 1 0
cp_value 2 2 0 0.00 100 1 1 2



Group Instance : uvm_test_top.env.m_eflash_tl_agent.cov::m_outstanding_item_w_same_addr_cov_obj
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
0.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_eflash_tl_agent.cov::m_outstanding_item_w_same_addr_cov_obj

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 4 0 0.00


Variables for Group Instance uvm_test_top.env.m_eflash_tl_agent.cov::m_outstanding_item_w_same_addr_cov_obj
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 2 0 0.00 100 1 1 0
cp_value 2 2 0 0.00 100 1 1 2



Group Instance : uvm_test_top.env.m_eflash_tl_agent.cov::mask_not_in_enabled_lanes
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
0.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_eflash_tl_agent.cov::mask_not_in_enabled_lanes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 4 0 0.00


Variables for Group Instance uvm_test_top.env.m_eflash_tl_agent.cov::mask_not_in_enabled_lanes
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 2 0 0.00 100 1 1 0
cp_value 2 2 0 0.00 100 1 1 2



Group Instance : uvm_test_top.env.m_eflash_tl_agent.cov::size_over_max
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
0.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_eflash_tl_agent.cov::size_over_max

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 4 0 0.00


Variables for Group Instance uvm_test_top.env.m_eflash_tl_agent.cov::size_over_max
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 2 0 0.00 100 1 1 0
cp_value 2 2 0 0.00 100 1 1 2



Group Instance : uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::m_outstanding_item_w_same_addr_cov_obj
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
25.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::m_outstanding_item_w_same_addr_cov_obj

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 3 1 25.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::m_outstanding_item_w_same_addr_cov_obj
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 2 0 0.00 100 1 1 0
cp_value 2 1 1 50.00 100 1 1 2



Group Instance : uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::PutFullData_mask_not_match_size
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::PutFullData_mask_not_match_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::PutFullData_mask_not_match_size
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::addr_not_align_mask
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::addr_not_align_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::addr_not_align_mask
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::addr_not_align_size
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::addr_not_align_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::addr_not_align_size
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::invalid_a_opcode
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::invalid_a_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::invalid_a_opcode
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::mask_not_in_enabled_lanes
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::mask_not_in_enabled_lanes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::mask_not_in_enabled_lanes
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::size_over_max
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::size_over_max

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_flash_ctrl_core_reg_block.cov::size_over_max
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 2 0 0.00


User Defined Bins for cp_transitions

Uncovered bins
NAMECOUNTAT LEASTNUMBER
falling 0 1 1
rising 0 1 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[0] - auto[1]] -- -- 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 2 0 0.00


User Defined Bins for cp_transitions

Uncovered bins
NAMECOUNTAT LEASTNUMBER
falling 0 1 1
rising 0 1 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[0] - auto[1]] -- -- 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 2 0 0.00


User Defined Bins for cp_transitions

Uncovered bins
NAMECOUNTAT LEASTNUMBER
falling 0 1 1
rising 0 1 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[0] - auto[1]] -- -- 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 2 0 0.00


User Defined Bins for cp_transitions

Uncovered bins
NAMECOUNTAT LEASTNUMBER
falling 0 1 1
rising 0 1 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[0] - auto[1]] -- -- 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 2 0 0.00


User Defined Bins for cp_transitions

Uncovered bins
NAMECOUNTAT LEASTNUMBER
falling 0 1 1
rising 0 1 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[0] - auto[1]] -- -- 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 2 0 0.00


User Defined Bins for cp_transitions

Uncovered bins
NAMECOUNTAT LEASTNUMBER
falling 0 1 1
rising 0 1 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[0] - auto[1]] -- -- 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 2 0 0.00


User Defined Bins for cp_transitions

Uncovered bins
NAMECOUNTAT LEASTNUMBER
falling 0 1 1
rising 0 1 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[0] - auto[1]] -- -- 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 2 0 0.00


User Defined Bins for cp_transitions

Uncovered bins
NAMECOUNTAT LEASTNUMBER
falling 0 1 1
rising 0 1 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2099244 1 T1 1532 T2 108681 T3 2080


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
falling 4327 1 T16 104 T17 380 T18 186
rising 4331 1 T16 105 T17 381 T18 186



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 16098 1 T16 503 T17 937 T18 1069
auto[1] 6196 1 T16 129 T17 634 T18 220


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
falling 4844 1 T16 143 T17 287 T18 300
rising 4838 1 T16 143 T17 287 T18 301



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 14872 1 T16 412 T17 1209 T18 754
auto[1] 7422 1 T16 220 T17 362 T18 535


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
falling 4844 1 T16 143 T17 287 T18 300
rising 4838 1 T16 143 T17 287 T18 301



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 14872 1 T16 412 T17 1209 T18 754
auto[1] 7422 1 T16 220 T17 362 T18 535


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
falling 4159 1 T16 165 T17 197 T18 313
rising 4156 1 T16 165 T17 197 T18 314



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 16446 1 T16 357 T17 1357 T18 768
auto[1] 5848 1 T16 275 T17 214 T18 521


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
falling 4918 1 T16 122 T17 391 T18 261
rising 4921 1 T16 122 T17 391 T18 260



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 14533 1 T16 447 T17 886 T18 945
auto[1] 7761 1 T16 185 T17 685 T18 344


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
falling 4433 1 T16 119 T17 318 T18 254
rising 4433 1 T16 119 T17 318 T18 254



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 16188 1 T16 483 T17 1153 T18 937
auto[1] 6106 1 T16 149 T17 418 T18 352

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%