Unified Coverage Report :: Module :: tlul_sram_byte

Module : tlul_sram_byte

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
66.90	97.67	55.00		0.00	81.82	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_sram_byte	55.72	79.07	45.00		0.00	54.55	100.00
tb.dut.u_tl_adapter_eflash.u_sram_byte	58.40	88.37	40.00		0.00	63.64	100.00
tb.dut.u_to_prog_fifo.u_sram_byte	64.99	97.67	50.00		0.00	77.27	100.00
tb.dut.u_to_rd_fifo.u_sram_byte	64.99	97.67	50.00		0.00	77.27	100.00

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_sram_byte

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
55.72	79.07	45.00		0.00	54.55	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.58	83.15	45.83		0.00	52.50	71.43

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
62.46	63.16	33.33			70.00	83.33	u_cfg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_intg_gen	100.00	100.00					100.00
u_sync_fifo	60.16	80.65	50.00			50.00	60.00

---

Module Instance : tb.dut.u_tl_adapter_eflash.u_sram_byte

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
58.40	88.37	40.00		0.00	63.64	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
51.20	85.39	41.67		0.00	57.50	71.43

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
68.44	93.22	22.22			75.00	83.33	u_tl_adapter_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_intg_gen	93.33	86.67					100.00
u_sync_fifo	60.16	80.65	50.00			50.00	60.00

---

Module Instance : tb.dut.u_to_prog_fifo.u_sram_byte

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
64.99	97.67	50.00		0.00	77.27	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
55.71	92.13	50.00		0.00	65.00	71.43

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.69	100.00	69.44			90.00	83.33	u_to_prog_fifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_intg_gen	100.00	100.00					100.00
u_sync_fifo	60.16	80.65	50.00			50.00	60.00

---

Module Instance : tb.dut.u_to_rd_fifo.u_sram_byte

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
64.99	97.67	50.00		0.00	77.27	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
55.71	92.13	50.00		0.00	65.00	71.43

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.50	100.00	75.00			95.00	100.00	u_to_rd_fifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_intg_gen	100.00	100.00					100.00
u_sync_fifo	60.16	80.65	50.00			50.00	60.00

Line Coverage for Module : tlul_sram_byte

	Line No.	Total	Covered	Percent
TOTAL		43	42	97.67
ALWAYS	61	3	3	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	83	0	0
ALWAYS	87	6	6	100.00
ALWAYS	116	22	22	100.00
ALWAYS	243	2	2	100.00
ALWAYS	257	0	0
ALWAYS	257	2	2	100.00
CONT_ASSIGN	286	1	0	0.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	346	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
61	1	1
62	1	1
64	1	1
78	1	1
79	1	1
80	1	1
81	1	1
82	1	1
83		unreachable
87	1	1
88	1	1
89	1	1
90	1	1
91	1	1
92	1	1
			MISSING_ELSE
116	1	1
117	1	1
118	1	1
119	1	1
121	1	1
135	1	1
136		unreachable
137	1	1
138		unreachable
			MISSING_ELSE
147	1	1
148	1	1
149	1	1
151	1	1
152	1	1
			MISSING_ELSE
			MISSING_ELSE
158	1	1
159	1	1
161	1	1
162	1	1
			MISSING_ELSE
167	1	1
168	1	1
170	1	1
171	1	1
			MISSING_ELSE
185	1	1
186	1	1
243	1	1
244	1	1
			MISSING_ELSE
257	1	1
258	1	1
286	0	1
339	1	1
346	1	1

---

Cond Coverage for Module : tlul_sram_byte

	Total	Covered	Percent
Conditions	20	11	55.00
Logical	20	11	55.00
Non-Logical	0	0
Event	0	0

 LINE       89
 EXPRESSION (a_ack && ((!d_ack)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       91
 EXPRESSION (((!a_ack)) && d_ack)
             -----1----    --2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       135
 EXPRESSION (byte_wr_txn && a_ack_q)
             -----1-----    ---2---

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Unreachable
1	1	Unreachable

 LINE       138
 EXPRESSION ((txn_cnt == '0) ? StWaitRd : StFlush)
             -------1-------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       186
 EXPRESSION (d_ack ? StPassThru : StWait)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       267
 EXPRESSION (wr_phase ? PutFullData : Get)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       267
 EXPRESSION (wr_phase ? held_data.a_param : tl_i.a_param)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       267
 EXPRESSION (wr_phase ? held_data.a_source : tl_i.a_source)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       267
 EXPRESSION 
 Number  Term
      1  wr_phase ? ({held_data.a_address[(top_pkg::TL_AW - 1):AccessSize], {AccessSize {1'b0}}}) : ({tl_i.a_address[(top_pkg::TL_AW - 1):AccessSize], {AccessSize {1'b0}}}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       267
 EXPRESSION (wr_phase ? combined_data : tl_i.a_data)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       267
 EXPRESSION (wr_phase ? held_data.a_user : tl_i.a_user)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

FSM Coverage for Module : tlul_sram_byte

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	1	20.00	(Not included in score)
Transitions	9	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StFlush	138	Not Covered
StPassThru	62	Covered	T1,T2,T3
StWait	171	Not Covered
StWaitRd	138	Not Covered
StWriteCmd	152	Not Covered

transitions	Line No.	Covered	Tests
StFlush->StPassThru	62	Not Covered
StFlush->StWriteCmd	152	Not Covered
StPassThru->StFlush	138	Not Covered
StPassThru->StWaitRd	138	Not Covered
StWait->StPassThru	62	Not Covered
StWaitRd->StPassThru	62	Not Covered
StWaitRd->StWriteCmd	162	Not Covered
StWriteCmd->StPassThru	62	Not Covered
StWriteCmd->StWait	171	Not Covered

---

Branch Coverage for Module : tlul_sram_byte

	Line No.	Total	Covered	Percent
Branches		22	18	81.82
IF	61	2	2	100.00
IF	87	4	4	100.00
CASE	121	14	10	71.43
IF	243	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	61	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	87	if ((!rst_ni))
-2-:	89	if ((a_ack && (!d_ack)))
-3-:	91	if (((!a_ack) && d_ack))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	121	case (state_q)
-2-:	135	if ((byte_wr_txn && a_ack_q))
-3-:	137	if (byte_req_ack)
-4-:	138	((txn_cnt == '0)) ? 
-5-:	148	if ((txn_cnt == 4'b1))
-6-:	151	if (sram_d_ack)
-7-:	161	if (sram_d_ack)
-8-:	170	if (sram_a_ack)
-9-:	186	(d_ack) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
StPassThru	1	-	-	-	-	-	-	-	Not Covered
StPassThru	0	1	1	-	-	-	-	-	Not Covered
StPassThru	0	1	0	-	-	-	-	-	Not Covered
StPassThru	0	0	-	-	-	-	-	-	Covered	T1,T2,T3
StFlush	-	-	-	1	1	-	-	-	Covered	T1,T2,T3
StFlush	-	-	-	1	0	-	-	-	Covered	T1,T2,T3
StFlush	-	-	-	0	-	-	-	-	Covered	T1,T2,T3
StWaitRd	-	-	-	-	-	1	-	-	Covered	T1,T2,T3
StWaitRd	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
StWriteCmd	-	-	-	-	-	-	1	-	Covered	T1,T2,T3
StWriteCmd	-	-	-	-	-	-	0	-	Covered	T1,T2,T3
StWait	-	-	-	-	-	-	-	1	Not Covered
StWait	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	243	if (sram_d_ack)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : tlul_sram_byte

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_non_intg_asserts.StableSignals_A	9609808	9593656	0	0

gen_non_intg_asserts.StableSignals_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9609808	9593656	0	0
T1	66176	65928	0	0
T2	873024	872720	0	0
T3	60512	60224	0	0
T4	9772	9484	0	0
T5	21240	20860	0	0
T6	47212	46916	0	0
T7	58264	57968	0	0
T8	1070368	1070040	0	0
T9	2164520	2164188	0	0
T10	603940	603688	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_sram_byte

	Line No.	Total	Covered	Percent
TOTAL		43	34	79.07
ALWAYS	61	3	3	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	0	0.00
CONT_ASSIGN	83	0	0
ALWAYS	87	6	4	66.67
ALWAYS	116	22	19	86.36
ALWAYS	243	2	1	50.00
ALWAYS	257	0	0
ALWAYS	257	2	2	100.00
CONT_ASSIGN	286	1	0	0.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	346	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
61	1	1
62	1	1
64	1	1
78	1	1
79	1	1
80	1	1
81	1	1
82	0	1
83		unreachable
87	1	1
88	1	1
89	1	1
90	0	1
91	1	1
92	0	1
			MISSING_ELSE
116	1	1
117	1	1
118	1	1
119	1	1
121	1	1
135	1	1
136		unreachable
137	1	1
138		unreachable
			MISSING_ELSE
147	1	1
148	1	1
149	1	1
151	1	1
152	0	1
			MISSING_ELSE
			MISSING_ELSE
158	1	1
159	1	1
161	1	1
162	0	1
			MISSING_ELSE
167	1	1
168	1	1
170	1	1
171	0	1
			MISSING_ELSE
185	1	1
186	1	1
243	1	1
244	0	1
			MISSING_ELSE
257	1	1
258	1	1
286	0	1
339	1	1
346	0	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_sram_byte

	Total	Covered	Percent
Conditions	20	9	45.00
Logical	20	9	45.00
Non-Logical	0	0
Event	0	0

 LINE       89
 EXPRESSION (a_ack && ((!d_ack)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       91
 EXPRESSION (((!a_ack)) && d_ack)
             -----1----    --2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       135
 EXPRESSION (byte_wr_txn && a_ack_q)
             -----1-----    ---2---

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Unreachable
1	1	Unreachable

 LINE       138
 EXPRESSION ((txn_cnt == '0) ? StWaitRd : StFlush)
             -------1-------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       186
 EXPRESSION (d_ack ? StPassThru : StWait)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       267
 EXPRESSION (wr_phase ? PutFullData : Get)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       267
 EXPRESSION (wr_phase ? held_data.a_param : tl_i.a_param)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       267
 EXPRESSION (wr_phase ? held_data.a_source : tl_i.a_source)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       267
 EXPRESSION 
 Number  Term
      1  wr_phase ? ({held_data.a_address[(top_pkg::TL_AW - 1):AccessSize], {AccessSize {1'b0}}}) : ({tl_i.a_address[(top_pkg::TL_AW - 1):AccessSize], {AccessSize {1'b0}}}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       267
 EXPRESSION (wr_phase ? combined_data : tl_i.a_data)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       267
 EXPRESSION (wr_phase ? held_data.a_user : tl_i.a_user)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

FSM Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_sram_byte

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	1	20.00	(Not included in score)
Transitions	9	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StFlush	138	Not Covered
StPassThru	62	Covered	T1,T2,T3
StWait	171	Not Covered
StWaitRd	138	Not Covered
StWriteCmd	152	Not Covered

transitions	Line No.	Covered	Tests
StFlush->StPassThru	62	Not Covered
StFlush->StWriteCmd	152	Not Covered
StPassThru->StFlush	138	Not Covered
StPassThru->StWaitRd	138	Not Covered
StWait->StPassThru	62	Not Covered
StWaitRd->StPassThru	62	Not Covered
StWaitRd->StWriteCmd	162	Not Covered
StWriteCmd->StPassThru	62	Not Covered
StWriteCmd->StWait	171	Not Covered

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_sram_byte

	Line No.	Total	Covered	Percent
Branches		22	12	54.55
IF	61	2	2	100.00
IF	87	4	2	50.00
CASE	121	14	7	50.00
IF	243	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	61	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	87	if ((!rst_ni))
-2-:	89	if ((a_ack && (!d_ack)))
-3-:	91	if (((!a_ack) && d_ack))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	121	case (state_q)
-2-:	135	if ((byte_wr_txn && a_ack_q))
-3-:	137	if (byte_req_ack)
-4-:	138	((txn_cnt == '0)) ? 
-5-:	148	if ((txn_cnt == 4'b1))
-6-:	151	if (sram_d_ack)
-7-:	161	if (sram_d_ack)
-8-:	170	if (sram_a_ack)
-9-:	186	(d_ack) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
StPassThru	1	-	-	-	-	-	-	-	Not Covered
StPassThru	0	1	1	-	-	-	-	-	Not Covered
StPassThru	0	1	0	-	-	-	-	-	Not Covered
StPassThru	0	0	-	-	-	-	-	-	Covered	T1,T2,T3
StFlush	-	-	-	1	1	-	-	-	Not Covered
StFlush	-	-	-	1	0	-	-	-	Covered	T1,T2,T3
StFlush	-	-	-	0	-	-	-	-	Covered	T1,T2,T3
StWaitRd	-	-	-	-	-	1	-	-	Not Covered
StWaitRd	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
StWriteCmd	-	-	-	-	-	-	1	-	Not Covered
StWriteCmd	-	-	-	-	-	-	0	-	Covered	T1,T2,T3
StWait	-	-	-	-	-	-	-	1	Not Covered
StWait	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	243	if (sram_d_ack)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_cfg.u_sram_byte

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_non_intg_asserts.StableSignals_A	2402452	2398414	0	0

gen_non_intg_asserts.StableSignals_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	2398414	0	0
T1	16544	16482	0	0
T2	218256	218180	0	0
T3	15128	15056	0	0
T4	2443	2371	0	0
T5	5310	5215	0	0
T6	11803	11729	0	0
T7	14566	14492	0	0
T8	267592	267510	0	0
T9	541130	541047	0	0
T10	150985	150922	0	0

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sram_byte

	Line No.	Total	Covered	Percent
TOTAL		43	38	88.37
ALWAYS	61	3	3	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	0	0.00
CONT_ASSIGN	83	0	0
ALWAYS	87	6	4	66.67
ALWAYS	116	22	22	100.00
ALWAYS	243	2	1	50.00
ALWAYS	257	0	0
ALWAYS	257	2	2	100.00
CONT_ASSIGN	286	1	0	0.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	346	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
61	1	1
62	1	1
64	1	1
78	1	1
79	1	1
80	1	1
81	1	1
82	0	1
83		unreachable
87	1	1
88	1	1
89	1	1
90	0	1
91	1	1
92	0	1
			MISSING_ELSE
116	1	1
117	1	1
118	1	1
119	1	1
121	1	1
135	1	1
136		unreachable
137	1	1
138		unreachable
			MISSING_ELSE
147	1	1
148	1	1
149	1	1
151	1	1
152	1	1
			MISSING_ELSE
			MISSING_ELSE
158	1	1
159	1	1
161	1	1
162	1	1
			MISSING_ELSE
167	1	1
168	1	1
170	1	1
171	1	1
			MISSING_ELSE
185	1	1
186	1	1
243	1	1
244	0	1
			MISSING_ELSE
257	1	1
258	1	1
286	0	1
339	1	1
346	1	1

---

Cond Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sram_byte

	Total	Covered	Percent
Conditions	20	8	40.00
Logical	20	8	40.00
Non-Logical	0	0
Event	0	0

 LINE       89
 EXPRESSION (a_ack && ((!d_ack)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       91
 EXPRESSION (((!a_ack)) && d_ack)
             -----1----    --2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       135
 EXPRESSION (byte_wr_txn && a_ack_q)
             -----1-----    ---2---

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Unreachable
1	1	Unreachable

 LINE       138
 EXPRESSION ((txn_cnt == '0) ? StWaitRd : StFlush)
             -------1-------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       186
 EXPRESSION (d_ack ? StPassThru : StWait)
             --1--

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       267
 EXPRESSION (wr_phase ? PutFullData : Get)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       267
 EXPRESSION (wr_phase ? held_data.a_param : tl_i.a_param)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       267
 EXPRESSION (wr_phase ? held_data.a_source : tl_i.a_source)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       267
 EXPRESSION 
 Number  Term
      1  wr_phase ? ({held_data.a_address[(top_pkg::TL_AW - 1):AccessSize], {AccessSize {1'b0}}}) : ({tl_i.a_address[(top_pkg::TL_AW - 1):AccessSize], {AccessSize {1'b0}}}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       267
 EXPRESSION (wr_phase ? combined_data : tl_i.a_data)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       267
 EXPRESSION (wr_phase ? held_data.a_user : tl_i.a_user)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

FSM Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sram_byte

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	1	20.00	(Not included in score)
Transitions	9	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StFlush	138	Not Covered
StPassThru	62	Covered	T1,T2,T3
StWait	171	Not Covered
StWaitRd	138	Not Covered
StWriteCmd	152	Not Covered

transitions	Line No.	Covered	Tests
StFlush->StPassThru	62	Not Covered
StFlush->StWriteCmd	152	Not Covered
StPassThru->StFlush	138	Not Covered
StPassThru->StWaitRd	138	Not Covered
StWait->StPassThru	62	Not Covered
StWaitRd->StPassThru	62	Not Covered
StWaitRd->StWriteCmd	162	Not Covered
StWriteCmd->StPassThru	62	Not Covered
StWriteCmd->StWait	171	Not Covered

---

Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sram_byte

	Line No.	Total	Covered	Percent
Branches		22	14	63.64
IF	61	2	2	100.00
IF	87	4	2	50.00
CASE	121	14	9	64.29
IF	243	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	61	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	87	if ((!rst_ni))
-2-:	89	if ((a_ack && (!d_ack)))
-3-:	91	if (((!a_ack) && d_ack))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	121	case (state_q)
-2-:	135	if ((byte_wr_txn && a_ack_q))
-3-:	137	if (byte_req_ack)
-4-:	138	((txn_cnt == '0)) ? 
-5-:	148	if ((txn_cnt == 4'b1))
-6-:	151	if (sram_d_ack)
-7-:	161	if (sram_d_ack)
-8-:	170	if (sram_a_ack)
-9-:	186	(d_ack) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
StPassThru	1	-	-	-	-	-	-	-	Not Covered
StPassThru	0	1	1	-	-	-	-	-	Not Covered
StPassThru	0	1	0	-	-	-	-	-	Not Covered
StPassThru	0	0	-	-	-	-	-	-	Covered	T1,T2,T3
StFlush	-	-	-	1	1	-	-	-	Covered	T1,T2,T3
StFlush	-	-	-	1	0	-	-	-	Covered	T1,T2,T3
StFlush	-	-	-	0	-	-	-	-	Covered	T1,T2,T3
StWaitRd	-	-	-	-	-	1	-	-	Covered	T1,T2,T3
StWaitRd	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
StWriteCmd	-	-	-	-	-	-	1	-	Covered	T1,T2,T3
StWriteCmd	-	-	-	-	-	-	0	-	Covered	T1,T2,T3
StWait	-	-	-	-	-	-	-	1	Not Covered
StWait	-	-	-	-	-	-	-	0	Not Covered
default	-	-	-	-	-	-	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	243	if (sram_d_ack)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sram_byte

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_non_intg_asserts.StableSignals_A	2402452	2398414	0	0

gen_non_intg_asserts.StableSignals_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	2398414	0	0
T1	16544	16482	0	0
T2	218256	218180	0	0
T3	15128	15056	0	0
T4	2443	2371	0	0
T5	5310	5215	0	0
T6	11803	11729	0	0
T7	14566	14492	0	0
T8	267592	267510	0	0
T9	541130	541047	0	0
T10	150985	150922	0	0

Line Coverage for Instance : tb.dut.u_to_prog_fifo.u_sram_byte

	Line No.	Total	Covered	Percent
TOTAL		43	42	97.67
ALWAYS	61	3	3	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	83	0	0
ALWAYS	87	6	6	100.00
ALWAYS	116	22	22	100.00
ALWAYS	243	2	2	100.00
ALWAYS	257	0	0
ALWAYS	257	2	2	100.00
CONT_ASSIGN	286	1	0	0.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	346	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
61	1	1
62	1	1
64	1	1
78	1	1
79	1	1
80	1	1
81	1	1
82	1	1
83		unreachable
87	1	1
88	1	1
89	1	1
90	1	1
91	1	1
92	1	1
			MISSING_ELSE
116	1	1
117	1	1
118	1	1
119	1	1
121	1	1
135	1	1
136		unreachable
137	1	1
138		unreachable
			MISSING_ELSE
147	1	1
148	1	1
149	1	1
151	1	1
152	1	1
			MISSING_ELSE
			MISSING_ELSE
158	1	1
159	1	1
161	1	1
162	1	1
			MISSING_ELSE
167	1	1
168	1	1
170	1	1
171	1	1
			MISSING_ELSE
185	1	1
186	1	1
243	1	1
244	1	1
			MISSING_ELSE
257	1	1
258	1	1
286	0	1
339	1	1
346	1	1

---

Cond Coverage for Instance : tb.dut.u_to_prog_fifo.u_sram_byte

	Total	Covered	Percent
Conditions	20	10	50.00
Logical	20	10	50.00
Non-Logical	0	0
Event	0	0

 LINE       89
 EXPRESSION (a_ack && ((!d_ack)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       91
 EXPRESSION (((!a_ack)) && d_ack)
             -----1----    --2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       135
 EXPRESSION (byte_wr_txn && a_ack_q)
             -----1-----    ---2---

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Unreachable
1	1	Unreachable

 LINE       138
 EXPRESSION ((txn_cnt == '0) ? StWaitRd : StFlush)
             -------1-------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       186
 EXPRESSION (d_ack ? StPassThru : StWait)
             --1--

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       267
 EXPRESSION (wr_phase ? PutFullData : Get)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       267
 EXPRESSION (wr_phase ? held_data.a_param : tl_i.a_param)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       267
 EXPRESSION (wr_phase ? held_data.a_source : tl_i.a_source)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       267
 EXPRESSION 
 Number  Term
      1  wr_phase ? ({held_data.a_address[(top_pkg::TL_AW - 1):AccessSize], {AccessSize {1'b0}}}) : ({tl_i.a_address[(top_pkg::TL_AW - 1):AccessSize], {AccessSize {1'b0}}}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       267
 EXPRESSION (wr_phase ? combined_data : tl_i.a_data)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       267
 EXPRESSION (wr_phase ? held_data.a_user : tl_i.a_user)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

FSM Coverage for Instance : tb.dut.u_to_prog_fifo.u_sram_byte

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	1	20.00	(Not included in score)
Transitions	9	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StFlush	138	Not Covered
StPassThru	62	Covered	T1,T2,T3
StWait	171	Not Covered
StWaitRd	138	Not Covered
StWriteCmd	152	Not Covered

transitions	Line No.	Covered	Tests
StFlush->StPassThru	62	Not Covered
StFlush->StWriteCmd	152	Not Covered
StPassThru->StFlush	138	Not Covered
StPassThru->StWaitRd	138	Not Covered
StWait->StPassThru	62	Not Covered
StWaitRd->StPassThru	62	Not Covered
StWaitRd->StWriteCmd	162	Not Covered
StWriteCmd->StPassThru	62	Not Covered
StWriteCmd->StWait	171	Not Covered

---

Branch Coverage for Instance : tb.dut.u_to_prog_fifo.u_sram_byte

	Line No.	Total	Covered	Percent
Branches		22	17	77.27
IF	61	2	2	100.00
IF	87	4	4	100.00
CASE	121	14	9	64.29
IF	243	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	61	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	87	if ((!rst_ni))
-2-:	89	if ((a_ack && (!d_ack)))
-3-:	91	if (((!a_ack) && d_ack))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	121	case (state_q)
-2-:	135	if ((byte_wr_txn && a_ack_q))
-3-:	137	if (byte_req_ack)
-4-:	138	((txn_cnt == '0)) ? 
-5-:	148	if ((txn_cnt == 4'b1))
-6-:	151	if (sram_d_ack)
-7-:	161	if (sram_d_ack)
-8-:	170	if (sram_a_ack)
-9-:	186	(d_ack) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
StPassThru	1	-	-	-	-	-	-	-	Not Covered
StPassThru	0	1	1	-	-	-	-	-	Not Covered
StPassThru	0	1	0	-	-	-	-	-	Not Covered
StPassThru	0	0	-	-	-	-	-	-	Covered	T1,T2,T3
StFlush	-	-	-	1	1	-	-	-	Covered	T1,T2,T3
StFlush	-	-	-	1	0	-	-	-	Covered	T1,T2,T3
StFlush	-	-	-	0	-	-	-	-	Covered	T1,T2,T3
StWaitRd	-	-	-	-	-	1	-	-	Covered	T1,T2,T3
StWaitRd	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
StWriteCmd	-	-	-	-	-	-	1	-	Covered	T1,T2,T3
StWriteCmd	-	-	-	-	-	-	0	-	Covered	T1,T2,T3
StWait	-	-	-	-	-	-	-	1	Not Covered
StWait	-	-	-	-	-	-	-	0	Not Covered
default	-	-	-	-	-	-	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	243	if (sram_d_ack)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_to_prog_fifo.u_sram_byte

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_non_intg_asserts.StableSignals_A	2402452	2398414	0	0

gen_non_intg_asserts.StableSignals_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	2398414	0	0
T1	16544	16482	0	0
T2	218256	218180	0	0
T3	15128	15056	0	0
T4	2443	2371	0	0
T5	5310	5215	0	0
T6	11803	11729	0	0
T7	14566	14492	0	0
T8	267592	267510	0	0
T9	541130	541047	0	0
T10	150985	150922	0	0

Line Coverage for Instance : tb.dut.u_to_rd_fifo.u_sram_byte

	Line No.	Total	Covered	Percent
TOTAL		43	42	97.67
ALWAYS	61	3	3	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	83	0	0
ALWAYS	87	6	6	100.00
ALWAYS	116	22	22	100.00
ALWAYS	243	2	2	100.00
ALWAYS	257	0	0
ALWAYS	257	2	2	100.00
CONT_ASSIGN	286	1	0	0.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	346	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
61	1	1
62	1	1
64	1	1
78	1	1
79	1	1
80	1	1
81	1	1
82	1	1
83		unreachable
87	1	1
88	1	1
89	1	1
90	1	1
91	1	1
92	1	1
			MISSING_ELSE
116	1	1
117	1	1
118	1	1
119	1	1
121	1	1
135	1	1
136		unreachable
137	1	1
138		unreachable
			MISSING_ELSE
147	1	1
148	1	1
149	1	1
151	1	1
152	1	1
			MISSING_ELSE
			MISSING_ELSE
158	1	1
159	1	1
161	1	1
162	1	1
			MISSING_ELSE
167	1	1
168	1	1
170	1	1
171	1	1
			MISSING_ELSE
185	1	1
186	1	1
243	1	1
244	1	1
			MISSING_ELSE
257	1	1
258	1	1
286	0	1
339	1	1
346	1	1

---

Cond Coverage for Instance : tb.dut.u_to_rd_fifo.u_sram_byte

	Total	Covered	Percent
Conditions	20	10	50.00
Logical	20	10	50.00
Non-Logical	0	0
Event	0	0

 LINE       89
 EXPRESSION (a_ack && ((!d_ack)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       91
 EXPRESSION (((!a_ack)) && d_ack)
             -----1----    --2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       135
 EXPRESSION (byte_wr_txn && a_ack_q)
             -----1-----    ---2---

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Unreachable
1	1	Unreachable

 LINE       138
 EXPRESSION ((txn_cnt == '0) ? StWaitRd : StFlush)
             -------1-------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       186
 EXPRESSION (d_ack ? StPassThru : StWait)
             --1--

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       267
 EXPRESSION (wr_phase ? PutFullData : Get)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       267
 EXPRESSION (wr_phase ? held_data.a_param : tl_i.a_param)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       267
 EXPRESSION (wr_phase ? held_data.a_source : tl_i.a_source)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       267
 EXPRESSION 
 Number  Term
      1  wr_phase ? ({held_data.a_address[(top_pkg::TL_AW - 1):AccessSize], {AccessSize {1'b0}}}) : ({tl_i.a_address[(top_pkg::TL_AW - 1):AccessSize], {AccessSize {1'b0}}}))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       267
 EXPRESSION (wr_phase ? combined_data : tl_i.a_data)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       267
 EXPRESSION (wr_phase ? held_data.a_user : tl_i.a_user)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

FSM Coverage for Instance : tb.dut.u_to_rd_fifo.u_sram_byte

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	1	20.00	(Not included in score)
Transitions	9	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StFlush	138	Not Covered
StPassThru	62	Covered	T1,T2,T3
StWait	171	Not Covered
StWaitRd	138	Not Covered
StWriteCmd	152	Not Covered

transitions	Line No.	Covered	Tests
StFlush->StPassThru	62	Not Covered
StFlush->StWriteCmd	152	Not Covered
StPassThru->StFlush	138	Not Covered
StPassThru->StWaitRd	138	Not Covered
StWait->StPassThru	62	Not Covered
StWaitRd->StPassThru	62	Not Covered
StWaitRd->StWriteCmd	162	Not Covered
StWriteCmd->StPassThru	62	Not Covered
StWriteCmd->StWait	171	Not Covered

---

Branch Coverage for Instance : tb.dut.u_to_rd_fifo.u_sram_byte

	Line No.	Total	Covered	Percent
Branches		22	17	77.27
IF	61	2	2	100.00
IF	87	4	4	100.00
CASE	121	14	9	64.29
IF	243	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	61	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	87	if ((!rst_ni))
-2-:	89	if ((a_ack && (!d_ack)))
-3-:	91	if (((!a_ack) && d_ack))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	121	case (state_q)
-2-:	135	if ((byte_wr_txn && a_ack_q))
-3-:	137	if (byte_req_ack)
-4-:	138	((txn_cnt == '0)) ? 
-5-:	148	if ((txn_cnt == 4'b1))
-6-:	151	if (sram_d_ack)
-7-:	161	if (sram_d_ack)
-8-:	170	if (sram_a_ack)
-9-:	186	(d_ack) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
StPassThru	1	-	-	-	-	-	-	-	Not Covered
StPassThru	0	1	1	-	-	-	-	-	Not Covered
StPassThru	0	1	0	-	-	-	-	-	Not Covered
StPassThru	0	0	-	-	-	-	-	-	Covered	T1,T2,T3
StFlush	-	-	-	1	1	-	-	-	Covered	T1,T2,T3
StFlush	-	-	-	1	0	-	-	-	Covered	T1,T2,T3
StFlush	-	-	-	0	-	-	-	-	Covered	T1,T2,T3
StWaitRd	-	-	-	-	-	1	-	-	Covered	T1,T2,T3
StWaitRd	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
StWriteCmd	-	-	-	-	-	-	1	-	Covered	T1,T2,T3
StWriteCmd	-	-	-	-	-	-	0	-	Covered	T1,T2,T3
StWait	-	-	-	-	-	-	-	1	Not Covered
StWait	-	-	-	-	-	-	-	0	Not Covered
default	-	-	-	-	-	-	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	243	if (sram_d_ack)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_to_rd_fifo.u_sram_byte

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_non_intg_asserts.StableSignals_A	2402452	2398414	0	0

gen_non_intg_asserts.StableSignals_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	2398414	0	0
T1	16544	16482	0	0
T2	218256	218180	0	0
T3	15128	15056	0	0
T4	2443	2371	0	0
T5	5310	5215	0	0
T6	11803	11729	0	0
T7	14566	14492	0	0
T8	267592	267510	0	0
T9	541130	541047	0	0
T10	150985	150922	0	0