Unified Coverage Report :: Module :: prim_count

Module : prim_count

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
47.92	81.25	47.51			46.26	16.67

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_count_0/rtl/prim_count.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_hw_if.u_word_cnt	45.41	75.00	41.18			45.45	20.00
tb.dut.u_flash_hw_if.u_page_cnt	53.35	87.50	53.85			47.06	25.00

---

Module Instance : tb.dut.u_flash_hw_if.u_word_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
45.41	75.00	41.18			45.45	20.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
47.24	77.78	41.18			50.00	20.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
43.26	90.59	13.46		0.00	68.97		u_flash_hw_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_cnts[0].u_buf	100.00	100.00
gen_cnts[0].u_cnt_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_flash_hw_if.u_page_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
53.35	87.50	53.85			47.06	25.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
56.91	91.67	53.85			57.14	25.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
43.26	90.59	13.46		0.00	68.97		u_flash_hw_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_cnts[0].u_buf	100.00	100.00
gen_cnts[0].u_cnt_flop	100.00	100.00				100.00
gen_cnts[1].u_buf	100.00	100.00
gen_cnts[1].u_cnt_flop	100.00	100.00				100.00

Line Coverage for Module : prim_count ( parameter Width=9,OutSelDnCnt=0,CntStyle=1 )
Line Coverage for Module self-instances :

SCORE	LINE
53.35	87.50

tb.dut.u_flash_hw_if.u_page_cnt

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
ALWAYS	167	6	4	66.67

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_count_0/rtl/prim_count.sv' or '../src/lowrisc_prim_count_0/rtl/prim_count.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
51	1	1
56	1	1
66	1	1
67	1	1
68	1	1
69		unreachable
			MISSING_ELSE
75	2	2
151	1	1
152	1	1
159	1	1
167	1	1
168	1	1
169	1	1
170	1	1
171	0	1
172	0	1
			MISSING_ELSE

---

Line Coverage for Module : prim_count ( parameter Width=10,OutSelDnCnt=0,CntStyle=0 )
Line Coverage for Module self-instances :

SCORE	LINE
45.41	75.00

tb.dut.u_flash_hw_if.u_word_cnt

	Line No.	Total	Covered	Percent
TOTAL		32	24	75.00
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	56	0	0
ALWAYS	66	4	3	75.00
CONT_ASSIGN	75	1	1	100.00
ALWAYS	103	6	4	66.67
ALWAYS	114	8	5	62.50
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	127	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
ALWAYS	167	6	4	66.67

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_count_0/rtl/prim_count.sv' or '../src/lowrisc_prim_count_0/rtl/prim_count.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
51	1	1
56		unreachable
66	1	1
67	1	1
68	1	1
69	0	1
			MISSING_ELSE
75	1	1
103	1	1
104	1	1
105	1	1
106	0	1
107	1	1
108	0	1
			MISSING_ELSE
114	1	1
115	1	1
116	1	1
117	0	1
118	1	1
119	0	1
120	1	1
121	0	1
			MISSING_ELSE
126	1	1
127	1	1
128	1	1
142	1	1
144	1	1
159	1	1
167	1	1
168	1	1
169	1	1
170	1	1
171	0	1
172	0	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_count ( parameter Width=9,OutSelDnCnt=0,CntStyle=1 )
Cond Coverage for Module self-instances :

SCORE	COND
53.35	53.85

tb.dut.u_flash_hw_if.u_page_cnt

	Total	Covered	Percent
Conditions	13	7	53.85
Logical	13	7	53.85
Non-Logical	0	0
Event	0	0

 LINE       75
 EXPRESSION (clr_up_cnt ? '0 : (set_up_cnt ? set_cnt_i : (((en_i & (up_cnt_q[0] < max_val))) ? ((up_cnt_q[0] + step_i)) : up_cnt_q[0])))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       75
 SUB-EXPRESSION (set_up_cnt ? set_cnt_i : (((en_i & (up_cnt_q[0] < max_val))) ? ((up_cnt_q[0] + step_i)) : up_cnt_q[0]))
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       75
 SUB-EXPRESSION (((en_i & (up_cnt_q[0] < max_val))) ? ((up_cnt_q[0] + step_i)) : up_cnt_q[0])
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       75
 EXPRESSION (clr_up_cnt ? '0 : (set_up_cnt ? set_cnt_i : (((en_i & (up_cnt_q[1] < max_val))) ? ((up_cnt_q[1] + step_i)) : up_cnt_q[1])))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       75
 SUB-EXPRESSION (set_up_cnt ? set_cnt_i : (((en_i & (up_cnt_q[1] < max_val))) ? ((up_cnt_q[1] + step_i)) : up_cnt_q[1]))
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       75
 SUB-EXPRESSION (((en_i & (up_cnt_q[1] < max_val))) ? ((up_cnt_q[1] + step_i)) : up_cnt_q[1])
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       159
 EXPRESSION ((cmp_valid == CmpValid) ? err : ((cmp_valid == CmpInvalid) ? '0 : 1'b1))
             -----------1-----------

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       159
 SUB-EXPRESSION ((cmp_valid == CmpInvalid) ? '0 : 1'b1)
                 ------------1------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

---

Cond Coverage for Module : prim_count ( parameter Width=10,OutSelDnCnt=0,CntStyle=0 )
Cond Coverage for Module self-instances :

SCORE	COND
45.41	41.18

tb.dut.u_flash_hw_if.u_word_cnt

	Total	Covered	Percent
Conditions	17	7	41.18
Logical	17	7	41.18
Non-Logical	0	0
Event	0	0

 LINE       68
 EXPRESSION (set_i && (CntStyle == CrossCnt))
             --1--    -----------2----------

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Not Covered

 LINE       75
 EXPRESSION (clr_up_cnt ? '0 : (set_up_cnt ? set_cnt_i : (((en_i & (up_cnt_q[0] < max_val))) ? ((up_cnt_q[0] + step_i)) : up_cnt_q[0])))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       75
 SUB-EXPRESSION (set_up_cnt ? set_cnt_i : (((en_i & (up_cnt_q[0] < max_val))) ? ((up_cnt_q[0] + step_i)) : up_cnt_q[0]))
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Unreachable

 LINE       75
 SUB-EXPRESSION (((en_i & (up_cnt_q[0] < max_val))) ? ((up_cnt_q[0] + step_i)) : up_cnt_q[0])
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       107
 EXPRESSION ((cmp_valid == CmpInvalid) && set_i)
             ------------1------------    --2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       120
 EXPRESSION (en_i && (gen_cross_cnt_hardening.down_cnt > '0))
             --1-    -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       159
 EXPRESSION ((cmp_valid == CmpValid) ? err : ((cmp_valid == CmpInvalid) ? '0 : 1'b1))
             -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       159
 SUB-EXPRESSION ((cmp_valid == CmpInvalid) ? '0 : 1'b1)
                 ------------1------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_count ( parameter Width=9,OutSelDnCnt=0,CntStyle=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
53.35	47.06

tb.dut.u_flash_hw_if.u_page_cnt

	Line No.	Total	Covered	Percent
Branches		17	8	47.06
TERNARY	159	3	1	33.33
TERNARY	75	4	1	25.00
TERNARY	75	4	2	50.00
IF	66	3	2	66.67
IF	167	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_count_0/rtl/prim_count.sv' or '../src/lowrisc_prim_count_0/rtl/prim_count.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	159	((cmp_valid == CmpValid)) ? 
-2-:	159	((cmp_valid == CmpInvalid)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	75	(clr_up_cnt) ? 
-2-:	75	(set_up_cnt) ? 
-3-:	75	((en_i & (up_cnt_q[0] < max_val))) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	75	(clr_up_cnt) ? 
-2-:	75	(set_up_cnt) ? 
-3-:	75	((en_i & (up_cnt_q[1] < max_val))) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	66	if ((!rst_ni))
-2-:	68	if ((set_i && (CntStyle == CrossCnt)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	167	if ((!rst_ni))
-2-:	170	if (en_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_count ( parameter Width=10,OutSelDnCnt=0,CntStyle=0 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
45.41	45.45

tb.dut.u_flash_hw_if.u_word_cnt

	Line No.	Total	Covered	Percent
Branches		22	10	45.45
TERNARY	159	3	1	33.33
TERNARY	75	4	1	25.00
IF	66	3	2	66.67
IF	167	3	2	66.67
IF	103	4	2	50.00
IF	114	5	2	40.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_count_0/rtl/prim_count.sv' or '../src/lowrisc_prim_count_0/rtl/prim_count.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	159	((cmp_valid == CmpValid)) ? 
-2-:	159	((cmp_valid == CmpInvalid)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T3
0	0	Not Covered

	LineNo.	Expression
-1-:	75	(clr_up_cnt) ? 
-2-:	75	(set_up_cnt) ? 
-3-:	75	((en_i & (up_cnt_q[0] < max_val))) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	66	if ((!rst_ni))
-2-:	68	if ((set_i && (CntStyle == CrossCnt)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	167	if ((!rst_ni))
-2-:	170	if (en_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	103	if ((!rst_ni))
-2-:	105	if (clr_i)
-3-:	107	if (((cmp_valid == CmpInvalid) && set_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	114	if ((!rst_ni))
-2-:	116	if (clr_i)
-3-:	118	if (set_i)
-4-:	120	if ((en_i && (gen_cross_cnt_hardening.down_cnt > '0)))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_count

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	12	12	100.00	2	16.67
Cover properties	0	0		0
Cover sequences	0	0		0
Total	12	12	100.00	2	16.67

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AssertConnected_A	110	110	0	0
CntStyleMatch_A	110	110	0	0
OutClr_A	4804904	0	0	0
OutSet_A	4804904	0	0	110
OutStep_A	4804904	0	0	0
SimulClrSet_A	4804904	0	0	0
gen_cross_cnt_hardening.CrossCntErrBackward_A	2402452	0	0	0
gen_cross_cnt_hardening.CrossCntErrForward_A	2402452	0	0	0
gen_cross_cnt_hardening.DownCntStepInt_A	2402452	0	0	0
gen_cross_cnt_hardening.UpCntOverFlow_A	2402452	0	0	0
gen_dup_cnt_hardening.DupCntErrBackward_A	2402452	0	0	0
gen_dup_cnt_hardening.DupCntErrForward_A	2402452	0	0	0

AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	110	110	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T8	2	2	0	0
T9	2	2	0	0
T10	2	2	0	0

CntStyleMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	110	110	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T8	2	2	0	0
T9	2	2	0	0
T10	2	2	0	0

OutClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4804904	0	0	0

OutSet_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4804904	0	0	110

OutStep_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4804904	0	0	0

SimulClrSet_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4804904	0	0	0

gen_cross_cnt_hardening.CrossCntErrBackward_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	0	0	0

gen_cross_cnt_hardening.CrossCntErrForward_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	0	0	0

gen_cross_cnt_hardening.DownCntStepInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	0	0	0

gen_cross_cnt_hardening.UpCntOverFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	0	0	0

gen_dup_cnt_hardening.DupCntErrBackward_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	0	0	0

gen_dup_cnt_hardening.DupCntErrForward_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	0	0	0

Line Coverage for Instance : tb.dut.u_flash_hw_if.u_word_cnt

	Line No.	Total	Covered	Percent
TOTAL		32	24	75.00
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	56	0	0
ALWAYS	66	4	3	75.00
CONT_ASSIGN	75	1	1	100.00
ALWAYS	103	6	4	66.67
ALWAYS	114	8	5	62.50
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	127	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
ALWAYS	167	6	4	66.67

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_count_0/rtl/prim_count.sv' or '../src/lowrisc_prim_count_0/rtl/prim_count.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
51	1	1
56		unreachable
66	1	1
67	1	1
68	1	1
69	0	1
			MISSING_ELSE
75	1	1
103	1	1
104	1	1
105	1	1
106	0	1
107	1	1
108	0	1
			MISSING_ELSE
114	1	1
115	1	1
116	1	1
117	0	1
118	1	1
119	0	1
120	1	1
121	0	1
			MISSING_ELSE
126	1	1
127	1	1
128	1	1
142	1	1
144	1	1
159	1	1
167	1	1
168	1	1
169	1	1
170	1	1
171	0	1
172	0	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_flash_hw_if.u_word_cnt

	Total	Covered	Percent
Conditions	17	7	41.18
Logical	17	7	41.18
Non-Logical	0	0
Event	0	0

 LINE       68
 EXPRESSION (set_i && (CntStyle == CrossCnt))
             --1--    -----------2----------

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Not Covered

 LINE       75
 EXPRESSION (clr_up_cnt ? '0 : (set_up_cnt ? set_cnt_i : (((en_i & (up_cnt_q[0] < max_val))) ? ((up_cnt_q[0] + step_i)) : up_cnt_q[0])))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       75
 SUB-EXPRESSION (set_up_cnt ? set_cnt_i : (((en_i & (up_cnt_q[0] < max_val))) ? ((up_cnt_q[0] + step_i)) : up_cnt_q[0]))
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Unreachable

 LINE       75
 SUB-EXPRESSION (((en_i & (up_cnt_q[0] < max_val))) ? ((up_cnt_q[0] + step_i)) : up_cnt_q[0])
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       107
 EXPRESSION ((cmp_valid == CmpInvalid) && set_i)
             ------------1------------    --2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       120
 EXPRESSION (en_i && (gen_cross_cnt_hardening.down_cnt > '0))
             --1-    -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       159
 EXPRESSION ((cmp_valid == CmpValid) ? err : ((cmp_valid == CmpInvalid) ? '0 : 1'b1))
             -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       159
 SUB-EXPRESSION ((cmp_valid == CmpInvalid) ? '0 : 1'b1)
                 ------------1------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_flash_hw_if.u_word_cnt

	Line No.	Total	Covered	Percent
Branches		22	10	45.45
TERNARY	159	3	1	33.33
TERNARY	75	4	1	25.00
IF	66	3	2	66.67
IF	167	3	2	66.67
IF	103	4	2	50.00
IF	114	5	2	40.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_count_0/rtl/prim_count.sv' or '../src/lowrisc_prim_count_0/rtl/prim_count.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	159	((cmp_valid == CmpValid)) ? 
-2-:	159	((cmp_valid == CmpInvalid)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T3
0	0	Not Covered

	LineNo.	Expression
-1-:	75	(clr_up_cnt) ? 
-2-:	75	(set_up_cnt) ? 
-3-:	75	((en_i & (up_cnt_q[0] < max_val))) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	66	if ((!rst_ni))
-2-:	68	if ((set_i && (CntStyle == CrossCnt)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	167	if ((!rst_ni))
-2-:	170	if (en_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	103	if ((!rst_ni))
-2-:	105	if (clr_i)
-3-:	107	if (((cmp_valid == CmpInvalid) && set_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	114	if ((!rst_ni))
-2-:	116	if (clr_i)
-3-:	118	if (set_i)
-4-:	120	if ((en_i && (gen_cross_cnt_hardening.down_cnt > '0)))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_hw_if.u_word_cnt

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	2	20.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	2	20.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AssertConnected_A	55	55	0	0
CntStyleMatch_A	55	55	0	0
OutClr_A	2402452	0	0	0
OutSet_A	2402452	0	0	55
OutStep_A	2402452	0	0	0
SimulClrSet_A	2402452	0	0	0
gen_cross_cnt_hardening.CrossCntErrBackward_A	2402452	0	0	0
gen_cross_cnt_hardening.CrossCntErrForward_A	2402452	0	0	0
gen_cross_cnt_hardening.DownCntStepInt_A	2402452	0	0	0
gen_cross_cnt_hardening.UpCntOverFlow_A	2402452	0	0	0

AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55	55	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

CntStyleMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55	55	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	0	0	0

OutSet_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	0	0	55

OutStep_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	0	0	0

SimulClrSet_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	0	0	0

gen_cross_cnt_hardening.CrossCntErrBackward_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	0	0	0

gen_cross_cnt_hardening.CrossCntErrForward_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	0	0	0

gen_cross_cnt_hardening.DownCntStepInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	0	0	0

gen_cross_cnt_hardening.UpCntOverFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	0	0	0

Line Coverage for Instance : tb.dut.u_flash_hw_if.u_page_cnt

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	66	3	3	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
ALWAYS	167	6	4	66.67

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_count_0/rtl/prim_count.sv' or '../src/lowrisc_prim_count_0/rtl/prim_count.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
51	1	1
56	1	1
66	1	1
67	1	1
68	1	1
69		unreachable
			MISSING_ELSE
75	2	2
151	1	1
152	1	1
159	1	1
167	1	1
168	1	1
169	1	1
170	1	1
171	0	1
172	0	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_flash_hw_if.u_page_cnt

	Total	Covered	Percent
Conditions	13	7	53.85
Logical	13	7	53.85
Non-Logical	0	0
Event	0	0

 LINE       75
 EXPRESSION (clr_up_cnt ? '0 : (set_up_cnt ? set_cnt_i : (((en_i & (up_cnt_q[0] < max_val))) ? ((up_cnt_q[0] + step_i)) : up_cnt_q[0])))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       75
 SUB-EXPRESSION (set_up_cnt ? set_cnt_i : (((en_i & (up_cnt_q[0] < max_val))) ? ((up_cnt_q[0] + step_i)) : up_cnt_q[0]))
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       75
 SUB-EXPRESSION (((en_i & (up_cnt_q[0] < max_val))) ? ((up_cnt_q[0] + step_i)) : up_cnt_q[0])
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       75
 EXPRESSION (clr_up_cnt ? '0 : (set_up_cnt ? set_cnt_i : (((en_i & (up_cnt_q[1] < max_val))) ? ((up_cnt_q[1] + step_i)) : up_cnt_q[1])))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       75
 SUB-EXPRESSION (set_up_cnt ? set_cnt_i : (((en_i & (up_cnt_q[1] < max_val))) ? ((up_cnt_q[1] + step_i)) : up_cnt_q[1]))
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       75
 SUB-EXPRESSION (((en_i & (up_cnt_q[1] < max_val))) ? ((up_cnt_q[1] + step_i)) : up_cnt_q[1])
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       159
 EXPRESSION ((cmp_valid == CmpValid) ? err : ((cmp_valid == CmpInvalid) ? '0 : 1'b1))
             -----------1-----------

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       159
 SUB-EXPRESSION ((cmp_valid == CmpInvalid) ? '0 : 1'b1)
                 ------------1------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_flash_hw_if.u_page_cnt

	Line No.	Total	Covered	Percent
Branches		17	8	47.06
TERNARY	159	3	1	33.33
TERNARY	75	4	1	25.00
TERNARY	75	4	2	50.00
IF	66	3	2	66.67
IF	167	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_count_0/rtl/prim_count.sv' or '../src/lowrisc_prim_count_0/rtl/prim_count.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	159	((cmp_valid == CmpValid)) ? 
-2-:	159	((cmp_valid == CmpInvalid)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	75	(clr_up_cnt) ? 
-2-:	75	(set_up_cnt) ? 
-3-:	75	((en_i & (up_cnt_q[0] < max_val))) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	75	(clr_up_cnt) ? 
-2-:	75	(set_up_cnt) ? 
-3-:	75	((en_i & (up_cnt_q[1] < max_val))) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	66	if ((!rst_ni))
-2-:	68	if ((set_i && (CntStyle == CrossCnt)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	167	if ((!rst_ni))
-2-:	170	if (en_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_hw_if.u_page_cnt

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	2	25.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	2	25.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AssertConnected_A	55	55	0	0
CntStyleMatch_A	55	55	0	0
OutClr_A	2402452	0	0	0
OutSet_A	2402452	0	0	55
OutStep_A	2402452	0	0	0
SimulClrSet_A	2402452	0	0	0
gen_dup_cnt_hardening.DupCntErrBackward_A	2402452	0	0	0
gen_dup_cnt_hardening.DupCntErrForward_A	2402452	0	0	0

AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55	55	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

CntStyleMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55	55	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	0	0	0

OutSet_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	0	0	55

OutStep_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	0	0	0

SimulClrSet_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	0	0	0

gen_dup_cnt_hardening.DupCntErrBackward_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	0	0	0

gen_dup_cnt_hardening.DupCntErrForward_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	0	0	0