Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : flash_ctrl
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.52 91.74 69.23 13.28 75.00 83.33

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 66.52 91.74 69.23 13.28 75.00 83.33



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.52 91.74 69.23 13.28 75.00 83.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
69.69 96.10 89.98 16.99 34.84 94.65 85.56


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
flash_ctrl_core_csr_assert 72.49 100.00 92.86 97.10 0.00
gen_alert_senders[0].u_alert_sender 91.67 91.67
gen_alert_senders[1].u_alert_sender 91.67 91.67
tlul_assert_device 99.07 100.00 100.00 97.20
u_ctrl_arb 86.31 100.00 100.00 50.00 95.24
u_eflash 56.35 87.14 47.62 25.10 49.48 67.04 61.70
u_flash_ctrl_erase 100.00 100.00 100.00 100.00
u_flash_ctrl_prog 77.37 98.25 48.15 85.71
u_flash_ctrl_rd 66.42 97.92 44.44 40.00 83.33
u_flash_hw_if 43.00 92.33 25.61 0.00 72.04 25.00
u_flash_mp 84.13 97.65 88.89 83.33 66.67
u_intr_corr_err 100.00 100.00 100.00
u_intr_op_done 100.00 100.00 100.00
u_intr_prog_empty 100.00 100.00 100.00
u_intr_prog_lvl 100.00 100.00 100.00
u_intr_rd_full 100.00 100.00 100.00
u_intr_rd_lvl 100.00 100.00 100.00
u_lc_escalation_en_sync 100.00 100.00 100.00 100.00
u_lc_seed_hw_rd_en_sync 100.00 100.00 100.00 100.00
u_lfsr 2.21 2.21
u_prog_empty_event 100.00 100.00 100.00
u_prog_fifo 93.00 94.74 90.91 86.36 100.00
u_prog_lvl_event 100.00 100.00 100.00
u_rd_fifo 93.00 94.74 90.91 86.36 100.00
u_rd_full_event 100.00 100.00 100.00
u_rd_lvl_event 100.00 100.00 100.00
u_reg_core 99.79 99.76 99.74 99.64 100.00
u_reg_idle 100.00 100.00 100.00
u_region_cfg 85.28 55.84 100.00 100.00
u_tl_adapter_eflash 45.10 62.32 33.33 0.00 56.15 73.68
u_to_prog_fifo 59.05 92.73 59.52 0.00 64.62 78.38
u_to_rd_fifo 66.04 95.10 66.67 0.00 73.85 94.59


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : flash_ctrl
Line No.TotalCoveredPercent
TOTAL10910091.74
CONT_ASSIGN37411100.00
CONT_ASSIGN37511100.00
CONT_ASSIGN37611100.00
CONT_ASSIGN37711100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN38111100.00
CONT_ASSIGN38211100.00
CONT_ASSIGN38311100.00
CONT_ASSIGN38411100.00
CONT_ASSIGN38511100.00
CONT_ASSIGN38611100.00
CONT_ASSIGN38711100.00
CONT_ASSIGN38811100.00
CONT_ASSIGN45911100.00
CONT_ASSIGN50411100.00
CONT_ASSIGN50611100.00
ALWAYS54233100.00
CONT_ASSIGN59211100.00
CONT_ASSIGN62311100.00
ALWAYS64577100.00
CONT_ASSIGN67811100.00
CONT_ASSIGN67911100.00
CONT_ASSIGN73911100.00
CONT_ASSIGN74111100.00
CONT_ASSIGN74211100.00
CONT_ASSIGN74311100.00
CONT_ASSIGN74411100.00
CONT_ASSIGN74511100.00
CONT_ASSIGN74611100.00
CONT_ASSIGN74711100.00
CONT_ASSIGN74811100.00
CONT_ASSIGN74911100.00
CONT_ASSIGN75011100.00
CONT_ASSIGN75311100.00
CONT_ASSIGN75611100.00
CONT_ASSIGN75911100.00
CONT_ASSIGN761100.00
CONT_ASSIGN763100.00
CONT_ASSIGN76711100.00
CONT_ASSIGN76811100.00
CONT_ASSIGN76911100.00
CONT_ASSIGN77011100.00
CONT_ASSIGN77111100.00
CONT_ASSIGN77211100.00
CONT_ASSIGN77411100.00
CONT_ASSIGN77511100.00
CONT_ASSIGN776100.00
CONT_ASSIGN777100.00
CONT_ASSIGN77811100.00
CONT_ASSIGN77911100.00
CONT_ASSIGN780100.00
CONT_ASSIGN781100.00
CONT_ASSIGN782100.00
CONT_ASSIGN78411100.00
CONT_ASSIGN78511100.00
CONT_ASSIGN786100.00
CONT_ASSIGN787100.00
CONT_ASSIGN78811100.00
CONT_ASSIGN78911100.00
CONT_ASSIGN79011100.00
CONT_ASSIGN79611100.00
CONT_ASSIGN81911100.00
CONT_ASSIGN82311100.00
CONT_ASSIGN82611100.00
CONT_ASSIGN83011100.00
CONT_ASSIGN86711100.00
CONT_ASSIGN87111100.00
CONT_ASSIGN87411100.00
CONT_ASSIGN89011100.00
CONT_ASSIGN89111100.00
CONT_ASSIGN89211100.00
CONT_ASSIGN89311100.00
CONT_ASSIGN89411100.00
CONT_ASSIGN89511100.00
CONT_ASSIGN89611100.00
CONT_ASSIGN89711100.00
CONT_ASSIGN89811100.00
CONT_ASSIGN91311100.00
CONT_ASSIGN91411100.00
CONT_ASSIGN91511100.00
CONT_ASSIGN91611100.00
CONT_ASSIGN91711100.00
CONT_ASSIGN91811100.00
CONT_ASSIGN91911100.00
CONT_ASSIGN92011100.00
CONT_ASSIGN92111100.00
CONT_ASSIGN92211100.00
CONT_ASSIGN92611100.00
CONT_ASSIGN92611100.00
CONT_ASSIGN92711100.00
CONT_ASSIGN92711100.00
CONT_ASSIGN93111100.00
CONT_ASSIGN93111100.00
CONT_ASSIGN93211100.00
CONT_ASSIGN93211100.00
CONT_ASSIGN103811100.00
CONT_ASSIGN103911100.00
CONT_ASSIGN107311100.00
CONT_ASSIGN107411100.00
CONT_ASSIGN107511100.00
CONT_ASSIGN116911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl.sv' or '../src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
374 1 1
375 1 1
376 1 1
377 1 1
378 1 1
381 1 1
382 1 1
383 1 1
384 1 1
385 1 1
386 1 1
387 1 1
388 1 1
459 1 1
504 1 1
506 1 1
542 1 1
543 1 1
545 1 1
592 1 1
623 1 1
645 1 1
647 1 1
648 1 1
651 1 1
652 1 1
655 1 1
656 1 1
678 1 1
679 1 1
739 1 1
741 1 1
742 1 1
743 1 1
744 1 1
745 1 1
746 1 1
747 1 1
748 1 1
749 1 1
750 1 1
753 1 1
756 1 1
759 1 1
761 0 1
763 0 1
767 1 1
768 1 1
769 1 1
770 1 1
771 1 1
772 1 1
774 1 1
775 1 1
776 0 1
777 0 1
778 1 1
779 1 1
780 0 1
781 0 1
782 0 1
784 1 1
785 1 1
786 0 1
787 0 1
788 1 1
789 1 1
790 1 1
796 1 1
819 1 1
823 1 1
826 1 1
830 1 1
867 1 1
871 1 1
874 1 1
890 1 1
891 1 1
892 1 1
893 1 1
894 1 1
895 1 1
896 1 1
897 1 1
898 1 1
913 1 1
914 1 1
915 1 1
916 1 1
917 1 1
918 1 1
919 1 1
920 1 1
921 1 1
922 1 1
926 2 2
927 2 2
931 2 2
932 2 2
1038 1 1
1039 1 1
1073 1 1
1074 1 1
1075 1 1
1169 1 1


Cond Coverage for Module : flash_ctrl
TotalCoveredPercent
Conditions13969.23
Logical13969.23
Non-Logical00
Event00

 LINE       545
 EXPRESSION (rd_fifo_ren && sw_rvalid)
             -----1-----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT1,T2,T3

 LINE       756
 EXPRESSION (sw_sel ? ((!op_start)) : 1'b1)
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       867
 EXPRESSION ((lc_escalate_en == On) ? MuBi4True : (mubi4_t'(reg2hw.dis.q)))
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       874
 EXPRESSION ((lc_escalate_en == On) ? MuBi4False : (mubi4_t'(reg2hw.exec.q)))
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       927
 EXPRESSION (((&reg2hw.ecc_single_err_cnt[0].q)) ? reg2hw.ecc_single_err_cnt[0].q : ((reg2hw.ecc_single_err_cnt[0].q + 1'b1)))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       927
 EXPRESSION (((&reg2hw.ecc_single_err_cnt[1].q)) ? reg2hw.ecc_single_err_cnt[1].q : ((reg2hw.ecc_single_err_cnt[1].q + 1'b1)))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

Toggle Coverage for Module : flash_ctrl
TotalCoveredPercent
Totals 108 42 38.89
Total Bits 2710 360 13.28
Total Bits 0->1 1355 180 13.28
Total Bits 1->0 1355 180 13.28

Ports 108 42 38.89
Port Bits 2710 360 13.28
Port Bits 0->1 1355 180 13.28
Port Bits 1->0 1355 180 13.28

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T13,T14,T15 Yes T1,T2,T3 INPUT
rst_shadowed_ni Yes Yes T13,T14,T15 Yes T1,T2,T3 INPUT
clk_otp_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_otp_ni Yes Yes T13,T14,T15 Yes T1,T2,T3 INPUT
lc_creator_seed_sw_rw_en_i[3:0] No No No INPUT
lc_owner_seed_sw_rw_en_i[3:0] No No No INPUT
lc_iso_part_sw_rd_en_i[3:0] No No No INPUT
lc_iso_part_sw_wr_en_i[3:0] No No No INPUT
lc_seed_hw_rd_en_i[3:0] No No No INPUT
lc_escalate_en_i[3:0] No No No INPUT
lc_nvm_debug_en_i[3:0] No No No INPUT
core_tl_i.d_ready Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
core_tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_user.instr_type[3:0] No No No INPUT
core_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
core_tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_address[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
core_tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
core_tl_o.d_error Yes Yes T16,T17,T18 Yes T16,T17,T18 OUTPUT
core_tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
core_tl_o.d_user.rsp_intg[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
core_tl_o.d_user.rsp_intg[6] No No No OUTPUT
core_tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
core_tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
core_tl_o.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
core_tl_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
core_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
core_tl_o.d_opcode[0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
core_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
core_tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
prim_tl_i.d_ready No No No INPUT
prim_tl_i.a_user.data_intg[6:0] No No No INPUT
prim_tl_i.a_user.cmd_intg[6:0] No No No INPUT
prim_tl_i.a_user.instr_type[3:0] No No No INPUT
prim_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
prim_tl_i.a_data[31:0] No No No INPUT
prim_tl_i.a_mask[3:0] No No No INPUT
prim_tl_i.a_address[31:0] No No No INPUT
prim_tl_i.a_source[7:0] No No No INPUT
prim_tl_i.a_size[1:0] No No No INPUT
prim_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
prim_tl_i.a_opcode[2:0] No No No INPUT
prim_tl_i.a_valid No No No INPUT
prim_tl_o.a_ready Yes Yes T13,T14,T15 Yes T1,T2,T3 OUTPUT
prim_tl_o.d_error No No No OUTPUT
prim_tl_o.d_user.data_intg[6:0] No No No OUTPUT
prim_tl_o.d_user.rsp_intg[6:0] No No No OUTPUT
prim_tl_o.d_data[31:0] No No No OUTPUT
prim_tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
prim_tl_o.d_source[7:0] No No No OUTPUT
prim_tl_o.d_size[1:0] No No No OUTPUT
prim_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
prim_tl_o.d_opcode[0] No No No OUTPUT
prim_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
prim_tl_o.d_valid No No No OUTPUT
mem_tl_i.d_ready Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
mem_tl_i.a_user.data_intg[6:0] No No No INPUT
mem_tl_i.a_user.cmd_intg[6:0] No No No INPUT
mem_tl_i.a_user.instr_type[3:0] No No No INPUT
mem_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
mem_tl_i.a_data[31:0] No No No INPUT
mem_tl_i.a_mask[3:0] No No No INPUT
mem_tl_i.a_address[31:0] No No No INPUT
mem_tl_i.a_source[7:0] No No No INPUT
mem_tl_i.a_size[1:0] No No No INPUT
mem_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
mem_tl_i.a_opcode[2:0] No No No INPUT
mem_tl_i.a_valid No No No INPUT
mem_tl_o.a_ready Yes Yes T13,T14,T15 Yes T1,T2,T3 OUTPUT
mem_tl_o.d_error No No No OUTPUT
mem_tl_o.d_user.data_intg[6:0] No No No OUTPUT
mem_tl_o.d_user.rsp_intg[6:0] No No No OUTPUT
mem_tl_o.d_data[31:0] No No No OUTPUT
mem_tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
mem_tl_o.d_source[7:0] No No No OUTPUT
mem_tl_o.d_size[1:0] No No No OUTPUT
mem_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
mem_tl_o.d_opcode[0] No No No OUTPUT
mem_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
mem_tl_o.d_valid No No No OUTPUT
otp_o.addr_req No No No OUTPUT
otp_o.data_req No No No OUTPUT
otp_i.seed_valid No No No INPUT
otp_i.rand_key[127:0] No No No INPUT
otp_i.key[127:0] No No No INPUT
otp_i.addr_ack No No No INPUT
otp_i.data_ack No No No INPUT
rma_req_i[3:0] No No No INPUT
rma_seed_i[31:0] No No No INPUT
rma_ack_o[3:0] No No No OUTPUT
pwrmgr_o.flash_idle Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1:0][255:0] No No No OUTPUT
cio_tck_i No No No INPUT
cio_tms_i No No No INPUT
cio_tdi_i No No No INPUT
cio_tdo_en_o No No No OUTPUT
cio_tdo_o No No No OUTPUT
intr_corr_err_o Yes Yes T19,T20,T21 Yes T19,T20,T21 OUTPUT
intr_prog_empty_o Yes Yes T19,T20,T22 Yes T19,T20,T22 OUTPUT
intr_prog_lvl_o Yes Yes T19,T20,T15 Yes T19,T20,T15 OUTPUT
intr_rd_full_o Yes Yes T19,T20,T21 Yes T19,T20,T21 OUTPUT
intr_rd_lvl_o Yes Yes T23,T19,T20 Yes T23,T19,T20 OUTPUT
intr_op_done_o Yes Yes T19,T20,T21 Yes T19,T20,T21 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T23,T24,T13 Yes T23,T24,T13 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T23,T24,T13 Yes T23,T24,T13 INPUT
alert_rx_i[1].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T23,T24,T13 Yes T23,T24,T13 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T23,T24,T13 Yes T23,T24,T13 OUTPUT
scan_en_i Unreachable Unreachable Unreachable INPUT
scanmode_i[3:0] Unreachable Unreachable Unreachable INPUT
scan_rst_ni Unreachable Unreachable Unreachable INPUT
flash_bist_enable_i[3:0] Unreachable Unreachable Unreachable INPUT
flash_power_down_h_i Yes Yes T1,T2,T3 Yes T13,T14,T15 INPUT
flash_power_ready_h_i Unreachable Unreachable Unreachable INPUT
flash_test_mode_a_io[1:0] No No No INOUT
flash_test_voltage_h_io No No No INOUT
flash_alert_o.n No No No OUTPUT
flash_alert_o.p No No No OUTPUT


Branch Coverage for Module : flash_ctrl
Line No.TotalCoveredPercent
Branches 16 12 75.00
TERNARY 756 2 2 100.00
TERNARY 867 2 1 50.00
TERNARY 874 2 1 50.00
TERNARY 927 2 1 50.00
TERNARY 927 2 1 50.00
IF 542 2 2 100.00
CASE 645 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl.sv' or '../src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 756 (sw_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 867 ((lc_escalate_en == On)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 874 ((lc_escalate_en == On)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 927 ((®2hw.ecc_single_err_cnt[0].q)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 927 ((®2hw.ecc_single_err_cnt[1].q)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 542 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 645 case (op_type)

Branches:
-1-StatusTests
FlashOpRead Covered T1,T2,T3
FlashOpProgram Covered T1,T2,T3
FlashOpErase Covered T1,T2,T3
default Covered T1,T2,T3


Assert Coverage for Module : flash_ctrl
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 18 18 100.00 15 83.33
Cover properties 0 0 0
Cover sequences 0 0 0
Total 18 18 100.00 15 83.33




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
FlashAddrKnown_A 2402452 2139116 0 0
FlashAddrKnown_AKnownEnable 2402452 2398414 0 0
FlashKnownO_A 2402452 2398414 0 0
FlashProgKnown_A 2402452 255269 0 0
FlashProgKnown_AKnownEnable 2402452 2398414 0 0
IntrErrO_A 2402452 2398414 0 0
IntrOpDoneKnownO_A 2402452 2398414 0 0
IntrProgEmptyKnownO_A 2402452 2398414 0 0
IntrProgLvlKnownO_A 2402452 2398414 0 0
IntrProgRdFullKnownO_A 2402452 2398414 0 0
IntrRdLvlKnownO_A 2402452 2398414 0 0
OutofBoundsReq_A 2402452 0 0 0
PageCntAlertCheck_A 2402452 0 0 0
PrimTlAReadyKnownO_A 2402452 2398414 0 0
PrimTlDValidKnownO_A 2402452 2398414 0 0
TlAReadyKnownO_A 2402452 2398414 0 0
TlDValidKnownO_A 2402452 2398414 0 0
WordCntAlertCheck_A 2402452 0 0 0


FlashAddrKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 2139116 0 0
T1 16544 7452 0 0
T2 218256 216061 0 0
T3 15128 8523 0 0
T4 2443 620 0 0
T5 5310 1565 0 0
T6 11803 5432 0 0
T7 14566 8247 0 0
T8 267592 266060 0 0
T9 541130 532863 0 0
T10 150985 141350 0 0

FlashAddrKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 2398414 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

FlashKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 2398414 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

FlashProgKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 255269 0 0
T1 16544 6723 0 0
T2 218256 14230 0 0
T3 15128 8178 0 0
T4 2443 100 0 0
T5 5310 1457 0 0
T6 11803 4892 0 0
T7 14566 7530 0 0
T9 541130 5198 0 0
T10 150985 6751 0 0
T11 336289 3909 0 0

FlashProgKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 2398414 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

IntrErrO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 2398414 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

IntrOpDoneKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 2398414 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

IntrProgEmptyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 2398414 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

IntrProgLvlKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 2398414 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

IntrProgRdFullKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 2398414 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

IntrRdLvlKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 2398414 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

OutofBoundsReq_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 0 0 0

PageCntAlertCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 0 0 0

PrimTlAReadyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 2398414 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

PrimTlDValidKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 2398414 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

TlAReadyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 2398414 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

TlDValidKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 2398414 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

WordCntAlertCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%