Unified Coverage Report :: Module :: flash_mp

Module : flash_mp

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.90	96.72	88.89			83.33	66.67

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_mp	83.90	96.72	88.89			83.33	66.67

---

Module Instance : tb.dut.u_flash_mp

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.90	96.72	88.89			83.33	66.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.13	97.65	88.89			83.33	66.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.52	91.74	69.23	13.28		75.00	83.33	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_hw_sel	100.00	100.00
u_sw_sel	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : flash_mp

	Line No.	Total	Covered	Percent
TOTAL		61	59	96.72
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
ALWAYS	172	0	0
ALWAYS	172	2	2	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	179	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	181	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	185	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
ALWAYS	213	7	7	100.00
CONT_ASSIGN	229	1	1	100.00
CONT_ASSIGN	233	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	237	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	252	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	255	1	1	100.00
CONT_ASSIGN	256	1	1	100.00
CONT_ASSIGN	257	1	1	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	262	1	1	100.00
ALWAYS	266	6	4	66.67
CONT_ASSIGN	275	1	1	100.00
CONT_ASSIGN	276	1	1	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	285	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
66	1	1
67	1	1
87	1	1
91	1	1
92	1	1
108	1	1
116	1	1
119	1	1
166	1	1
167	1	1
172	1	1
173	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
188	1	1
213	1	1
214	1	1
215	1	1
216	1	1
218	1	1
221	1	1
222	1	1
			MISSING_ELSE
			MISSING_ELSE
229	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
240	1	1
243	1	1
251	1	1
252	1	1
253	1	1
254	1	1
255	1	1
256	1	1
257	1	1
258	1	1
262	1	1
266	1	1
267	1	1
268	1	1
269	0	1
270	1	1
271	0	1
			MISSING_ELSE
275	1	1
276	1	1
277	1	1
278	1	1
283	1	1
284	1	1
285	1	1

---

Cond Coverage for Module : flash_mp

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       116
 EXPRESSION (data_part_sel ? flash_ctrl_pkg::DataPartitionEndAddr : flash_ctrl_pkg::InfoPartitionEndAddr[info_sel_i])
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (hw_sel ? hw_sel_cfg : sw_sel_cfg)
             ---1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       215
 EXPRESSION (hw_sel && req_i)
             ---1--    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       230
 EXPRESSION (hw_sel ? hw_page_cfg : info_page_cfgs_i[bank_addr][info_sel_i][info_page_addr])
             ---1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Module : flash_mp

	Line No.	Total	Covered	Percent
Branches		12	10	83.33
TERNARY	116	2	2	100.00
TERNARY	161	2	2	100.00
TERNARY	230	2	2	100.00
IF	215	2	2	100.00
IF	266	4	2	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	116	(data_part_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	161	(hw_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	230	(hw_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	215	if ((hw_sel && req_i))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	266	if ((!rst_ni))
-2-:	268	if (txn_err)
-3-:	270	if (no_allowed_txn)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_mp

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	9	9	100.00	6	66.67
Cover properties	0	0		0
Cover sequences	0	0		0
Total	9	9	100.00	6	66.67

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BankEraseData_a	2402452	1835120	0	0
BankEraseInfo_a	2402452	0	0	0
DataReqToInfo_a	2402452	2139116	0	0
InReqOutReq_a	2402452	2139116	0	0
InfoReqToData_a	2402452	0	0	0
bkEraseEnOnehot_a	2402452	1835120	0	0
hwInfoRuleOnehot_a	2402452	0	0	0
invalidReqOnehot_a	2402452	2139116	0	0
requestTypesOnehot_a	2402452	2139116	0	0

BankEraseData_a

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	1835120	0	0
T1	0	0	0	0
T2	218256	196620	0	0
T8	267592	262160	0	0
T9	541130	524320	0	0
T10	150985	131080	0	0
T11	336289	327700	0	0
T25	277820	262160	0	0
T27	70666	65540	0	0
T29	69919	65540	0	0

BankEraseInfo_a

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	0	0	0

DataReqToInfo_a

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	2139116	0	0
T1	16544	7452	0	0
T2	218256	216061	0	0
T3	15128	8523	0	0
T4	2443	620	0	0
T5	5310	1565	0	0
T6	11803	5432	0	0
T7	14566	8247	0	0
T8	267592	266060	0	0
T9	541130	532863	0	0
T10	150985	141350	0	0

InReqOutReq_a

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	2139116	0	0
T1	16544	7452	0	0
T2	218256	216061	0	0
T3	15128	8523	0	0
T4	2443	620	0	0
T5	5310	1565	0	0
T6	11803	5432	0	0
T7	14566	8247	0	0
T8	267592	266060	0	0
T9	541130	532863	0	0
T10	150985	141350	0	0

InfoReqToData_a

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	0	0	0

bkEraseEnOnehot_a

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	1835120	0	0
T1	0	0	0	0
T2	218256	196620	0	0
T8	267592	262160	0	0
T9	541130	524320	0	0
T10	150985	131080	0	0
T11	336289	327700	0	0
T25	277820	262160	0	0
T27	70666	65540	0	0
T29	69919	65540	0	0

hwInfoRuleOnehot_a

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	0	0	0

invalidReqOnehot_a

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	2139116	0	0
T1	16544	7452	0	0
T2	218256	216061	0	0
T3	15128	8523	0	0
T4	2443	620	0	0
T5	5310	1565	0	0
T6	11803	5432	0	0
T7	14566	8247	0	0
T8	267592	266060	0	0
T9	541130	532863	0	0
T10	150985	141350	0	0

requestTypesOnehot_a

Name	Attempts	Real Successes	Failures	Incomplete
Total	2402452	2139116	0	0
T1	16544	7452	0	0
T2	218256	216061	0	0
T3	15128	8523	0	0
T4	2443	620	0	0
T5	5310	1565	0	0
T6	11803	5432	0	0
T7	14566	8247	0	0
T8	267592	266060	0	0
T9	541130	532863	0	0
T10	150985	141350	0	0