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Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
fifo_h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
fifo_h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dfifo[0].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dfifo[0].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dfifo[1].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dfifo[1].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dfifo[2].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dfifo[2].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo
Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5100
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 1 1
43 1 1
46 1 1
47 1 1
51 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 10560772 3153355 0 0
DepthKnown_A 10560772 10169856 0 0
RvalidKnown_A 10560772 10169856 0 0
WreadyKnown_A 10560772 10169856 0 0
gen_passthru_fifo.paramCheckPass 279 279 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10560772 3153355 0 0
T1 16544 1532 0 0
T2 218256 109116 0 0
T3 15128 2085 0 0
T4 2443 263 0 0
T5 5310 455 0 0
T6 11803 1662 0 0
T7 14566 2078 0 0
T8 267592 38172 0 0
T9 541130 51543 0 0
T10 150985 21457 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10560772 10169856 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10560772 10169856 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10560772 10169856 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 279 279 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5100
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 1 1
43 1 1
46 1 1
47 1 1
51 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 10560772 3922295 0 0
DepthKnown_A 10560772 10169856 0 0
RvalidKnown_A 10560772 10169856 0 0
WreadyKnown_A 10560772 10169856 0 0
gen_passthru_fifo.paramCheckPass 279 279 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10560772 3922295 0 0
T1 16544 7012 0 0
T2 218256 108681 0 0
T3 15128 2080 0 0
T4 2443 263 0 0
T5 5310 2039 0 0
T6 11803 1655 0 0
T7 14566 2064 0 0
T8 267592 38172 0 0
T9 541130 230934 0 0
T10 150985 21446 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10560772 10169856 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10560772 10169856 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10560772 10169856 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 279 279 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5100
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 1 1
43 1 1
46 1 1
47 1 1
51 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 10560772 13979 0 0
DepthKnown_A 10560772 10169856 0 0
RvalidKnown_A 10560772 10169856 0 0
WreadyKnown_A 10560772 10169856 0 0
gen_passthru_fifo.paramCheckPass 279 279 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10560772 13979 0 0
T1 16544 253 0 0
T2 218256 480 0 0
T3 15128 273 0 0
T4 2443 4 0 0
T5 5310 46 0 0
T6 11803 157 0 0
T7 14566 253 0 0
T9 541130 193 0 0
T10 150985 226 0 0
T11 336289 126 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10560772 10169856 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10560772 10169856 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10560772 10169856 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 279 279 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5100
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 1 1
43 1 1
46 1 1
47 1 1
51 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 10560772 28296 0 0
DepthKnown_A 10560772 10169856 0 0
RvalidKnown_A 10560772 10169856 0 0
WreadyKnown_A 10560772 10169856 0 0
gen_passthru_fifo.paramCheckPass 279 279 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10560772 28296 0 0
T1 16544 1203 0 0
T2 218256 480 0 0
T3 15128 273 0 0
T4 2443 4 0 0
T5 5310 236 0 0
T6 11803 157 0 0
T7 14566 253 0 0
T9 541130 912 0 0
T10 150985 226 0 0
T11 336289 126 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10560772 10169856 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10560772 10169856 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10560772 10169856 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 279 279 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5100
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 1 1
43 1 1
46 1 1
47 1 1
51 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 10560772 16479 0 0
DepthKnown_A 10560772 10169856 0 0
RvalidKnown_A 10560772 10169856 0 0
WreadyKnown_A 10560772 10169856 0 0
gen_passthru_fifo.paramCheckPass 279 279 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10560772 16479 0 0
T1 16544 243 0 0
T2 218256 872 0 0
T3 15128 120 0 0
T5 5310 36 0 0
T6 11803 187 0 0
T7 14566 253 0 0
T9 541130 75 0 0
T10 150985 404 0 0
T11 336289 278 0 0
T12 5785 57 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10560772 10169856 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10560772 10169856 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10560772 10169856 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 279 279 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5100
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 1 1
43 1 1
46 1 1
47 1 1
51 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 10560772 26962 0 0
DepthKnown_A 10560772 10169856 0 0
RvalidKnown_A 10560772 10169856 0 0
WreadyKnown_A 10560772 10169856 0 0
gen_passthru_fifo.paramCheckPass 279 279 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10560772 26962 0 0
T1 16544 1096 0 0
T2 218256 437 0 0
T3 15128 115 0 0
T5 5310 130 0 0
T6 11803 180 0 0
T7 14566 239 0 0
T9 541130 326 0 0
T10 150985 393 0 0
T11 336289 138 0 0
T12 5785 57 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10560772 10169856 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10560772 10169856 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10560772 10169856 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 279 279 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5100
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 1 1
43 1 1
46 1 1
47 1 1
51 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 10560772 3117316 0 0
DepthKnown_A 10560772 10169856 0 0
RvalidKnown_A 10560772 10169856 0 0
WreadyKnown_A 10560772 10169856 0 0
gen_passthru_fifo.paramCheckPass 279 279 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10560772 3117316 0 0
T1 16544 1036 0 0
T2 218256 107764 0 0
T3 15128 1692 0 0
T4 2443 259 0 0
T5 5310 373 0 0
T6 11803 1318 0 0
T7 14566 1572 0 0
T8 267592 38172 0 0
T9 541130 51275 0 0
T10 150985 20827 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10560772 10169856 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10560772 10169856 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10560772 10169856 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 279 279 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5100
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 1 1
43 1 1
46 1 1
47 1 1
51 unreachable


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 10560772 3867037 0 0
DepthKnown_A 10560772 10169856 0 0
RvalidKnown_A 10560772 10169856 0 0
WreadyKnown_A 10560772 10169856 0 0
gen_passthru_fifo.paramCheckPass 279 279 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10560772 3867037 0 0
T1 16544 4713 0 0
T2 218256 107764 0 0
T3 15128 1692 0 0
T4 2443 259 0 0
T5 5310 1673 0 0
T6 11803 1318 0 0
T7 14566 1572 0 0
T8 267592 38172 0 0
T9 541130 229696 0 0
T10 150985 20827 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10560772 10169856 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10560772 10169856 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10560772 10169856 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 279 279 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%