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Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
59.44 77.78 50.00 50.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
59.44 77.78 50.00 50.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
77.93 98.23 55.00 67.57 90.91 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
58.31 77.78 45.45 50.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
58.31 77.78 45.45 50.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
65.48 96.43 50.00 50.00 u_eflash


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.i_rsp_order_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.08 100.00 83.33 85.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.08 100.00 83.33 85.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
77.93 98.23 55.00 67.57 90.91 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.08 100.00 83.33 85.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.08 100.00 83.33 85.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
77.93 98.23 55.00 67.57 90.91 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
59.44 77.78 50.00 50.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
59.44 77.78 50.00 50.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
77.93 98.23 55.00 67.57 90.91 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.i_rsp_order_fifo
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage
Line No.TotalCoveredPercent
TOTAL362877.78
ALWAYS6544100.00
CONT_ASSIGN7911100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9511100.00
ALWAYS987457.14
ALWAYS1127457.14
CONT_ASSIGN12511100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN13411100.00
ALWAYS1372150.00
CONT_ASSIGN155100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
79 1 1
80 1 1
81 1 1
82 1 1
83 1 1
87 1 1
88 1 1
93 1 1
94 1 1
95 1 1
98 1 1
99 1 1
100 1 1
101 unreachable
102 1 1
103 0 1
104 0 1
106 0 1
MISSING_ELSE
112 1 1
113 1 1
114 1 1
115 unreachable
116 1 1
117 0 1
118 0 1
120 0 1
MISSING_ELSE
125 1 1
126 1 1
134 1 1
137 1 1
138 0 1
MISSING_ELSE
155 0 1
156 1 1
162 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage
TotalCoveredPercent
Conditions6350.00
Logical6350.00
Non-Logical00
Event00

 LINE       83
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       83
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage
Line No.TotalCoveredPercent
Branches 20 10 50.00
TERNARY 83 3 1 33.33
TERNARY 160 2 1 50.00
IF 65 3 3 100.00
IF 98 5 2 40.00
IF 112 5 2 40.00
IF 137 2 1 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 83 (gen_normal_fifo.full) ? -2-: 83 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T2,T3
0 0 Not Covered


LineNo. Expression -1-: 160 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 98 if ((!rst_ni)) -2-: 100 if (clr_i) -3-: 102 if (gen_normal_fifo.fifo_incr_wptr) -4-: 103 if ((gen_normal_fifo.fifo_wptr[0] == 1'((Depth - 1))))

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Not Covered
0 0 1 1 Not Covered
0 0 1 0 Not Covered
0 0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 112 if ((!rst_ni)) -2-: 114 if (clr_i) -3-: 116 if (gen_normal_fifo.fifo_incr_rptr) -4-: 117 if ((gen_normal_fifo.fifo_rptr[0] == 1'((Depth - 1))))

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Not Covered
0 0 1 1 Not Covered
0 0 1 0 Not Covered
0 0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 137 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 3 60.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 3 60.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 2402452 0 0 0
DepthKnown_A 2402452 2398414 0 0
RvalidKnown_A 2402452 2398414 0 0
WreadyKnown_A 2402452 2398414 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 2402452 0 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 2398414 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 2398414 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 2398414 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 0 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo
Line No.TotalCoveredPercent
TOTAL362877.78
ALWAYS6544100.00
CONT_ASSIGN7911100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9511100.00
ALWAYS987457.14
ALWAYS1127457.14
CONT_ASSIGN12511100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN134100.00
ALWAYS1372150.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
79 1 1
80 1 1
81 1 1
82 1 1
83 1 1
87 1 1
88 1 1
93 1 1
94 1 1
95 1 1
98 1 1
99 1 1
100 1 1
101 unreachable
102 1 1
103 0 1
104 0 1
106 0 1
MISSING_ELSE
112 1 1
113 1 1
114 1 1
115 unreachable
116 1 1
117 0 1
118 0 1
120 0 1
MISSING_ELSE
125 1 1
126 1 1
134 0 1
137 1 1
138 0 1
MISSING_ELSE
155 1 1
156 1 1
162 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo
TotalCoveredPercent
Conditions11545.45
Logical11545.45
Non-Logical00
Event00

 LINE       83
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       83
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       152
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       152
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       160
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo
Line No.TotalCoveredPercent
Branches 22 11 50.00
TERNARY 83 3 1 33.33
TERNARY 152 2 1 50.00
TERNARY 160 2 1 50.00
IF 65 3 3 100.00
IF 98 5 2 40.00
IF 112 5 2 40.00
IF 137 2 1 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 83 (gen_normal_fifo.full) ? -2-: 83 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T2,T3
0 0 Not Covered


LineNo. Expression -1-: 152 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 160 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 98 if ((!rst_ni)) -2-: 100 if (clr_i) -3-: 102 if (gen_normal_fifo.fifo_incr_wptr) -4-: 103 if ((gen_normal_fifo.fifo_wptr[0] == 1'((Depth - 1))))

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Not Covered
0 0 1 1 Not Covered
0 0 1 0 Not Covered
0 0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 112 if ((!rst_ni)) -2-: 114 if (clr_i) -3-: 116 if (gen_normal_fifo.fifo_incr_rptr) -4-: 117 if ((gen_normal_fifo.fifo_rptr[0] == 1'((Depth - 1))))

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Not Covered
0 0 1 1 Not Covered
0 0 1 0 Not Covered
0 0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 137 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 3 60.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 3 60.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 2402452 0 0 0
DepthKnown_A 2402452 2398414 0 0
RvalidKnown_A 2402452 2398414 0 0
WreadyKnown_A 2402452 2398414 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 2402452 0 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 2398414 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 2398414 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 2398414 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 0 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.i_rsp_order_fifo
Line No.TotalCoveredPercent
TOTAL3636100.00
ALWAYS6544100.00
CONT_ASSIGN7911100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9511100.00
ALWAYS9877100.00
ALWAYS11277100.00
CONT_ASSIGN12511100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN13411100.00
ALWAYS13722100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
79 1 1
80 1 1
81 1 1
82 1 1
83 1 1
87 1 1
88 1 1
93 1 1
94 1 1
95 1 1
98 1 1
99 1 1
100 1 1
101 unreachable
102 1 1
103 1 1
104 1 1
106 1 1
MISSING_ELSE
112 1 1
113 1 1
114 1 1
115 unreachable
116 1 1
117 1 1
118 1 1
120 1 1
MISSING_ELSE
125 1 1
126 1 1
134 1 1
137 1 1
138 1 1
MISSING_ELSE
155 1 1
156 1 1
162 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.i_rsp_order_fifo
TotalCoveredPercent
Conditions6583.33
Logical6583.33
Non-Logical00
Event00

 LINE       83
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       83
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.i_rsp_order_fifo
Line No.TotalCoveredPercent
Branches 20 17 85.00
TERNARY 83 3 2 66.67
TERNARY 160 2 2 100.00
IF 65 3 3 100.00
IF 98 5 4 80.00
IF 112 5 4 80.00
IF 137 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 83 (gen_normal_fifo.full) ? -2-: 83 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 160 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 98 if ((!rst_ni)) -2-: 100 if (clr_i) -3-: 102 if (gen_normal_fifo.fifo_incr_wptr) -4-: 103 if ((gen_normal_fifo.fifo_wptr[0] == 1'((Depth - 1))))

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Not Covered
0 0 1 1 Covered T1,T2,T3
0 0 1 0 Covered T1,T2,T3
0 0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 112 if ((!rst_ni)) -2-: 114 if (clr_i) -3-: 116 if (gen_normal_fifo.fifo_incr_rptr) -4-: 117 if ((gen_normal_fifo.fifo_rptr[0] == 1'((Depth - 1))))

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Not Covered
0 0 1 1 Covered T1,T2,T3
0 0 1 0 Covered T1,T2,T3
0 0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 137 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.i_rsp_order_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 2402452 8754 0 0
DepthKnown_A 2402452 2398414 0 0
RvalidKnown_A 2402452 2398414 0 0
WreadyKnown_A 2402452 2398414 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 2402452 8754 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 8754 0 0
T1 16544 230 0 0
T2 218256 362 0 0
T3 15128 210 0 0
T6 11803 40 0 0
T7 14566 436 0 0
T9 541130 150 0 0
T10 150985 412 0 0
T11 336289 182 0 0
T12 5785 60 0 0
T26 526 24 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 2398414 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 2398414 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 2398414 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 8754 0 0
T1 16544 230 0 0
T2 218256 362 0 0
T3 15128 210 0 0
T6 11803 40 0 0
T7 14566 436 0 0
T9 541130 150 0 0
T10 150985 412 0 0
T11 336289 182 0 0
T12 5785 60 0 0
T26 526 24 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage
Line No.TotalCoveredPercent
TOTAL3636100.00
ALWAYS6544100.00
CONT_ASSIGN7911100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9511100.00
ALWAYS9877100.00
ALWAYS11277100.00
CONT_ASSIGN12511100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN13411100.00
ALWAYS13722100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
79 1 1
80 1 1
81 1 1
82 1 1
83 1 1
87 1 1
88 1 1
93 1 1
94 1 1
95 1 1
98 1 1
99 1 1
100 1 1
101 unreachable
102 1 1
103 1 1
104 1 1
106 1 1
MISSING_ELSE
112 1 1
113 1 1
114 1 1
115 unreachable
116 1 1
117 1 1
118 1 1
120 1 1
MISSING_ELSE
125 1 1
126 1 1
134 1 1
137 1 1
138 1 1
MISSING_ELSE
155 1 1
156 1 1
162 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage
TotalCoveredPercent
Conditions6583.33
Logical6583.33
Non-Logical00
Event00

 LINE       83
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       83
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage
Line No.TotalCoveredPercent
Branches 20 17 85.00
TERNARY 83 3 2 66.67
TERNARY 160 2 2 100.00
IF 65 3 3 100.00
IF 98 5 4 80.00
IF 112 5 4 80.00
IF 137 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 83 (gen_normal_fifo.full) ? -2-: 83 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 160 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 98 if ((!rst_ni)) -2-: 100 if (clr_i) -3-: 102 if (gen_normal_fifo.fifo_incr_wptr) -4-: 103 if ((gen_normal_fifo.fifo_wptr[0] == 1'((Depth - 1))))

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Not Covered
0 0 1 1 Covered T1,T2,T3
0 0 1 0 Covered T1,T2,T3
0 0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 112 if ((!rst_ni)) -2-: 114 if (clr_i) -3-: 116 if (gen_normal_fifo.fifo_incr_rptr) -4-: 117 if ((gen_normal_fifo.fifo_rptr[0] == 1'((Depth - 1))))

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Not Covered
0 0 1 1 Covered T1,T2,T3
0 0 1 0 Covered T1,T2,T3
0 0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 137 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 2402452 4377 0 0
DepthKnown_A 2402452 2398414 0 0
RvalidKnown_A 2402452 2398414 0 0
WreadyKnown_A 2402452 2398414 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 2402452 4377 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 4377 0 0
T1 16544 115 0 0
T2 218256 181 0 0
T3 15128 105 0 0
T6 11803 20 0 0
T7 14566 218 0 0
T9 541130 75 0 0
T10 150985 206 0 0
T11 336289 91 0 0
T12 5785 30 0 0
T26 526 12 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 2398414 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 2398414 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 2398414 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 4377 0 0
T1 16544 115 0 0
T2 218256 181 0 0
T3 15128 105 0 0
T6 11803 20 0 0
T7 14566 218 0 0
T9 541130 75 0 0
T10 150985 206 0 0
T11 336289 91 0 0
T12 5785 30 0 0
T26 526 12 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage
Line No.TotalCoveredPercent
TOTAL362877.78
ALWAYS6544100.00
CONT_ASSIGN7911100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9511100.00
ALWAYS987457.14
ALWAYS1127457.14
CONT_ASSIGN12511100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN13411100.00
ALWAYS1372150.00
CONT_ASSIGN155100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
79 1 1
80 1 1
81 1 1
82 1 1
83 1 1
87 1 1
88 1 1
93 1 1
94 1 1
95 1 1
98 1 1
99 1 1
100 1 1
101 unreachable
102 1 1
103 0 1
104 0 1
106 0 1
MISSING_ELSE
112 1 1
113 1 1
114 1 1
115 unreachable
116 1 1
117 0 1
118 0 1
120 0 1
MISSING_ELSE
125 1 1
126 1 1
134 1 1
137 1 1
138 0 1
MISSING_ELSE
155 0 1
156 1 1
162 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage
TotalCoveredPercent
Conditions6350.00
Logical6350.00
Non-Logical00
Event00

 LINE       83
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       83
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage
Line No.TotalCoveredPercent
Branches 20 10 50.00
TERNARY 83 3 1 33.33
TERNARY 160 2 1 50.00
IF 65 3 3 100.00
IF 98 5 2 40.00
IF 112 5 2 40.00
IF 137 2 1 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 83 (gen_normal_fifo.full) ? -2-: 83 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T2,T3
0 0 Not Covered


LineNo. Expression -1-: 160 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 65 if ((!rst_ni)) -2-: 67 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 98 if ((!rst_ni)) -2-: 100 if (clr_i) -3-: 102 if (gen_normal_fifo.fifo_incr_wptr) -4-: 103 if ((gen_normal_fifo.fifo_wptr[0] == 1'((Depth - 1))))

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Not Covered
0 0 1 1 Not Covered
0 0 1 0 Not Covered
0 0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 112 if ((!rst_ni)) -2-: 114 if (clr_i) -3-: 116 if (gen_normal_fifo.fifo_incr_rptr) -4-: 117 if ((gen_normal_fifo.fifo_rptr[0] == 1'((Depth - 1))))

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Not Covered
0 0 1 1 Not Covered
0 0 1 0 Not Covered
0 0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 137 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 3 60.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 3 60.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 2402452 0 0 0
DepthKnown_A 2402452 2398414 0 0
RvalidKnown_A 2402452 2398414 0 0
WreadyKnown_A 2402452 2398414 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 2402452 0 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 2398414 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 2398414 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 2398414 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%