Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
52.48 52.48 u_region_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
52.48 52.48 u_region_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
52.48 52.48 u_region_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
52.48 52.48 u_region_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_lc_seed_hw_rd_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
66.52 91.74 69.23 13.28 75.00 83.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_sync_rma_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
43.26 90.59 13.46 0.00 68.97 u_flash_hw_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_lc_escalation_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
66.52 91.74 69.23 13.28 75.00 83.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
65.48 96.43 50.00 50.00 u_eflash


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=1,AsyncOn=1,ResetValueIsOn=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync

SCORELINE
100.00 100.00
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync

SCORELINE
100.00 100.00
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync

SCORELINE
100.00 100.00
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync

SCORELINE
100.00 100.00
tb.dut.u_lc_seed_hw_rd_en_sync

SCORELINE
100.00 100.00
tb.dut.u_flash_hw_if.u_sync_rma_req

SCORELINE
100.00 100.00
tb.dut.u_lc_escalation_en_sync

Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN6511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1


Line Coverage for Module : prim_lc_sync ( parameter NumCopies=5,AsyncOn=1,ResetValueIsOn=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_eflash.u_lc_nvm_debug_en_sync

Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN6511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 5 5


Assert Coverage for Module : prim_lc_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 440 440 0 0
OutputsKnown_A 19219616 19187312 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 440 440 0 0
T1 8 8 0 0
T2 8 8 0 0
T3 8 8 0 0
T4 8 8 0 0
T5 8 8 0 0
T6 8 8 0 0
T7 8 8 0 0
T8 8 8 0 0
T9 8 8 0 0
T10 8 8 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 19219616 19187312 0 0
T1 132352 131856 0 0
T2 1746048 1745440 0 0
T3 121024 120448 0 0
T4 19544 18968 0 0
T5 42480 41720 0 0
T6 94424 93832 0 0
T7 116528 115936 0 0
T8 2140736 2140080 0 0
T9 4329040 4328376 0 0
T10 1207880 1207376 0 0

Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN6511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1


Assert Coverage for Instance : tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 55 55 0 0
OutputsKnown_A 2402452 2398414 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 2398414 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN6511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1


Assert Coverage for Instance : tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 55 55 0 0
OutputsKnown_A 2402452 2398414 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 2398414 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN6511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1


Assert Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 55 55 0 0
OutputsKnown_A 2402452 2398414 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 2398414 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN6511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1


Assert Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 55 55 0 0
OutputsKnown_A 2402452 2398414 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 2398414 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

Line Coverage for Instance : tb.dut.u_lc_seed_hw_rd_en_sync
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN6511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1


Assert Coverage for Instance : tb.dut.u_lc_seed_hw_rd_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 55 55 0 0
OutputsKnown_A 2402452 2398414 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 2398414 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

Line Coverage for Instance : tb.dut.u_flash_hw_if.u_sync_rma_req
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN6511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1


Assert Coverage for Instance : tb.dut.u_flash_hw_if.u_sync_rma_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 55 55 0 0
OutputsKnown_A 2402452 2398414 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 2398414 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

Line Coverage for Instance : tb.dut.u_lc_escalation_en_sync
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN6511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1


Assert Coverage for Instance : tb.dut.u_lc_escalation_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 55 55 0 0
OutputsKnown_A 2402452 2398414 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 2398414 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN6511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 5 5


Assert Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 55 55 0 0
OutputsKnown_A 2402452 2398414 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55 55 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2402452 2398414 0 0
T1 16544 16482 0 0
T2 218256 218180 0 0
T3 15128 15056 0 0
T4 2443 2371 0 0
T5 5310 5215 0 0
T6 11803 11729 0 0
T7 14566 14492 0 0
T8 267592 267510 0 0
T9 541130 541047 0 0
T10 150985 150922 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%