Module Definition
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Module : prim_subreg_arb
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg_core.u_intr_state_prog_empty.wr_en_data_arb 100.00 100.00
tb.dut.u_reg_core.u_intr_state_prog_lvl.wr_en_data_arb 100.00 100.00
tb.dut.u_reg_core.u_intr_state_rd_full.wr_en_data_arb 100.00 100.00
tb.dut.u_reg_core.u_intr_state_rd_lvl.wr_en_data_arb 100.00 100.00
tb.dut.u_reg_core.u_intr_state_op_done.wr_en_data_arb 100.00 100.00
tb.dut.u_reg_core.u_intr_state_corr_err.wr_en_data_arb 100.00 100.00
tb.dut.u_reg_core.u_intr_enable_prog_empty.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_intr_enable_prog_lvl.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_intr_enable_rd_full.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_intr_enable_rd_lvl.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_intr_enable_op_done.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_intr_enable_corr_err.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_dis.wr_en_data_arb 100.00 100.00
tb.dut.u_reg_core.u_exec.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_init.wr_en_data_arb 100.00 100.00
tb.dut.u_reg_core.u_control_start.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_control_op.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_control_prog_sel.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_control_erase_sel.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_control_partition_sel.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_control_info_sel.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_control_num.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_addr.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_prog_type_en_normal.wr_en_data_arb 100.00 100.00
tb.dut.u_reg_core.u_prog_type_en_repair.wr_en_data_arb 100.00 100.00
tb.dut.u_reg_core.u_erase_suspend.wr_en_data_arb 66.67 100.00 50.00 50.00
tb.dut.u_reg_core.u_region_cfg_regwen_0.wr_en_data_arb 100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_1.wr_en_data_arb 100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_2.wr_en_data_arb 100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_3.wr_en_data_arb 100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_4.wr_en_data_arb 100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_5.wr_en_data_arb 100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_6.wr_en_data_arb 100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_7.wr_en_data_arb 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_en_0.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_en_0.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_en_0.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_rd_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_rd_en_0.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_rd_en_0.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_rd_en_0.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_prog_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_prog_en_0.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_prog_en_0.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_prog_en_0.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_erase_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_erase_en_0.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_erase_en_0.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_erase_en_0.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_scramble_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_scramble_en_0.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_scramble_en_0.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_scramble_en_0.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_ecc_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_ecc_en_0.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_ecc_en_0.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_ecc_en_0.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_he_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_he_en_0.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_he_en_0.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_he_en_0.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_base_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_base_0.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_base_0.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_base_0.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_size_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_size_0.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_size_0.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_size_0.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_en_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_en_1.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_en_1.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_en_1.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_rd_en_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_rd_en_1.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_rd_en_1.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_rd_en_1.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_prog_en_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_prog_en_1.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_prog_en_1.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_prog_en_1.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_erase_en_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_erase_en_1.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_erase_en_1.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_erase_en_1.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_scramble_en_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_scramble_en_1.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_scramble_en_1.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_scramble_en_1.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_ecc_en_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_ecc_en_1.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_ecc_en_1.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_ecc_en_1.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_he_en_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_he_en_1.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_he_en_1.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_he_en_1.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_base_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_base_1.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_base_1.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_base_1.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_size_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_size_1.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_size_1.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_size_1.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_en_2.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_en_2.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_en_2.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_en_2.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_rd_en_2.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_rd_en_2.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_rd_en_2.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_rd_en_2.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_prog_en_2.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_prog_en_2.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_prog_en_2.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_prog_en_2.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_erase_en_2.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_erase_en_2.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_erase_en_2.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_erase_en_2.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_scramble_en_2.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_scramble_en_2.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_scramble_en_2.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_scramble_en_2.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_ecc_en_2.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_ecc_en_2.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_ecc_en_2.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_ecc_en_2.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_he_en_2.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_he_en_2.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_he_en_2.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_he_en_2.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_base_2.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_base_2.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_base_2.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_base_2.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_size_2.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_size_2.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_size_2.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_size_2.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_3_en_3.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_3_en_3.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_3_en_3.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_3_en_3.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_3_rd_en_3.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_3_rd_en_3.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_3_rd_en_3.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_3_rd_en_3.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_3_prog_en_3.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_3_prog_en_3.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_3_prog_en_3.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_3_prog_en_3.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_3_erase_en_3.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_3_erase_en_3.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_3_erase_en_3.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_3_erase_en_3.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_3_scramble_en_3.wr_en_data_arb 100.00 100.00 100.00 100.00
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tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_1_rd_en_1.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
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tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_1_he_en_1.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
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tb.dut.u_reg_core.u_bank0_info0_page_cfg_shadowed_2_en_2.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
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tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_0_ecc_en_0.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
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tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_1_ecc_en_1.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
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tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_1_he_en_1.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
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tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_2_en_2.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_2_en_2.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
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tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_2_rd_en_2.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_2_rd_en_2.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
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tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_2_scramble_en_2.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_2_scramble_en_2.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
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tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_2_ecc_en_2.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_2_ecc_en_2.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_2_ecc_en_2.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
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tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_2_he_en_2.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_2_he_en_2.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
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tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_3_en_3.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
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tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_9_ecc_en_9.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_9_ecc_en_9.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_9_ecc_en_9.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_9_he_en_9.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_9_he_en_9.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_9_he_en_9.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_shadowed_9_he_en_9.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_regwen.wr_en_data_arb 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_shadowed_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_shadowed_en_0.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_shadowed_en_0.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_shadowed_en_0.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_shadowed_rd_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_shadowed_rd_en_0.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_shadowed_rd_en_0.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_shadowed_rd_en_0.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_shadowed_prog_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_shadowed_prog_en_0.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_shadowed_prog_en_0.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_shadowed_prog_en_0.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_shadowed_erase_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_shadowed_erase_en_0.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_shadowed_erase_en_0.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_shadowed_erase_en_0.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_shadowed_scramble_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_shadowed_scramble_en_0.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_shadowed_scramble_en_0.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_shadowed_scramble_en_0.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_shadowed_ecc_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_shadowed_ecc_en_0.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_shadowed_ecc_en_0.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_shadowed_ecc_en_0.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_shadowed_he_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_shadowed_he_en_0.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_shadowed_he_en_0.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_shadowed_he_en_0.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_regwen_0.wr_en_data_arb 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_regwen_1.wr_en_data_arb 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_0_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_0_en_0.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_0_en_0.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_0_en_0.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_0_rd_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_0_rd_en_0.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_0_rd_en_0.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_0_rd_en_0.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_0_prog_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_0_prog_en_0.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_0_prog_en_0.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_0_prog_en_0.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_0_erase_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_0_erase_en_0.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_0_erase_en_0.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_0_erase_en_0.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_0_scramble_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_0_scramble_en_0.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_0_scramble_en_0.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_0_scramble_en_0.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_0_ecc_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_0_ecc_en_0.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_0_ecc_en_0.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_0_ecc_en_0.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_0_he_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_0_he_en_0.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_0_he_en_0.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_0_he_en_0.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_1_en_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_1_en_1.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_1_en_1.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_1_en_1.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_1_rd_en_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_1_rd_en_1.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_1_rd_en_1.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_1_rd_en_1.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_1_prog_en_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_1_prog_en_1.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_1_prog_en_1.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_1_prog_en_1.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_1_erase_en_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_1_erase_en_1.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_1_erase_en_1.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_1_erase_en_1.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_1_scramble_en_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_1_scramble_en_1.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_1_scramble_en_1.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_1_scramble_en_1.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_1_ecc_en_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_1_ecc_en_1.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_1_ecc_en_1.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_1_ecc_en_1.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_1_he_en_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_1_he_en_1.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_1_he_en_1.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_1_he_en_1.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank_cfg_regwen.wr_en_data_arb 100.00 100.00
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_op_status_done.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_op_status_err.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_status_rd_full.wr_en_data_arb 100.00 100.00
tb.dut.u_reg_core.u_status_rd_empty.wr_en_data_arb 100.00 100.00
tb.dut.u_reg_core.u_status_prog_full.wr_en_data_arb 100.00 100.00
tb.dut.u_reg_core.u_status_prog_empty.wr_en_data_arb 100.00 100.00
tb.dut.u_reg_core.u_status_init_wip.wr_en_data_arb 66.67 66.67
tb.dut.u_reg_core.u_err_code_oob_err.wr_en_data_arb 100.00 100.00
tb.dut.u_reg_core.u_err_code_mp_err.wr_en_data_arb 100.00 100.00
tb.dut.u_reg_core.u_err_code_rd_err.wr_en_data_arb 100.00 100.00
tb.dut.u_reg_core.u_err_code_prog_win_err.wr_en_data_arb 100.00 100.00
tb.dut.u_reg_core.u_err_code_prog_type_err.wr_en_data_arb 100.00 100.00
tb.dut.u_reg_core.u_err_code_flash_phy_err.wr_en_data_arb 100.00 100.00
tb.dut.u_reg_core.u_err_code_update_err.wr_en_data_arb 100.00 100.00
tb.dut.u_reg_core.u_fault_status_oob_err.wr_en_data_arb 66.67 66.67
tb.dut.u_reg_core.u_fault_status_mp_err.wr_en_data_arb 66.67 66.67
tb.dut.u_reg_core.u_fault_status_rd_err.wr_en_data_arb 66.67 66.67
tb.dut.u_reg_core.u_fault_status_prog_win_err.wr_en_data_arb 66.67 66.67
tb.dut.u_reg_core.u_fault_status_prog_type_err.wr_en_data_arb 66.67 66.67
tb.dut.u_reg_core.u_fault_status_flash_phy_err.wr_en_data_arb 66.67 66.67
tb.dut.u_reg_core.u_fault_status_reg_intg_err.wr_en_data_arb 66.67 66.67
tb.dut.u_reg_core.u_fault_status_phy_intg_err.wr_en_data_arb 66.67 66.67
tb.dut.u_reg_core.u_fault_status_lcmgr_err.wr_en_data_arb 66.67 66.67
tb.dut.u_reg_core.u_fault_status_storage_err.wr_en_data_arb 66.67 66.67
tb.dut.u_reg_core.u_err_addr.wr_en_data_arb 100.00 100.00
tb.dut.u_reg_core.u_ecc_single_err_cnt_ecc_single_err_cnt_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_ecc_single_err_cnt_ecc_single_err_cnt_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_ecc_single_err_addr_0.wr_en_data_arb 100.00 100.00
tb.dut.u_reg_core.u_ecc_single_err_addr_1.wr_en_data_arb 100.00 100.00
tb.dut.u_reg_core.u_phy_err_cfg_regwen.wr_en_data_arb 100.00 100.00
tb.dut.u_reg_core.u_phy_err_cfg.wr_en_data_arb 66.67 100.00 50.00 50.00
tb.dut.u_reg_core.u_phy_alert_cfg_alert_ack.wr_en_data_arb 66.67 100.00 50.00 50.00
tb.dut.u_reg_core.u_phy_alert_cfg_alert_trig.wr_en_data_arb 66.67 100.00 50.00 50.00
tb.dut.u_reg_core.u_phy_status_init_wip.wr_en_data_arb 66.67 66.67
tb.dut.u_reg_core.u_phy_status_prog_normal_avail.wr_en_data_arb 33.33 33.33
tb.dut.u_reg_core.u_phy_status_prog_repair_avail.wr_en_data_arb 33.33 33.33
tb.dut.u_reg_core.u_scratch.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_fifo_lvl_prog.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_fifo_lvl_rd.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_fifo_rst.wr_en_data_arb 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=3 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_intr_state_prog_empty.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_intr_state_prog_lvl.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_intr_state_rd_full.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_intr_state_rd_lvl.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_intr_state_op_done.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_intr_state_corr_err.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_err_code_oob_err.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_err_code_mp_err.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_err_code_rd_err.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_err_code_prog_win_err.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_err_code_prog_type_err.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_err_code_flash_phy_err.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_err_code_update_err.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_dis.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_prog_type_en_normal.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_prog_type_en_repair.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_4.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_5.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_6.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_7.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_4.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_5.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_6.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_7.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_8.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_9.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info1_regwen.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_regwen_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_regwen_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_4.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_5.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_6.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_7.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_8.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_9.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_regwen.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_regwen_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_regwen_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank_cfg_regwen.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_phy_err_cfg_regwen.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_init.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=0 + DW=4,SwAccess=0 + DW=2,SwAccess=0 + DW=12,SwAccess=0 + DW=32,SwAccess=0 + DW=9,SwAccess=0 + DW=10,SwAccess=0 + DW=8,SwAccess=0 + DW=5,SwAccess=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_intr_enable_prog_empty.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_intr_enable_prog_lvl.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_intr_enable_rd_full.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_intr_enable_rd_lvl.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_intr_enable_op_done.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_intr_enable_corr_err.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_exec.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_control_start.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_control_op.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_control_prog_sel.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_control_erase_sel.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_control_partition_sel.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_control_info_sel.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_control_num.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_addr.wr_en_data_arb

SCORELINE
66.67 100.00
tb.dut.u_reg_core.u_erase_suspend.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_en_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_en_0.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_en_0.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_en_0.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_rd_en_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_rd_en_0.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_rd_en_0.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_rd_en_0.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_prog_en_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_prog_en_0.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_prog_en_0.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_prog_en_0.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_erase_en_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_erase_en_0.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_erase_en_0.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_erase_en_0.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_scramble_en_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_scramble_en_0.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_scramble_en_0.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_scramble_en_0.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_ecc_en_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_ecc_en_0.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_ecc_en_0.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_ecc_en_0.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_he_en_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_he_en_0.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_he_en_0.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_he_en_0.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_base_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_base_0.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_base_0.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_base_0.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_size_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_size_0.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_size_0.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_0_size_0.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_en_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_en_1.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_en_1.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_en_1.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_rd_en_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_rd_en_1.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_rd_en_1.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_rd_en_1.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_prog_en_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_prog_en_1.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_prog_en_1.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_prog_en_1.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_erase_en_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_erase_en_1.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_erase_en_1.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_erase_en_1.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_scramble_en_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_scramble_en_1.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_scramble_en_1.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_scramble_en_1.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_ecc_en_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_ecc_en_1.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_ecc_en_1.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_ecc_en_1.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_he_en_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_he_en_1.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_he_en_1.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_he_en_1.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_base_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_base_1.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_base_1.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_base_1.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_size_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_size_1.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_size_1.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_1_size_1.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_en_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_en_2.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_en_2.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_en_2.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_rd_en_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_rd_en_2.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_rd_en_2.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_rd_en_2.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_prog_en_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_prog_en_2.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_prog_en_2.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_prog_en_2.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_erase_en_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_erase_en_2.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_erase_en_2.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_erase_en_2.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_scramble_en_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_scramble_en_2.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_scramble_en_2.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_scramble_en_2.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_ecc_en_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_ecc_en_2.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_ecc_en_2.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_ecc_en_2.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_he_en_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_shadowed_2_he_en_2.staged_reg.wr_en_data_arb

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tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_0_prog_en_0.wr_en_data_arb

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tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_0_scramble_en_0.wr_en_data_arb

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tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_0_scramble_en_0.committed_reg.wr_en_data_arb

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tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_0_ecc_en_0.wr_en_data_arb

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tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_0_ecc_en_0.staged_reg.wr_en_data_arb

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tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_0_ecc_en_0.shadow_reg.wr_en_data_arb

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tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_0_ecc_en_0.committed_reg.wr_en_data_arb

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tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_0_he_en_0.wr_en_data_arb

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tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_0_he_en_0.committed_reg.wr_en_data_arb

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tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_1_en_1.committed_reg.wr_en_data_arb

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tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_1_rd_en_1.wr_en_data_arb

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tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_1_rd_en_1.staged_reg.wr_en_data_arb

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tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_1_ecc_en_1.wr_en_data_arb

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tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_1_ecc_en_1.committed_reg.wr_en_data_arb

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tb.dut.u_reg_core.u_bank1_info2_page_cfg_shadowed_1_he_en_1.wr_en_data_arb

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tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.wr_en_data_arb

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tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.wr_en_data_arb

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tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.staged_reg.wr_en_data_arb

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tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.shadow_reg.wr_en_data_arb

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tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.committed_reg.wr_en_data_arb

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tb.dut.u_reg_core.u_op_status_done.wr_en_data_arb

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tb.dut.u_reg_core.u_op_status_err.wr_en_data_arb

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tb.dut.u_reg_core.u_ecc_single_err_cnt_ecc_single_err_cnt_0.wr_en_data_arb

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tb.dut.u_reg_core.u_ecc_single_err_cnt_ecc_single_err_cnt_1.wr_en_data_arb

SCORELINE
66.67 100.00
tb.dut.u_reg_core.u_phy_err_cfg.wr_en_data_arb

SCORELINE
66.67 100.00
tb.dut.u_reg_core.u_phy_alert_cfg_alert_ack.wr_en_data_arb

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66.67 100.00
tb.dut.u_reg_core.u_phy_alert_cfg_alert_trig.wr_en_data_arb

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tb.dut.u_reg_core.u_scratch.wr_en_data_arb

SCORELINE
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tb.dut.u_reg_core.u_fifo_lvl_prog.wr_en_data_arb

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100.00 100.00
tb.dut.u_reg_core.u_fifo_lvl_rd.wr_en_data_arb

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tb.dut.u_reg_core.u_fifo_rst.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
35 1 1

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=1 + DW=32,SwAccess=1 + DW=20,SwAccess=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_status_rd_full.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_status_rd_empty.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_status_prog_full.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_status_prog_empty.wr_en_data_arb

SCORELINE
66.67 66.67
tb.dut.u_reg_core.u_status_init_wip.wr_en_data_arb

SCORELINE
66.67 66.67
tb.dut.u_reg_core.u_fault_status_oob_err.wr_en_data_arb

SCORELINE
66.67 66.67
tb.dut.u_reg_core.u_fault_status_mp_err.wr_en_data_arb

SCORELINE
66.67 66.67
tb.dut.u_reg_core.u_fault_status_rd_err.wr_en_data_arb

SCORELINE
66.67 66.67
tb.dut.u_reg_core.u_fault_status_prog_win_err.wr_en_data_arb

SCORELINE
66.67 66.67
tb.dut.u_reg_core.u_fault_status_prog_type_err.wr_en_data_arb

SCORELINE
66.67 66.67
tb.dut.u_reg_core.u_fault_status_flash_phy_err.wr_en_data_arb

SCORELINE
66.67 66.67
tb.dut.u_reg_core.u_fault_status_reg_intg_err.wr_en_data_arb

SCORELINE
66.67 66.67
tb.dut.u_reg_core.u_fault_status_phy_intg_err.wr_en_data_arb

SCORELINE
66.67 66.67
tb.dut.u_reg_core.u_fault_status_lcmgr_err.wr_en_data_arb

SCORELINE
66.67 66.67
tb.dut.u_reg_core.u_fault_status_storage_err.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_err_addr.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_ecc_single_err_addr_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_ecc_single_err_addr_1.wr_en_data_arb

SCORELINE
66.67 66.67
tb.dut.u_reg_core.u_phy_status_init_wip.wr_en_data_arb

SCORELINE
33.33 33.33
tb.dut.u_reg_core.u_phy_status_prog_normal_avail.wr_en_data_arb

SCORELINE
33.33 33.33
tb.dut.u_reg_core.u_phy_status_prog_repair_avail.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3711100.00
CONT_ASSIGN3811100.00
CONT_ASSIGN4300